KR20060113305A - Clock buffer in delay locked loop - Google Patents

Abstract

A clock buffer of a delay locked loop(DLL) is provided to secure operation stability of the DLL by preventing abnormal pulsing of a DLL internal clock. A detection part compares a positive external clock with a negative external clock in response to a buffer enable signal. A latch part latches a clock enable signal in response to an output clock of the detection part. A logic assembly part performs logic assembly of the output clock of the detection part and an output signal of the latch part. The latch part comprises a D-flip flop.

Description

Clock buffer of delay lock loop {CLOCK BUFFER IN DELAY LOCKED LOOP}

1 is a block diagram of a register control DLL of a DDR SDRAM according to the prior art.

2 is a circuit diagram of a clock buffer of a DLL according to the prior art.

3 is a timing diagram of the clock buffer of FIG.

4 is a circuit diagram of a clock buffer according to an embodiment of the present invention.

5 is a timing diagram of the clock buffer of FIG.

* Explanation of symbols for the main parts of the drawings

D F / F: D-Flip Flop

cock: DLL internal clock

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly to a clock buffer of a delay locked loop (DLL) applied to a synchronous semiconductor memory device.

The main issue in the recent semiconductor memory field is changing from integration to operating speed. As a result, high-speed synchronous memories such as DDR SDRAM (Double Data Rate Synchronous DRAM) and RAMBUS DRAM are emerging as new topics in the semiconductor memory field.

Synchronous memory refers to a memory that operates in synchronization with an external system clock. Among the DRAMs, SDRAM is the mainstream of the mass production memory market. The SDRAM performs one data access every clock by synchronizing input / output operations to the rising edge of the clock. On the other hand, high-speed synchronous memory such as DDR SDRAM is synchronized not only to the rising edge of the clock, but also to the falling edge (falling edge) input / output operation is possible to access the data twice every clock.

In general, a clock is used as a reference for timing operation in various systems or circuits including a semiconductor memory, and may be used to ensure faster operation without an error.

When a clock input from the outside is used in the internal circuit, a time delay (clock skew) caused by the internal circuit is inevitably generated. In order to compensate for this clock skew, clock synchronization circuits such as PLL and DLL are widely used.

On the other hand, DLL is less noise-affected than the conventional phase locked loop (PLL) has been widely used in synchronous semiconductor memory, including DDR Double Data Rate Synchronous DRAM (SDRAM). In a synchronous semiconductor memory device, the DLL basically receives an external clock to compensate for the delay component of the clock path and reflects the negative delay in advance so that the output of the data is synchronized with the external clock.

1 is a block diagram of a register control DLL of a DDR SDRAM according to the prior art.

Referring to FIG. 1, a register control DLL of a DDR SDRAM according to the related art is configured to generate an internal clock (fall_clk) synchronized with a falling edge of an external clock (clk) by using an inverted external clock (/ clk) as an input. The second clock buffer 12 and the external clock clk for generating the internal clock rise_clk synchronized with the rising edge of the external clock clk using the first clock buffer 11, the external clock clk as an input. Clock clock that outputs delayed clock clock (dly_in) and reference clock (ref) by dividing the internal clock (rise_clk) synchronized to the rising edge of 1) by 1 / n (n is a positive integer, typically n = 8). The first delay line 14 which receives the period 13, the internal clock fall_clk synchronized to the falling edge of the external clock clk, and the internal clock rise_clk synchronized to the rising edge of the external clock clk. 2nd delay line 15 which takes an input as an input, and a 3rd delay line which inputs the delay monitoring clock dly_in as an input. 6), a shift register 17 for determining the delay amount of the first and second third delay lines 14, 15, and 16, and an output ifclk of the first delay line 14 to drive the DLL. A first DLL driver 20 for generating a clock fclk_dll, a second DLL driver 21 for generating a DLL clock rclk_dll by driving an output irclk of the second delay line 15, A delay model 22 configured to receive the output of the third delay line 16 as the input (feedback_dly), and to have the clock (feedback_dly) pass through the same delay condition as the actual clock path, and the output of the delay model 22 and A shift control signal for controlling the shift direction of the shift register 17 in response to the phase comparator 19 for comparing the phases of the reference clock ref and the comparison signal ctrl output from the phase comparator 19. A shift controller 18 for outputting (SR, SL) is provided.

The delay model 22 here includes a dummy clock buffer, a dummy output buffer and a dummy load, also called a replica circuit.

Hereinafter, the operation of the conventional register control DLL configured as described above will be described.

First, the first clock buffer 11 receives the falling edge of the external clock clk to generate a synchronized internal clock fall_clk, and the second clock buffer 12 receives the rising edge of the external clock clk and receives the internal clock. Generate a clock (rise_clk). The clock divider 13 divides the internal clock rise_clk synchronized to the rising edge of the external clock clk by 1 / n to generate a clock (ref, dly_in) that is synchronized with the external clock clk once every nth clock. .

In the initial operation, the delay monitoring clock dly_in passes through only one unit delay element of the third delay line 16 and is output as a feedback_dly clock. The clock is delayed and output as a feedback clock while passing through the delay model 22 again. do.

Meanwhile, the phase comparator 19 compares the rising edge of the reference clock ref, which is a reference clock, with the rising edge of the feedback clock, to generate a comparison signal ctrl, and the shift controller 18 responds to the comparison signal ctrl. To output shift control signals SR and SL for controlling the shift direction of the shift register 17. The shift register 17 determines the delay amounts of the first, second and third delay lines 14, 15, and 16 in response to the shift control signals SR and SL. At this time, if a shift right (SR) is input, the register is shifted to the left, and if a shift left (SL) is input, the register is shifted to the right. Subsequently, as the delay amount is compared with the controlled feedback clock and the reference clock ref, delay locking is performed at the moment when the two clocks have the minimum jitter, and the first and second DLL drivers ( The DLL clocks fclk_dll and rclk_dll output from 20 and 21 have the same phase as the external clock clk.

2 is a circuit diagram of a clock buffer of a DLL according to the prior art.

Referring to FIG. 2, a clock buffer of a DLL according to the related art includes a detector (NMOS type differential amplifier circuit) for comparing a positive external clock eclk and a negative external clock eclkb in response to a buffer enable signal. And the output signal of the inverter INV2 and the output clock of the inverter INV2. The inverter INV1 inputs the output signal of the detector and the output clock clock1 of the inverter INV1. A transmission gate TG1 for selectively outputting the clock enable signal Clk_enb under the control of the inverter INV3, the output clock clock1 of the inverter INV1, and an output signal of the transmission gate TG1. And a NAND gate NAND1 for outputting an internal clock of the DLL by inputting the inverter INV5, the output clock clockb of the inverter INV3, and the output signal Clk_en of the inverter INV5. do.

3 is a timing diagram of the clock buffer of FIG. 2, which will be described below with reference to the diagram.

Referring to the clock buffer of the DLL illustrated in FIG. 2, it can be seen that the clock enable signal Clk_enb, which controls the power down mode, is input through the transmission gate TG1. This is to reduce unnecessary current consumption by toggling the clock. The clock enable signal Clk_en passing through the inverter INV5 is combined with the output clock clockb of the inverter INV3 to generate an internal clock of the DLL.

On the other hand, the clock enable signal Clk_enb is an asynchronous parameter rather than a synchronous parameter synchronized with the clock edge. Therefore, if the output clock Cb_en of the inverter INV3 and the output signal Clk_en of the inverter INV5 meet at the time of exiting the power-down mode of FIG. 3, the internal clock of the DLL output from the NAND gate NAND1. Abnormal pulses may occur. 'a' is the delay from the falling edge of clock signal clock1 to the rising edge of clock enable signal Clk_en passing through inverter INV5, and 'b' is the falling edge of clock signal clockb from the falling edge of clock signal clock1. Delays up to, respectively, show a relationship of 'a' <'b' to cause abnormal pulsing.

If such an abnormal clock enters the DLL, it causes a serious error in the operation of the DLL.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a clock buffer of a fixed delay loop that can prevent abnormal clock generation at the time of exiting the power-down mode.

According to an aspect of the present invention for achieving the above technical problem, a detection unit for comparing the positive external clock and the negative external clock in response to the buffer enable signal; A latch unit for latching a clock enable signal in response to an output clock of the detector; And a logic combining section for logically combining the output clock of the detection section and the output signal of the latch section.

Here, the latch unit is preferably implemented as a D-flip flop.

Preferably, the logic combination section includes a NAND gate for inputting an output clock of the detector section and an output signal of the latch section.

In the present invention, a latch circuit having a clock synchronization function is used without a transmission gate as in the related art in order to transfer a clock enable signal that controls a power-down mode into a clock buffer. Latch circuits with clock synchronization can be implemented simply with D-flip flops. In this case, the power down mode exit time is synchronized with the clock in the clock buffer to prevent abnormal clock generation.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

4 is a circuit diagram of a clock buffer according to an embodiment of the present invention.

Referring to FIG. 4, the clock buffer of the DLL according to the present embodiment is a detector (NMOS type differential) for comparing the positive external clock eclk and the negative external clock eclkb in response to a buffer enable signal. Implemented with an amplifying circuit), an inverter INV11 for inputting an output signal of the detector, an inverter INV12 for inputting an output clock clock1 of the inverter INV11, and an output clock of the inverter INV12. D-flip flop (DF / F) and D-flip flop (DF / F) for latching the clock enable signal Clk_enb in response to the inverter INV13 serving as an input, the output clock clock1 of the inverter INV1. And a NAND gate NAND11 for outputting the internal clock of the DLL by inputting the output signal Clk_en of / F and the output clock (clockb) of the inverter INV3.

FIG. 5 is a timing diagram of the clock buffer of FIG. 4, which will be described with reference to the following.

Referring to the clock buffer of the DLL illustrated in FIG. 4, it can be seen that the clock enable signal Clk_enb, which controls the power-down mode, is latched at the falling edge of the clock signal clock1.

The output signal Clk_en of the D-flip flop D F / F is combined with the output clock b of the inverter INV13 to generate an internal clock of the DLL.

As mentioned above, the clock enable signal Clk_enb is an asynchronous parameter, not a synchronous parameter. However, in the present embodiment, the clock enable signal Clk_enb is input through the D-flip-flop DF / F. Will be recognized.

Thus, as shown in FIG. 5, a relationship 'a' delay is always greater than 'b' delay ('a'> 'b'), thereby preventing abnormally pulsing the DLL clock. have. Here, 'a' is the delay from the falling edge of clock signal clock1 to the rising edge of output signal Clk_en of D-flip-flop (DF / F), and 'b' is the clock signal clockb from the falling edge of clock signal clock1. Delays to the falling edges are shown.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

For example, in the above-described embodiment, the case of a register control DLL has been described as an example, but the present invention can be applied to a DLL of any control method using a clock buffer.

In addition, the inverter and the logic gate used in the above-described embodiment need to be changed according to the active level of the signal.

The present invention as described above can prevent abnormal pulsing of the DLL internal clock to ensure the stability of the operation of the DLL, and further can block the possibility of causing the entire operation failure of the chip in advance.

Claims (3)

A detector configured to compare the positive external clock and the negative external clock in response to the buffer enable signal; A latch unit for latching a clock enable signal in response to an output clock of the detector; And Logic combiner for logically combining the output clock of the detector and the output signal of the latch A delay buffer loop clock buffer having a. The method of claim 1, And the latch portion includes a D-flip flop. The method according to claim 1 or 2, And said logic combination section comprises a NAND gate for inputting an output clock of said detection section and an output signal of said latch section.

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