KR20060113277A - Method for forming a copper metal in semiconductor device - Google Patents

Abstract

A method for forming a copper interconnection of a semiconductor device is provided to simplify manufacturing process by simultaneously polishing a copper film and a barrier layer using the same slurry. A substrate(110) having an insulating layer(111) is prepared. A trench is formed by etching the insulating layer. A barrier layer(112) is deposited on the resultant structure. A copper film(113) is then filled in the trench. The copper film and the barrier layer are sequentially and simultaneously polished by using slurry of polycarboxylate group and a silica particle.

Description

Copper wiring formation method of semiconductor device {METHOD FOR FORMING A COPPER METAL IN SEMICONDUCTOR DEVICE}

1 is a front sectional view showing a general CMP apparatus.

2A to 2C are cross-sectional views illustrating a method for forming copper wirings of a semiconductor device according to the prior art.

3A and 3B are cross-sectional views illustrating a method of forming copper wirings in a semiconductor device according to a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 110: semiconductor structure layer

11, 111: insulating film

12, 112: barrier film

13, 113: copper layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming copper wiring of a semiconductor device, and more particularly, to a method of planarizing copper wiring using a chemical mechanical polishing process.

BACKGROUND ART In recent years, with the increase in the speed and the high integration of semiconductor devices, there is an increasing demand for increasing the number of wiring layers and miniaturization of wiring patterns in a multilayer wiring structure, so that multilayer wiring technology is an important problem in the submicron process. In particular, as the process margin with respect to the depth of focus of the exposure apparatus for realizing fine pattern formation is reduced while entering a process age of 0.15 μm or less, a wide area planarization technique is required over the chip region to secure sufficient depth of focus.

In order to realize such a planar flattening, chemical mechanical polishing (CMP) technology is currently applied to a semiconductor device manufacturing process. For example, the CMP technology is not only applied to logic devices that require multi-layered wiring for realizing high speed, but also to memory devices.

1 is a front sectional view illustrating a general CMP apparatus and its operation principle.

As shown in FIG. 1, when the wafer W is first clamped by the head 1, the head 1 is moved above the pad 5 to polish the wafer W on the top surface of the pad 5. Make sure the sides are in close contact. At this time, the pad 5 is installed on the upper side of the support 7 is supported by the support (7). Thereafter, the head 1 and the support 7 are rotated by the respective rotation shafts 3 and 9 in the same direction (or in different directions) and at different speeds, so that the contact surface of the polishing surface of the wafer W and the pad 5 is rotated. A frictional force due to the relative speed between the head 1 and the pad 5 is generated between the wafers W to polish.

The CMP technology is also applied to a copper wiring forming process of a semiconductor device using a dual damascene process or a single damascene process.

2A through 2C are cross-sectional views illustrating a copper wiring forming process of a semiconductor device using a CMP technique according to the prior art. For convenience of description, a process of forming a copper wiring of a semiconductor device to which a single damascene process is applied will be described.

First, as shown in FIG. 2A, a trench or via hole (not shown) is formed by depositing an insulating layer 11 on the semiconductor structure layer 10 and then performing a single damascene process. . Then, a barrier layer 12 is deposited on the Ta / TaN laminated film along the steps above the entire structure including the trench. The copper layer 13 is then deposited over the entire structure including the barrier film 12 so that the trench is completely embedded.

Subsequently, as illustrated in FIGS. 2B and 2C, the CMP processes 14 and 15 using different slurries are sequentially performed to polish the copper layer 13 and the barrier layer 12. As a result, an isolated copper wiring is formed in the trench.

As described above, in the method of forming a copper wiring of a semiconductor device according to the related art, the copper layer 13 is first planarized using a copper polishing slurry, and the slurry is changed to polish the barrier film 12. That is, the CMP process is performed using different slurries in the copper wiring forming process.

In order to use the two types of slurry in the copper wiring forming process, a dedicated polishing pad must be used for each slurry in the polishing equipment, and a slurry supply device must be separately provided. In addition, the use of two types of slurry not only significantly reduces the throughput of the equipment, but also requires a lot of problems in terms of process cost, such as the compatibility of each slurry, that is, an appropriate combination of slurry to minimize defects. Occurs.

Therefore, the present invention has been proposed to solve the above problems of the prior art, and a method for forming a copper wiring of a semiconductor device capable of simultaneously polishing a copper layer and a barrier film using the same slurry without using two kinds of slurries. The purpose is to provide.

According to an aspect of the present invention, there is provided a substrate including an insulating film formed thereon, etching the insulating film to form a trench, and forming a barrier along an upper level of an entire structure including the trench. Depositing a film, depositing a copper layer on the barrier layer so that the trench is embedded, and using the polycarboxylate-based slurry for polishing copper and silica abrasive particles, the copper layer and the barrier Provided is a method for forming a copper wiring in a semiconductor device comprising the step of simultaneously polishing a film continuously.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

Example

3A and 3B are cross-sectional views illustrating a method for forming a copper wiring of a semiconductor device according to a preferred embodiment of the present invention.

First, as shown in FIG. 3A, a semiconductor structure layer 110 is formed on a semiconductor substrate (not shown). In this case, the semiconductor structure layer 110 may include at least one of a photo diode, a transistor, a memory cell, a capacitor, a resistor, an inductor, a junction layer, a metal layer, and an insulating layer. Can be done.

Next, an insulating layer 111 is deposited on the semiconductor structure layer 110. At this time, the insulating film 111 is formed of an oxide film containing any one of impurities such as C, F, B, P, and In in the SiO or SiO ₂ film. For example, Boron Phosphorus Silicate Glass (BPSG), Phosphorus Silicate Glass (PSG), Un-doped Silicate Glass (USG), Fluorinated Silicate Glass (FSG), and the like. In addition, the insulating film 11 may be formed of a single layer made of any one of these oxide films, or may be formed in a stacked structure in which at least two or more of these films are stacked.

A single damascene process is then performed to form trenches (not shown). Instead of the single damascene process, the dual damascene process may be carried out in a pre-via or post-via manner.

Subsequently, the barrier layer 112 is formed along the stepped portion of the entire structure including the trench. At this time, the barrier film 112 is formed of a single layer of any one of Ta, TaN, TaC, TaAlN, TaSiN, TaSi ₂ , Ti, TiN, TiSiN, WN, WBN, WC, Co, and CoSi ₂ , or at least 2 It is formed by a laminated structure in which more than one layer is laminated. For example, in the case of a laminated structure, it is formed of a Ti / TiN, Ta / TaN film. At this time, the Ti film or Ta film functions as a glue layer because the adhesion of the TiN film or TaN film is low and the adhesion to the lower layer is reduced. The barrier film 112 is formed to have a thickness of 250 mW to 350 mW, preferably 300 mW. The barrier film is deposited by PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition).

Subsequently, a copper layer 113 is deposited on the barrier layer 112 to fill the trench. At this time, the copper layer 113 is formed by a CVD method, an ALD method or an electroplating method.

Subsequently, as illustrated in FIG. 3B, the CMP process 114 is performed to continuously polish the copper layer 113 and the barrier film 112. As a result, the copper layer 113 and the barrier film 112 are simultaneously polished.

Here, the CMP process 114 uses a polycarboxylate-based slurry for copper polishing, and uses silica (SiO ₂ ) as abrasive particles. At this time, the content of the abrasive is 2wt% to 10wt%. Thereby, the polishing rate of the copper layer 113 can be controlled to 15000 kPa / min to 20000 kPa / min, and the polishing selectivity with the barrier film 112 can be 50: 1. As such, when the polishing selectivity is 50: 1, the polishing rate of Ta is close to 300 kPa / min to 400 kPa / min. The copper polishing slurry uses hydrogen peroxide (H ₂ O ₂ ) as the oxidizing agent.

In the CMP process 114, the copper layer 113 and the barrier layer 112 may be polished using the same pad or may be polished using different pads. In the latter case, the barrier film 112 is preferably polished using a soft pad to reduce defects. Here, the soft pad is used as a hard pad for polishing the copper layer 113, for example, a pad much softer than a polyurethane-based pad. Such a soft pad is used directly in the polishing of the barrier metal film 112 during the touch polishing process or in order not to further perform the final touch polishing to remove defects of the wafer polished in the final CMP process.

In addition, in order to minimize dishing and erosion of the insulating layer 111 during the CMP process 114, the copper layer 113 is preferentially polished at a high polishing rate, and then the polishing rate is decreased to thereby retain the remaining copper layer. The 113 and the barrier film 112 are polished continuously. In this case, an EPD (End Point Detector) is applied to change the polishing speed, and the EPD measures a material to be polished using a light source, a eddy current, or a motor current.

The above-mentioned EPD is a system for detecting a material to be polished by detecting a degree of reflection by scanning a laser or white light or the like. The eddy current method uses an induction current to measure the thickness of the metal.The magnetic field induction mechanism is installed in the mechanical device under the polishing pad, and then the magnetic field is changed when the conductive thin film (here, copper layer) is polished. By measuring the thickness of the copper changes the magnetic field changes. On the other hand, the method using the motor current is a method of using a current flowing through the motor for driving the polishing device, such as a platen rotating motor, the head rotating motor, the motor current according to the difference in friction between the pad and the wafer depending on the material to be polished Will fluctuate. In other words, by measuring these motor currents, the material to be polished can be determined.

In addition, after the barrier film 112 is polished, a buffing process may be performed using a separate soft pad to reduce defects. In the buffing process, silica having an insulating film 111 polishing rate of at least 500 kW / min or more may be used. It is carried out using a slurry containing abrasive particles.

The process as described above completes the isolated copper wiring inside the trench.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the copper layer and the barrier film are continuously and simultaneously polished using a polycarboxylate-based copper polishing slurry and silica abrasive grains during the copper wiring forming process using the damascene process. As a result, a separate barrier film polishing slurry is not required, thereby reducing the number of slurry supply equipments, and also greatly increasing the number of processed wafers per equipment in a polishing apparatus.

Further, according to the present invention, by simultaneously polishing the copper layer and the barrier film, it is possible to proceed with the concept of only increasing the productivity of the wafer in the equipment, as in the case of the oxide film CMP process or the tungsten CMP process, in which case the productivity is greatly increased. It can increase.

Further, according to the present invention, the problem of corrosion of copper can be solved by continuously polishing the copper layer and the barrier film using the same copper polishing slurry. For reference, in the related art, as the polishing process is performed using two kinds of slurries, the polishing time between the copper polishing process and the barrier film polishing process is greatly different, which causes a problem of corrosion of copper. However, this problem can be solved by simultaneously polishing the copper layer and the barrier film using only one type of copper polishing slurry as in the present invention.

Moreover, according to this invention, a process can be simplified by continuously grind | polishing a copper layer and a barrier film using the same copper polishing slurry. For reference, in the case of performing a polishing process using two kinds of slurries as in the prior art, in a polishing apparatus having three polishing pads, the copper layer is generally polished using the first and second pads, and the barrier using the third pad. The film was polished and much effort was also required to keep the polishing time equal for each pad to prevent copper corrosion.

Claims (13)

Providing a substrate having an insulating film formed thereon; Etching the insulating layer to form a trench; Depositing a barrier film along a step above the entire structure including the trench; Depositing a copper layer on the barrier layer to fill the trench; And Continuously polishing the copper layer and the barrier layer using a polycarboxylate-based copper polishing slurry and silica abrasive particles Copper wiring forming method of a semiconductor device comprising a. The method of claim 1, The copper polishing slurry is a copper wiring forming method of a semiconductor device containing 2wt% to 10wt% abrasive. The method according to claim 1 or 2, And a polishing selectivity ratio between the copper layer and the barrier layer in the polishing process is 50: 1. The method of claim 3, wherein And a polishing rate of the copper layer in the polishing step is 15000 kW / min to 20000 kW / min. The method according to claim 1 or 2, The copper polishing slurry is a copper wiring forming method of a semiconductor device using hydrogen peroxide (H ₂ O ₂ ) as an oxidizing agent. The method according to claim 1 or 2, In the polishing step, the copper layer and the barrier film is polished using the same pad, or using a different pad to polish the copper wiring formation method of a semiconductor device. The method of claim 6, The method for forming copper wirings of a semiconductor device, wherein the barrier layer is softer than the pad for polishing the copper layer when the copper layer and the barrier layer are polished using different pads during the polishing process. The method according to claim 1 or 2, And polishing the barrier layer by slowing down the polishing rate of the copper layer after polishing the copper layer during the polishing step. The method of claim 8, An end point detector is applied to reduce the polishing speed, and the end point detector uses a light source, a eddy current, or a motor current. The method according to claim 1 or 2, And polishing the copper layer and the barrier layer, and performing a buffing process using a soft pad that is softer than a pad polished with the copper layer. The method of claim 10, And the buffing step is performed using a slurry containing silica abrasive particles having an insulating film polishing rate of at least 500 kW / min. The method according to claim 1 or 2, The barrier film is formed of a single layer of any one of Ta, TaN, TaC, TaAlN, TaSiN, TaSi ₂ , Ti, TiN, TiSiN, WN, WBN, WC, Co, and CoSi ₂ , or a laminate in which at least two or more of them are stacked. Copper wiring formation method of a semiconductor element formed in a structure. The method of claim 12, The barrier film is a copper wiring forming method of a semiconductor device to form a thickness of 250 ~ 350Å.

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