KR20060104594A - Synchronous dram cell sram having recovery delay time from refresh to normal access and operating method thereof - Google Patents

Abstract

A synchronous DRAM cell SRAM in which a return delay time from refreshing to normal access is controlled and a driving method thereof are disclosed. The synchronous DRAM cell SRAM of the present invention includes a clock synchronous unit that generates a clock synchronous signal that is activated after a clock of the number of return clocks of the external clock signal has elapsed with respect to deactivation of the refresh driving signal. The return clock number is controlled by a setting signal provided from the outside. According to the synchronous DRAM cell SRAM of the present invention and its driving method, the return delay time is controlled corresponding to the operating frequency, and the overall operating speed is improved.

SRAM, DRAM Cell, Refresh, Clock, Sync, Return Delay

Description

SYNCHRONOUS DRAM CELL SRAM HAVING RECOVERY DELAY TIME FROM REFRESH TO NORMAL ACCESS AND OPERATING METHOD THEREOF}

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram illustrating a synchronous DRAM cell SRAM according to an embodiment of the present invention.

2 is a view showing in detail the clock synchronization unit of FIG.

3 is a block diagram illustrating in detail the refresh control unit of FIG. 1.

4 is a diagram illustrating in detail the refresh request signal generator of FIG. 1.

5 is a timing diagram illustrating a method of driving a synchronous DRAM cell SRAM according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous semiconductor memory device, and more particularly, to a synchronous DRAM cell SRAM having a dynamic random access memory (DRAM) cell and compatible with a static random access memory (SRAM) and its driving. It is about a method.

In general, random access memory (RAM) in a synchronous semiconductor memory device is classified into a synchronous SRAM and a synchronous DRAM. The RAM consists of a memory array having a plurality of unit memory cells arranged on a matrix composed of rows and columns, and a peripheral circuit that controls input / output of data to / from the unit memory cells. The unit memory cell for storing one bit of information used for SRAM is implemented by four transistors forming a latch structure and two transistors serving as a transfer gate. That is, since the conventional SRAM stores data in unit memory cells having a latch structure, a refresh operation for storing data is not required. In addition, SRAM has advantages such as faster operation speed and lower power consumption than DRAM.

However, since SRAM unit memory cells are implemented with six transistors, SRAM has disadvantages in terms of required wafer area compared with DRAMs in which unit memory cells are implemented with one transistor and one capacitor. That is, in order to manufacture memory elements having the same capacity, the wafer area of SRAM is about 6 to 10 times the wafer area of DRAM. As such, the required area of the SRAM increases the unit price of the SRAM. If a conventional DRAM is used in place of SRAM for cost reduction, the DRAM controller should be additionally installed due to periodic refresh. In addition, the overall performance of the system itself is reduced because of the time required for the periodic refresh operation of the DRAM and the slow operation speed.

In order to overcome the drawbacks of DRAM and SRAM as described above, efforts to implement SRAM (hereinafter, referred to as `` synchronous DRAM DRAM SRAM '') which is synchronized with an external clock signal as an SRAM using a DRAM cell continue. It is becoming. One such effort is to hide the refresh operation externally, making it compatible with SRAM.

In the conventional synchronous DRAM cell SRAM, the delay time from the refresh execution to the return to the normal access operation (hereinafter, referred to as a "return delay time") is mainly defined by the delay time of the internal delay circuit. In such a synchronous DRAM cell SRAM, the return delay time is constant regardless of the operating frequency (period). That is, in the conventional synchronous DRAM cell SRAM, the return delay time is still constant even when operating at a large frequency. Therefore, in the conventional synchronous DRAM cell SRAM, a problem occurs that the overall operation speed is lowered.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronous DRAM cell SRAM and a driving method thereof, by which a return delay time is controlled corresponding to an operating frequency, thereby improving the overall operating speed.

One aspect of the present invention for solving the above technical problem relates to a synchronous DRAM cell SRAM. In order to effectively preserve the stored data, the synchronous DRAM cell SRAM of the present invention includes a plurality of DRAM cells, each of which requires a refresh operation to amplify and rewrite the stored data within a predetermined refresh period. In an exemplary embodiment, an operation section for performing the refresh may be interfaced with an external system that is not active, and may be synchronized with an external clock signal. The synchronous DRAM cell SRAM of the present invention includes a memory array including the plurality of DRAM cells arranged on a matrix structure defined by rows and columns; A word line driver driven to specify a row of the memory array according to a predetermined refresh address in a refresh operation mode, the word line driver recovering normal access in response to activation of a predetermined normal recovery signal; A column selector driven to specify a column of the memory array according to a column address provided from the outside; A clock synchronous unit which generates a clock synchronous signal which is activated after a clock of the number of the return clocks of the external clock signal has elapsed with respect to deactivation of a predetermined refresh drive signal, wherein the number of the return clocks is set by an externally provided setting signal. The clock synchronization unit being controlled; A refresh request signal generator for generating a refresh request signal activated at a predetermined cycle; A refresh control unit for driving the refresh request signal to generate the refresh driving signal, the refresh control unit activating the normal recovery signal in response to the clock synchronization signal; And a refresh address generator for providing the refresh address to the word line driver in response to the refresh drive signal.

Another aspect of the present invention for solving the other technical problem as described above relates to a method for driving a synchronous DRAM cell SRAM of the present invention. Method of driving the synchronous DRAM SRAM of the present invention comprises the steps of receiving a setting signal from the outside; Activating a refresh request signal requesting to perform the refresh; And enabling the refresh request signal by activating the refresh request signal and performing a refresh during the clock count of the external clock signal corresponding to a predetermined return clock number after the enable request. The return clock number is controlled by the setting signal.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings. In understanding the drawings, it should be noted that like parts are intended to be represented by the same reference numerals as much as possible. Incidentally, detailed descriptions of well-known functions and configurations that are determined to unnecessarily obscure the subject matter of the present invention will be omitted.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The synchronous DRAM cell SRAM of the present invention employs a DRAM cell internally and a refresh operation is performed, but externally, an operation section for refreshing is not allocated externally like a synchronous DRAM. In addition, the synchronous DRAM cell SRAM of the present invention does not require a separate control signal for controlling the refresh operation from the outside, and may be driven externally by the same rules as a conventional synchronous SRAM (SRAM).

The synchronous DRAM cell SRAM of the present invention performs a refresh (REFRESH) operation. The refresh operation is an operation of activating a specific word line, outputting data of all DRAM cells connected to the word line from the DRAM cell, and then amplifying and writing the data again.

The synchronous DRAM cell SRAM of the present invention is driven in synchronization with an external clock signal.

1 is a block diagram illustrating a synchronous DRAM cell SRAM according to an embodiment of the present invention. Referring to FIG. 1, the synchronous DRAM cell SRAM of the present invention includes a memory array 100, a word line driver 200, a column selector 300, a clock synchronizer 400, a refresh controller 500, and a command input unit. 600, a refresh address generator 700, a refresh request signal generator 800, a normal blocking unit 900, and a data input / output unit 1000.

The memory array 100 includes a plurality of DRAM cells arranged on a matrix defined by rows and columns. The DRAM cell is a cell requiring refreshing within a predetermined refresh period in order to effectively preserve stored data. The DRAM cells form a memory array of DRAMs. The DRAM cell, as is well known, is implemented with a transfer transistor gated by a word line and a capacitor that stores data of a bit line transmitted through the transfer transistor.

The word line driver 200 specifies a row of the memory array 100 according to the refresh address FADD in the refresh mode and is driven to activate the word line WL of the specified row. The refresh address FADD is provided from the refresh address generator 700 in the refresh mode. The word line driver 200 may perform normal access again by activating the normal recovery signal NRC generated by the refresh controller 500 to "H".

In the normal mode, the word line driver 200 specifies a row of the memory array 100 according to a low address RADD provided from the outside, and activates the word line WL of the specified row. Driven.

The column selector 300 generates a column select signal CSL that is driven to specify a column of the memory array 100 by a column address CADD provided from the outside.

The clock synchronous unit 400 provides a predetermined clock synchronous signal CSEN. The clock synchronous signal CSEN is activated after the return clock of the external clock signal CLK has elapsed with respect to the deactivation of the refresh driving signal REF. Here, the number of return clocks is controlled by a setting signal SET provided from the outside. Preferably, the setting signal SET is a column latency signal CL that specifies column latency.

In this embodiment, the "return delay time" which is the delay time from the refresh execution to the return to the normal access operation is controlled by the return clock number.

FIG. 2 is a diagram illustrating the clock synchronizer 400 of FIG. 1 in detail. Referring to FIG. 2, the clock synchronizer 400 includes a refresh response unit 410, a latch unit 420, a counter 430, and a setting comparison unit 440. The logic unit 450 and the reset control unit are provided. Means 460 are further provided.

The refresh response means 410 sets the initial terminal NINI in response to the deactivation of the refresh driving signal REF. That is, when the refresh driving signal REF transitions to "L", the terminal N411 gating the NMOS transistor 412 is generated with an "H" pulse, and the initial terminal NINI is the ground voltage VSS. Is controlled.

The latch means 420 reverse latches the signal of the initial terminal NINI. The counter 420 is enabled by the output signal N421 of the latch means 420 generated in response to the deactivation of the refresh driving signal REF to " L ". The counter 430 counts the number of clocks of the external clock signal CLK generated after enabling the counter 430 to provide a predetermined counting signal CNT.

The setting comparison means 440 compares the counting signal CNT with the setting signal SET and ultimately activates the clock synchronization signal CSEN. That is, when the number of clocks of the external clock signal CLK generated after the enable of the counter 430 corresponds to the 'return clock number' of the output signal N441 of the setting comparison means 440, Is activated with "H". The logic means 450, when the output signal N421 of the setting comparison means 440 is in the "H" state, in response to the external clock signal CLK, the logic synchronous signal CSEN is "H". "To activate it. Therefore, the clock synchronous signal CSEN is activated as "H" when the number of clocks of the external clock signal CLK generated after the enable of the counter 430 corresponds to the 'return clock number'.

The reset control means 460 controls the signal of the initial terminal NINI to a logic " H " in response to the activation of the clock synchronous signal CLK. At this time, the counter 430 is disabled.

Referring back to FIG. 1, the refresh control unit 500 generates a refresh driving signal REF for driving the refresh of the memory array 100. The refresh drive signal REF is activated in response to a pulse of the clock synchronous signal CSEN generated during the activation of the leaf refresh request signal REQ provided from the refresh request signal generating means 800. In the state where the refresh driving signal REF is activated as "H", the row address selecting means 210 of the word line driver 200 replaces the row address RADD provided from the outside, and thus the refresh address FADD. To the select address SADD. When the refresh driving signal REF is deactivated to "L", the selection address SADD corresponding to the row address RADD is provided.

3 is a block diagram illustrating in detail the refresh control unit 500 of FIG. 1. Referring to FIG. 3, the refresh control unit 500 includes a clock synchronous response unit 510, a response pulse generating unit 520, a pulse expansion unit 530, and a normal recovery unit 560. The clock synchronous response means 510 transitions the response terminal signal NRES to a logic "L" in response to activation of the clock synchronous signal CSEN provided by the clock synchronous unit 400 to "H".

The response pulse generating means 520 provides a response pulse signal RPUL generated as a pulse having a predetermined activation width in response to the transition of the response terminal signal NRES to " L ". At this time, the response pulse signal RPUL has an activation width depending on the delay time by the delay circuit 521 of the response pulse generating means 520.

The pulse expansion means 530 is enabled in response to the refresh request signal REQ provided from the refresh request signal generator 800. The pulse expansion means 530 generates the refresh driving signal REF in response to the response pulse signal RPUL. Preferably, the refresh driving signal REF has an activation width extended to the response pulse signal RPUL.

The normal recovery means 560 generates a normal recovery signal NRC. The normal recovery signal NRC is activated by a pulse of logic "H" in response to the response pulse signal RPUL generated in an inactive state of logic "L" of the refresh drive signal REF. Therefore, the normal recovery signal NRC is deactivated by the logic " L " of the refresh driving signal REF, and the clock of the clock signal CLK corresponding to the number of return clocks set by the setting signal SET is reduced. After elapsed, a pulse of logic "H" is generated.

According to a preferred embodiment, the refresh control unit 500 further includes an initialization means 570 and an active response means 580. The initialization means 570, when the synchronous DRAM cell SRAM of the present invention is powered up, the response terminal signal (NRES) is referred to as the logic "H" (in this specification, "second logic state") Control).

The active response means 580 controls the response terminal signal NRES to the ground voltage VSS in response to an active signal ACT activated when the synchronous DRAM cell SRAM of the present invention enters the active mode. do. Therefore, when the synchronous DRAM cell SRAM of the present invention enters the active mode, the refresh is driven.

Referring back to FIG. 1, the command input unit 600 generates an active signal generated by an "H" pulse when the DRAM cell SRAM of the present invention is driven in an active mode according to an externally supplied control command CMD. ACT). The command input unit 400 supplies write / read control signals WR / RD to the data input / output unit 1000 according to the control command CMD. The data input / output unit 1000 performs a write / read access operation on the memory array 100 according to an active signal ACT and the write / read control signals WR / RD. The word line driver 200 and the column selector 300 also receive the write read control signals WR / RD to identify the DRAM cell of the memory array 100 according to a write / read access operation. Is driven to. In addition, the active signal ACT is also provided to the refresh control unit 500.

The refresh address generator 700 provides the refresh address FADD to the row address selector 210 of the word line driver 200 in response to the refresh drive signal REF.

The synchronous DRAM cell SRAM of the present invention includes a refresh request signal generator 800. The refresh request signal REQ generated by the refresh request signal generator 800 is activated at regular intervals.

4 is a diagram illustrating in detail the refresh request signal generator 800 of FIG. 1. The refresh request signal generator 800 includes a refresh oscillator 810 and a refresh request signal generator 830. The refresh oscillator 810 generates an oscillation signal OSC that is activated at a predetermined cycle. The refresh request signal generating means 830 generates the refresh request signal REQ. The refresh request signal REQ is activated in response to the oscillation signal OSC, and is deactivated with a constant delay time in response to the refresh drive signal REF.

Specifically, the refresh request signal generating means 830 includes an NMOS transistor 831, a latch circuit 833, an inverted delay pulse circuit 835, and a PMOS transistor 837.

The NMOS transistor 831 is gated by the oscillation signal OSC. Therefore, the refresh request signal REQ, which is an output signal of the latch circuit 833, is latched at " L " when the oscillation signal OSC is activated at " H ".

The inversion delay pulse circuit 835 generates an output signal N836 generated with an "L" pulse after a predetermined delay time in response to the activation of the refresh driving signal REF to "H". The PMOS transistor 837 is gated in response to the output signal N836 of the inversion delay pulse circuit 835. Therefore, the refresh request signal REQ, which is an output signal of the latch circuit 833, is deactivated again to " L " after a predetermined time elapses from the activation of the refresh drive signal REF to " H ".

Referring back to FIG. 1, the normal blocking unit 900 generates a normal blocking signal NRA. The normal blocking signal NRA is activated to "H" in response to the refresh driving signal REF and is deactivated to "L" in response to the normal recovery signal NRC. The word line driver 200 specifies a row of the memory array 100 according to the refresh address FADD when the normal blocking signal NRA is activated as “H”. In the state where the normal blocking signal NRA is deactivated to "L", a row of the memory array 100 according to the external address RADD is specified.

Subsequently, a refresh method in the synchronous DRAM cell SRAM of the present invention is described.

5 is a timing diagram illustrating a method of driving a synchronous DRAM cell SRAM according to the present invention. At a time point t11, in the state where the refresh request signal REQ is activated to " H ", the active signal ACT is generated with an " H " pulse. At this time, the refresh driving signal REF is activated as "H". Subsequently, in response to the refresh driving signal REF, the word line WL corresponding to the refresh address FADD is activated. In addition, in response to the refresh driving signal REF, the normal blocking signal NRA is also activated.

At a time point t12 after a predetermined time elapses, the refresh driving signal REF is deactivated to "L", and the refresh word line WL is also deactivated.

Then, the clock synchronous signal CSEN is generated as a pulse at a time point t13 when the return clock number RVCK (2 in this embodiment) has elapsed. In addition, in response to the clock synchronizing signal CSEN, the normal blocking signal NRA is also deactivated to "L". The synchronous DRAM cell SRAM of the present invention may also perform a normal access operation in synchronization with the clock signal CLK.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

The synchronous DRAM cell SRAM of the present invention as described above includes a clock synchronous unit for generating a clock synchronous signal that is activated after a clock of the number of return clocks of the external clock signal has elapsed with respect to deactivation of the refresh driving signal. The return clock number is controlled by a setting signal provided from the outside. According to the synchronous DRAM cell SRAM of the present invention and its driving method, the return delay time is controlled corresponding to the operating frequency, and the overall operating speed is improved.

Claims (9)

In order to effectively preserve the stored data, each of the DRAM cells includes a plurality of DRAM cells that are required to perform a refresh operation for amplifying and rewriting the stored data within a predetermined refresh period, and an operation section for performing the refresh externally. In a synchronous DRAM cell SRAM that can be interfaced with an unacceptable external system and synchronized to an external clock signal, A memory array including the plurality of DRAM cells arranged on a matrix structure defined by rows and columns; A word line driver driven to specify a row of the memory array according to a predetermined refresh address in a refresh operation mode, the word line driver recovering normal access in response to activation of a predetermined normal recovery signal; A column selector driven to specify a column of the memory array according to a column address provided from the outside; A clock synchronous unit which generates a clock synchronous signal which is activated after a clock of the number of the return clocks of the external clock signal has elapsed with respect to deactivation of a predetermined refresh drive signal, wherein the number of the return clocks is set by an externally provided setting signal. The clock synchronization unit being controlled; A refresh request signal generator for generating a refresh request signal activated at a predetermined cycle; A refresh control unit for driving the refresh request signal to generate the refresh driving signal, the refresh control unit activating the normal recovery signal in response to the clock synchronization signal; And And a refresh address generator for providing the refresh address to the word line driver in response to the refresh drive signal. The method of claim 1, wherein the clock synchronization unit Refresh response means for setting a predetermined initial terminal in response to activation of the refresh drive signal; Latch means for latching a signal of the initial terminal; A counter that is enabled by an output signal of the latch means generated according to the activation of the refresh driving signal, and provides a predetermined counting signal by counting the number of clocks of the external clock signal generated after the enable; And Comparing the counting signal with the setting signal, and setting setting means for ultimately activating the clock synchronous signal when the number of clocks of the external clock signal generated after enabling the counter corresponds to the number of refresh clocks. Synchronous DRAM cell SRAM comprising a setting comparison means characterized in that. The method of claim 2, wherein the clock synchronization unit And resetting control means for controlling the signal of the initial terminal to disable the counter in response to the activation of the clock synchronous signal. The method of claim 1, wherein the refresh control unit Clock synchronous response means for transitioning a predetermined response terminal signal to a first logic state in response to activation of the clock synchronous signal; Response pulse generating means for providing a response pulse signal activated by a pulse having a predetermined activation width in response to the transition of the response terminal signal to a first logic state; Pulse expansion means which is enabled in response to the refresh request signal and is driven to provide the refresh drive signal in response to the response pulse signal; And And a normal recovery means for generating the normal recovery signal to be activated in response to the activation of the response pulse signal generated in an inactive state of the refresh driving signal REF. The method of claim 4, wherein the refresh control unit And initialization means for controlling the response terminal signal to a second logic state opposite to the first logic state at power up. The refresh request signal generating unit of claim 1, A refresh oscillator for generating an oscillation signal that is activated at a constant cycle; And And a refresh request signal generating means which is activated in response to the oscillation signal and generates the refresh request signal in response to the refresh drive signal and deactivated with a constant delay time. The method of claim 1, wherein the setting signal is A synchronous DRAM cell SRAM, characterized in that the column latency signal. In order to effectively preserve the stored data, each of the DRAM cells includes a plurality of DRAM cells that are required to perform a refresh operation for amplifying and rewriting the stored data within a predetermined refresh period, and an operation section for performing the refresh externally. In a method of driving a synchronous DRAM cell SRAM that can be interfaced with an external system that is not active and is synchronized with an external clock signal, Receiving a setting signal from the outside; Activating a refresh request signal requesting to perform the refresh; And Enabling the refresh request signal by activating the refresh request signal, and performing a refresh during the number of clocks of the external clock signal corresponding to the predetermined number of return clocks after the enable request. The return clock number is A method of driving a synchronous DRAM cell SRAM, characterized in that controlled by the setting signal. The method of claim 8, wherein the setting signal is A method of driving a synchronous DRAM cell SRAM, characterized in that the column latency signal.

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