KR20060102822A - Burst mode clock/data recovering circuit robust to duty cycle distortion - Google Patents

Abstract

The present invention relates to a burst mode clock / data recovery circuit resistant to duty cycle distortion used in a burst mode receiver.

The burst mode clock / data recovery circuit, which is resistant to the duty cycle distortion of the present invention, is a clock / data recovery circuit for recovering clock and data by using an open / close oscillator, each of which has a length of half a period at an upstream and a downstream edge of an input signal. A reset signal generator for generating two pulse signals having; With the two pulse signals of the reset signal generator as inputs, one oscillator has a phase error backward from the input signal as long as the duty cycle is distorted, and the other oscillator has a duty cycle distorted. Two oscillators (Gated Oscillators) oscillating with a phase difference forward in the input signal as much as; Half-phase divider for outputting clocks having the same magnitude as the outputs of the two open / close oscillators and having a phase difference opposite in direction with respect to the input signal, and dividing the phase to output a clock having no phase difference from the input signal. Phase interpolator); There is a technical feature made to include.

Reset Signal Generator, Half Phase Divider

Description

Burst Mode Clock / Data Recovering Circuit Robust to Duty Cycle Distortion}

1 is a structure of a basic opening and closing oscillator,

2 is a basic clock / data recovery circuit diagram using an oscillator;

3 is a diagram illustrating clock recovery by the circuit of FIG. 2;

4 is a diagram illustrating distortion of a recovery clock due to duty cycle distortion;

5 is a clock / data recovery circuit diagram according to an embodiment of the present invention;

6 is a structure of the reset signal generator of FIG.

7 is a half cycle delay circuit structure of FIG.

8 is a view showing the operation of the reset signal generator of FIG.

9 is a structure of the half phase divider of FIG.

10 is a view showing the operation of the half-phase divider of FIG.

11 is a clock recovery diagram by the clock / data recovery circuit of the present invention.

<Description of Symbols for Main Parts of Drawings>

100: Delay Cell

101: Data Retimer

110: reset signal generator

121, 122: Gated VCO

130: half phase interpolator

140: control voltage generator

The present invention relates to a burst mode clock / data recovery circuit that is resistant to duty cycle distortion, and more particularly, by adding a half-phase divider and a reset signal generator to recover an undistorted form of clock and data even when duty cycle distortion occurs. The present invention relates to a burst mode clock / data recovery circuit that is resistant to duty cycle distortion for improving bit error rate.

Clock and data recovery circuits commonly used in burst mode receivers include a gated oscillator.

The open / close oscillator is configured as shown in FIG. 1 and adds an AND gate to the structure of a general ring oscillator composed of an odd number of inverters, and oscillates when an enable signal is applied. If not, output 0.

More specifically, when the enable signal is 1, the output of the AND gate is determined only by the other input. When the node immediately after the AND gate is called the output node of the oscillator, if the output node is high, the previous inverter is odd, so that the output node goes low after five inverters and the AND gate delay time. Is reversed. Also, after that delay again, the output node will return to its original high again.

If the enable signal is zero, the AND gate will output zero on any input. In other words, whether the oscillation can be adjusted according to whether the enable signal is 1 or 0.

On the other hand, when the enable signal continues to 0 and changes to 1, and the delay time of the AND gate passes, the output of the switching oscillator changes from 0 to 1, and at this point, the outputs of the five inverters and the AND gate delay time passes. It is changed to 0 again, and after that, it is changed to 1.

In other words, when the enable signal is changed to 1, the phase is aligned with 0 degrees to start oscillation. As a result, the output of the switching oscillator also has an up edge to match the up edge of the enable signal.

The operation of the switching oscillator as described above can be interpreted as a kind of phase reset. In other words, at the moment of applying the enable signal, the oscillating phase can be set to 0 degrees.

The clock and data recovery circuit using the open / close oscillator may be implemented as shown in FIG. 2. Inverted input signals and input signals are applied to the two open / close oscillators Gated VCOs 11 and 12 as enable signals, respectively.

The operation at this time is as shown in FIG. That is, when the input signal is 0, oscillation occurs in the open / close oscillator 11, and when the input signal is 1, oscillation occurs in the lower open / close oscillator (Gated VCO) 12. These two clocks start oscillating at 0 degrees at the rising and falling edges of the input signal, respectively.

Therefore, when the outputs of the two open / close oscillators are passed through the OR gate 21, a clock that always oscillates can be obtained.

Meanwhile, the control voltage generator 30 added below has a phase locking loop (PLL) structure, in which the control voltage generator (2, 12) can operate at a specified frequency. Control Voltage).

If the three open / close oscillators 11, 12, 31 are the same, the three open / close oscillators 11, 12 are applied when a voltage for controlling the open / close oscillator 31 included in the phase locked circuit PLL is applied to the other two open / close oscillators 11, 12. Oscillators 11, 12 and 31 will oscillate in the same cycle.

For this reason, the open / close oscillator 12 to which input data is applied as it is is aligned with the up edge and starts oscillation. When the data is high, the oscillator starts oscillating and when the data goes low, oscillation stops.

The oscillator 11 in which data is inverted and input is oscillated by being aligned with the downward edge of the original data, and oscillates while the data is low and stops oscillation at the data of high.

Therefore, the outputs of the two open / close oscillators 11 and 12 are shown in FIG. 3.

One open / close oscillator GVCO # 2 or 11 applies inverted data, and the other open / close oscillator GVCO # 1 or 12 applies input data as an enable signal. As described above, the two oscillators oscillate alternately, and when the outputs of the two oscillators are combined with the gate 21, the clock which always oscillates as shown in the last clock of the figure can be restored.

However, even though not shown in the figure, this clock has been through several gate delays in the input data, so the phase will be slower than the phase of the input data. Accordingly, a clock that is correctly phased may be restored by a delay cell 13 that causes the input data to undergo the same gate delay.

On the other hand, when duty cycle distortion occurs, the period when each bit is 1 and the period when 0 is different as shown in FIG. 4. Therefore, the period in which the open / close oscillator should oscillate is different from the period of each bit.

As a result, as shown in FIG. 4, the recovered clock appears in a distorted form and cannot be used as it is, and since the clock is distorted, the distortion of the duty cycle is inevitably reflected in the restored data.

In addition, the bit error rate (BER) is deteriorated because the sampling point does not capture the center of the bit.

In burst-mode optical receivers used in passive optical networks (PONs), duty cycle distortions inevitably occur.To use conventional structures, circuits that compensate for duty cycle distortions are added, or other parts of the circuits More complex design is required, which adds cost to the receiver and makes the design of the network itself difficult.

Accordingly, the present invention is to solve the above-mentioned disadvantages and problems of the prior art, in the design of a burst mode receiver to reduce the additional blocks, reduce the design burden to reduce the design time and cost, distortion of the duty cycle It is an object of the present invention to provide a strong clock / data recovery circuit.

The object of the present invention is a clock / data recovery circuit for recovering clock and data using an open / close oscillator, each of which generates a reset signal generator for generating two pulse signals having a length of half a period at an upstream and a downstream edge of an input signal ( Reset Signal Generator); With the two pulse signals of the reset signal generator as inputs, one oscillator has a phase error backward from the input signal as long as the duty cycle is distorted, and the other oscillator has a duty cycle distorted. Two oscillators (Gated Oscillators) oscillating with a phase difference forward in the input signal as much as; Half-phase divider which outputs a clock having no phase difference by dividing the phase by inputting two clocks having opposite phases and the same phase difference with respect to the input signal as the outputs of the two switching oscillators. Phase interpolator); And a burst mode clock / data recovery circuit resistant to duty cycle distortion.

Details of the above object and technical configuration of the present invention and the resulting effects thereof will be more clearly understood from the following detailed description based on the accompanying drawings.

First, FIG. 5 is a clock / data recovery circuit diagram according to an embodiment of the present invention.

As shown, the clock / data recovery circuit of the present invention, unlike the conventional circuit, uses the output of the reset signal generator 110 as an enable signal of the on / off oscillator and uses an OR gate. Instead, a half phase interpolator (130) is used, and as in the conventional circuit, a delay cell (Delay Cell, 100), a data retimer (Data Retimer, 101), and a gated oscillator (Gated VCO, 121). , 122), and a control voltage generator 140.

The delay cell 100 inputs the delayed data to the data retimer 101 so that the input data has a gate delay such as a clock so as to generate a clock whose phase is accurate. The control voltage generator 140 is a phase synchronization circuit. As a PLL, two open / close oscillators 121 and 122 provide a control voltage for operating at a specified frequency.

The structure and operation of the reset signal generator 110 and the anti-phase divider 130 are as follows.

6 is a structure of the reset signal generator of FIG. 5, FIG. 7 is a half cycle delay circuit structure of FIG. 6, and FIG. 8 is a diagram illustrating an operation of the reset signal generator of FIG. 6.

As shown in FIG. 6, the reset signal generator 110 includes a half-cycle delay circuit 111. The reset signal generator 110 includes input data and data whose input data is half-cycle delayed through the half-cycle delay circuit 111. It consists of two NAND gates 112 and 113.

As shown in FIG. 7, the half-cycle delay circuit 111 removes only the feedback connecting the output and the input from the basic open / close oscillator, that is, the open / close oscillator composed of a ring oscillator and one end gate. It consists of an inverter and one end gate. In this case, when the enable signal is 1, the delay time is about half the period as in the basic switching oscillator.

Accordingly, the reset signal generator 110 generates two pulse signals each having a length of half a cycle at the up and down edges of the input signal, as shown in FIG. 8.

Next, FIG. 9 is a structure of the half phase divider of FIG. 5, and FIG. 10 is a diagram illustrating an operation of the half phase divider of FIG. 9.

As shown, the half phase divider 130 is a circuit for outputting a clock having an intermediate phase of two clocks inputted, and is composed of two pairs of differential transistors.

The half phase divider 130 divides a phase by adding currents of the two pairs of differential transistor signals, and the operation thereof is illustrated in FIG. 10.

10 shows the outputs of clock 1, clock 2 and half phase divider. Half-phase divider 130 is implemented by the sum of the current as shown in FIG. Therefore, the sum of the two clocks in FIG. 10 is equivalent to the following output.

Since the data sampling point is a zero crossing point, the zero crossing point is indicated as a position for comparing the phases of the clocks. The part indicated by the vertical dotted line is the zero crossing point of each clock, and the part indicated by the vertical solid line is the zero crossing point of the output of the half phase divider 130.

10 shows a case in which two clocks have no phase difference, in which case the sum of the two clocks is equal to the original clock.

10 is a case where there is a slight phase difference, in which case the output rises with a small slope from the rising point of one clock, and then rises with a double slope as both clocks rise. When one side finishes rising, it rises again with a small slope, and when both clocks finish rising, the output ends.

As a result, as shown in the drawing, the zero crossing point of the output appears in the middle of the zero crossing point of the two clocks.

10 is a maximum phase difference that the half phase divider 130 can divide. If there is more than this phase difference, there will be a flat part in the middle of the output, and phase division will not be performed properly.

Finally, FIG. 11 is a clock recovery diagram by the clock / data recovery circuit of the present invention.

As shown, according to the clock / data recovery circuit of the present invention, one open / close oscillator is reset in phase at the up edge of the input signal, and the other open / close oscillator is reset in phase at the down edge of the input signal.

Therefore, the first oscillator oscillates with a phase error backward in the input signal as the duty cycle is distorted, and the second oscillator oscillates with a phase difference forward in the input signal as the duty cycle is distorted.

Since the phase difference between the two clocks is the same in magnitude and only opposite in direction, when the two clocks are input to the half phase divider 130, a clock having no phase difference with the input signal can be made. The clock is not distorted in this way, and the point of data acquisition is located in the center of the signal. Therefore, the clock can be used as it is and the bit error rate can be improved.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

Therefore, according to the burst mode clock / data recovery circuit resistant to the duty cycle distortion of the present invention, in designing a burst mode receiver, it is possible to reduce the additional burden for compensating for the duty cycle and to reduce the design burden, so that the time required for the design It is expected to reduce costs and costs, and thus help to accelerate the optical subscriber network era.

Claims (4)

A clock / data recovery circuit for recovering clock and data using an open / close oscillator, A reset signal generator for generating two pulse signals each having a length equal to half a period at the up and down edges of the input signal; With the two pulse signals of the reset signal generator as inputs, one oscillator has a phase error backward from the input signal as long as the duty cycle is distorted, and the other oscillator has a duty cycle distorted. Two oscillators (Gated Oscillators) oscillating with a phase difference forward in the input signal as much as; Half-phase divider for outputting clocks having the same magnitude as the outputs of the two open / close oscillators and having a phase difference opposite in direction with respect to the input signal, and dividing the phase to output a clock having no phase difference from the input signal. Phase interpolator); Burst mode clock / data recovery circuit resistant to the duty cycle distortion, characterized in that consisting of. The method of claim 1, The reset signal generator, A half cycle delay circuit for outputting a half cycle delay of the input signal; A pair of NAND gates for inputting an input signal and a half-period delayed signal through the half-period delay circuit, and generating two pulse signals each having a length of half a cycle at an upstream and a downside edge; Burst mode clock / data recovery circuitry resistant to duty cycle distortion. The method of claim 2, The half cycle delay circuit, A circuit removing only feedback connecting an output and an input from a ring oscillator, the duty being characterized in that an odd number of inverters and one end gate having an output signal of the inverter and an enable signal 1 are connected in series Burst-mode clock / data recovery circuitry resistant to cycle distortion. The method of claim 1, The half phase divider, Burst mode clock / data resistant to duty cycle distortion, comprising two pairs of differential transistors, outputting a clock having an intermediate phase of two clocks inputted by dividing the phase by adding currents of the two pairs of differential transistor signals Restoration circuit.

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