KR20060099023A - Circuit for controlling offset of analog to digital converter - Google Patents

Abstract

The present invention sets an offset value so that an analog-to-digital converter can accurately convert an analog graphic signal into a digital graphic signal according to the resolution.

A coupling capacitor for passing a preset offset control signal, an analog / digital converter for converting a signal passing through the coupling capacitor into a digital signal, an output signal of the analog / digital converter, and a resolution of an analog graphic signal. A reference offset value set according to the comparison, and a comparator selectively generating a charge control signal or a discharge control signal according to the comparison result, and increase or decrease an offset voltage according to the charge control signal or the discharge control signal and apply the result to the capacitor. It consists of a charge pump which converts an analog graphic signal into a digital graphic signal of exactly 10 bits or 12 bits according to the resolution, thereby improving the image quality of the graphic signal displayed on the flat panel display panel.

ADC.Analog / Digital Conversion, Offset, Graphic Signal, Charge Pump

Description

Circuit for controlling offset of analog to digital converter}

1 is a block diagram showing the configuration of an analog graphics signal processing circuit in a conventional video display device.

Figure 2 is a block diagram showing the configuration of the offset control circuit of the present invention.

Figure 3 is a circuit diagram showing the configuration of an embodiment of a charge pump in the offset adjustment circuit of the present invention.

Figure 4 is a circuit diagram showing the configuration of another embodiment of the charge pump in the offset adjustment circuit of the present invention.

Explanation of symbols on the main parts of the drawings

200: switching unit 210: coupling capacitor

220, 340, 460: Buffer 230: Analog-to-digital converter

240: comparator 250: charge pump

300, 310, 400, 410: constant current source 320: offset voltage generator

330: compensation voltage generator 420: offset charging voltage charging unit

430: voltage discharge unit for offset control 440: voltage charging unit for compensation

450: compensation voltage discharge part I _UP : charge control signal

I _DN : discharge control signal

The present invention is to convert an analog graphic signal into a digital graphic signal in a video display device such as a monitor and a television receiver using a flat panel display panel such as a plasma display panel (PDP) or a liquid crystal display (LCD) panel as a display screen. The present invention relates to an offset control circuit of an analog / digital converter for adjusting an offset value of an analog / digital converter.

Recently, the market of video display devices using PDP and LCD panels as display screens is growing rapidly. Various analog graphic signals are input to the video display device. For example, various types of analog graphic signals, including NTSC component signals, luminance and color signals, R, G, B signals, Y, PB, and PR signals, may be input to the digital image display device.

Therefore, video display devices that use LCD panels and PDPs as display screens convert analog graphic signals to digital graphic signals using analog / digital conversion circuits to display the various types of analog graphic signals described above. scaling).

This conventional technique will be described in detail with reference to the drawings of FIG. 1.

1 is a block diagram showing a configuration of a processing circuit of an analog graphic signal in a conventional video display device. Here, reference numeral 100 denotes a graphic signal input unit. The graphic signal input unit 100 may include, for example, R, G, and B signals output from a computer, an NTSC component signal, a YC (luminance and color) signal output from a VCR, and a DVD (Digital Video) Disc. A variety of analog graphics t knees are input, including the Y, PB, and PR signals output from the player.

Reference numeral 110 is an analog / digital converter for converting an analog graphic signal input by the graphic signal input unit 100 into a digital graphic signal. The analog / digital converter 110 may include a sampling / holding amplifier and a flash analog. And a digital conversion unit, a multiplying digital to analog converter (MDAC), and an error correction unit to convert the analog graphic signal input by the graphic signal input unit 100 into a digital graphic signal.

Reference numeral 120 denotes a digital signal processor (DSP). The DSP 120 scales the digital graphic signal output from the analog-to-digital converter 110 to the flat panel display panel, processes the graphic, and outputs the graphic signal to the display unit 130 to display the graphic signal on the flat panel display panel. do.

In such a conventional image display device, when the analog-to-analog signal is converted into a digital graphic signal by the analog-to-digital converter 110, it must be converted into a digital graphic signal of 10 bits or 12 bits according to various resolutions. However, in the related art, since the offset value of the analog-to-digital converter 110 is always fixed at a constant level, there is a limit to converting the digital graphic signal accurately according to the analog graphic signal of various resolutions. There have been various problems such as deterioration of image quality.

Therefore, it is an object of the present invention to adjust the offset value of an analog / digital converter so that the analog-to-digital converter can convert the analog-to-digital signal into a 10-bit or 12-bit digital graphic signal according to the resolution of the input analog graphic signal. The present invention provides an offset control circuit of an analog / digital converter.

The offset control circuit of the analog-to-digital converter of the present invention having the above object includes a coupling capacitor for passing a preset offset adjustment reference signal, an analog-to-digital converter for converting a signal passing through the coupling capacitor into a digital signal; A comparator for comparing the output signal of the analog-to-digital converter with a reference offset value set according to the resolution of the analog graphic signal, and selectively generating a charge control signal or a discharge control signal according to a comparison result; Or a charge pump applied to the capacitor by increasing or decreasing the offset voltage according to the discharge control signal.

The present invention provides a switching unit for switching an analog graphic signal or the preset offset control reference signal to output the coupling capacitor, and buffering and amplifying the signal passing through the coupling capacitor to input the analog / digital converter. Is characterized in that it further comprises a buffer.

The charge pump is provided between the first and first constant current sources, through which the constant current flows according to the first and second bias voltages, and the first constant current source and the second constant current source, wherein the charge control signal and the discharge control signal. An offset adjustment voltage generator for generating an offset adjustment voltage in accordance with the first constant current source and the second constant current source, and according to the generation of the offset adjustment voltage according to an inversion charge control signal and an inversion discharge control signal. And a buffer for buffering and amplifying the offset voltage generated by the offset voltage generator and the compensation voltage generated by the offset voltage generator.

The charge pump may be configured to output first and second constant current sources through which constant current flows according to first and second bias voltages, and constant currents of the first constant current source according to the charge control signal and the inverted charge control signal. A voltage regulating part for charging a voltage, a voltage regulating part for discharging the phase adjusting voltage through the second constant current source according to a discharge control signal and an inverted discharge control signal, and a charge control signal and an inverted charge control signal. A compensation voltage charging unit configured to output a constant current of the first constant current source to charge the compensation voltage, and a compensation voltage to discharge the compensation voltage through the second constant current source according to a discharge control signal and an inverted discharge control signal. A buffer which buffers and amplifies a discharge part, the phase control voltage and the compensation voltage to generate the oscillation control voltage. It characterized in that province.

Each of the phase regulating voltage charging part and the phase regulating voltage discharge part is connected in parallel with an NMOS transistor and a PMOS transistor which are in a conductive state according to the charging control signal and the discharge control signal, and the compensation voltage charging part and the compensation voltage discharge part are connected in parallel. Each of the parts is characterized in that the PMOS transistor and the NMOS transistor which are in a conducting state are connected in parallel according to the inversion charging control signal and the inversion discharge control signal.

Hereinafter, the offset control circuit of the analog-to-digital converter of the present invention will be described in detail with reference to the accompanying drawings of FIGS. 2 to 4.

2 is a block diagram showing the configuration of the offset control circuit of the analog-to-digital converter of the present invention. As shown in the figure, a switching unit 200 for switching and selecting an analog graphic signal or a preset offset adjustment reference signal and a coupling for passing the selected analog graphic signal or a preset offset adjustment reference signal by the switching unit 200. A condenser 210, a buffer 220 for buffering and amplifying the signal passing through the coupling capacitor 210, an analog / digital converter 230 for converting the output signal of the buffer 220 into a digital signal, The output signal of the analog-to-digital converter 230 is compared with a reference offset value set according to the resolution of the input analog graphic signal, and according to the comparison result, the charge control signal I _UP or the discharge control signal I _DN is compared. and selectively generating a comparator 240 to the charge control signal (I _UP) or the discharge control signal (I _DN) to increase or decrease the offset voltage in accordance with the And it was composed of a charge pump 250 is applied to the condenser 210.

The offset adjustment circuit of the analog-to-digital converter of the present invention configured as described above adjusts the offset at the initial stage of switching the input of the analog graphic signal or turning on the image display device, and the control unit (not shown) first By controlling the switching unit 200 to allow the movable terminal to connect to the fixed terminal (b) and select the reference signal, the reference offset value according to the resolution of the analog graphic signal to be input to the comparator 240 is input.

Then, the reference signal switched by the switching unit 200 is buffered and amplified in the buffer 220 through the coupling capacitor 210 and then input to the analog-to-digital converter 230 is converted into a digital signal.

The digital reference signal output from the analog-to-digital converter 230 is input to the comparator 240 and compared with a reference offset value according to the resolution of the analog graphic signal, and according to the comparison result, the comparator 240 uses the charging control signal I _UP ) or discharge control signal I _DN is selectively output.

For example, when the digital reference signal output from the analog-to-digital converter 230 is smaller than the reference offset value according to the resolution of the analog graphic signal, the comparator 240 outputs the charging control signal I _UP and the analog / digital signal. When the digital reference signal output from the digital converter 230 is larger than the reference offset value according to the resolution of the analog graphic signal, the comparator 240 outputs a discharge control signal I _DN , and the comparator 240 optionally The offset value of the reference signal passing through the condenser 210 is set while the output voltage of the charge pump 250 increases or decreases according to the output charging control signal I _UP or discharge control signal I _DN . a / D converter 230, the digital reference signal and the reference offset value of the charge pump 250 when the same according to the resolution of the analog graphics signal charge control signal (I _uP) output from the While maintaining the offset value filled in the discharge control signal (I _DN) without outputting all of the charge pump output is at 250, coupling capacitor 210, as is the offset adjustment is completed.

After the adjustment of the offset of the analog-to-digital converter 230 is completed, the control unit switches the analog graphic signal by connecting the movable terminal of the switching unit 200 to the fixed terminal (a), and the switched analog graphic signal is a buffer 220 ) Is input to the analog-to-digital converter 230 and converted into a digital graphic signal and then input to the DSP 230 for processing.

3 is a circuit diagram showing the configuration of an embodiment of a charge pump in the offset control circuit of the present invention. As shown in the drawing, the first constant current source 300 through which the constant current flows through the PMOS transistor PM31 at the power supply terminal V _DD according to the bias voltage BIASP, and the NMOS transistor according to the bias voltage BIASN. An NMOS transistor NM32 (NM33) between the second constant current source 310 through which the constant current flows through the NM31 to the power supply terminal V _SS , and the first constant current source 300 and the second constant current source 310. ) Is connected in series and the NMOS transistor NM32 (NM33) selectively operates according to the charge control signal I _UP and the discharge control signal I _DN to generate an offset adjustment voltage. PMOS transistors PM32 and PM33 are connected in series between the first constant current source 300 and the second constant current source 310, and an inverted charge control signal / I _UP and an inverted discharge control signal When the PMOS transistor (PM32) (PM33) is selectively operated in accordance with the / I _DN) The compensation voltage generator 330 for generating a compensation voltage according to the generation of the offset adjustment voltage, the offset voltage generated by the offset voltage generator 320 and the compensation voltage generator 330 The buffer 340 buffers and amplifies the generated compensation voltage with the operational amplifier OP31.

The charge pump 250 of the present invention configured as described above has a first and second bias voltages BIASP (BIASN) of a predetermined level when an operating power is applied to a power supply terminal V _DD (V _SS ). The PMOS transistor PM31 and the NMOS transistor NM31 of the constant current sources 300 and 310 are respectively in a conductive state to supply and discharge a constant level of a predetermined level.

In this state, the NMOS transistors NM32 and NM33 of the offset adjustment voltage generator 320 selectively conduct according to the charge control signal I _UP and the discharge control signal I _DN output by the comparator 340. In this state, the level of the offset adjustment voltage input to the non-inverting input terminal (+) of the operational amplifier OP31 of the buffer 340 is varied. That is, when the comparator 340 outputs the charge control signal I _UP , the NMOS transistor NM32 becomes conductive, and current flows through the PMOS transistor PM31 and the NMOS transistor NM32. The level of the offset control voltage input to the non-inverting input terminal (+) of the operational amplifier OP1 is increased. When the comparator 340 outputs the discharge control signal I _DN , the NMOS transistor NM33 is brought into a conducting state, and the NMOS transistor NM33 (at the non-inverting input terminal + of the operational amplifier OP1). The current flows through the NM31 to the power supply terminal V _SS to reduce the level of the offset adjustment voltage applied to the non-inverting input terminal (+) of the operational amplifier OP31.

And the charge control signal (I _UP) and a discharge control signal is inverted by inverting the (I _DN), the charge control signal (/ I _UP) and reverse discharge control signal (/ I _DN), the compensation voltage generating unit 330 for in accordance with The PMOS transistors PM32 and PM33 are selectively in a conductive state so that the level of the compensation voltage input to the inverting input terminal (−) of the operational amplifier OP31 of the buffer 340 is varied. That is, the compensating voltage generator 330 is a non-inverting input terminal of the operational amplifier OP31 in the offset adjustment voltage generator 320 according to the charge control signal I _UP and the discharge control signal I _DN . The PMOS transistor PM32 is in a conductive state when the inverted charge control signal / I _UP is input. A current flows through the PM32 to increase the level of the compensation voltage input to the inverting input terminal (−) of the operational amplifier OP31. The PMOS transistor PM33 is brought into a conductive state according to the inverted discharge control signal / I _DN so that the PMOS transistor PM33 and the NMOS transistor NM31 are connected at the inverting input terminal (-) of the operational amplifier OP31. A current flows through the power supply terminal V _SS to reduce the level of the compensating voltage applied to the inverting input terminal (−) of the operational amplifier OP31.

As such, the offset adjustment voltage output by the offset adjustment voltage generator 320 and the compensation voltage generated by the compensation voltage generator 330 are buffered and amplified by the operational amplifier OP31 of the buffer 340 and output as offset voltages. The output offset voltage is charged in the coupling capacitor 210 to determine the offset of the signal passing through the capacitor 210.

4 is a circuit diagram showing the configuration of another embodiment of the charge pump in the offset adjustment circuit of the present invention. As shown in FIG. 1, the first constant current source 400 through which the constant current flows through the PMOS transistor PM41 at the power supply terminal V _DD according to the bias voltage BIASP, and the NMOS transistor according to the bias voltage BIASN. According to the second constant current source 410 through which the constant current flows through the NM41 to the power supply terminal V _SS , the NMOS transistor NM42 and the P according to the charge control signal I _UP and the inverted charge control signal / I _UP . Each of the MOS transistors PM42 is in a conductive state, and outputs a constant current of the first constant current source 400 to offset the voltage charging unit 420 for charging the offset adjustment voltage, the discharge control signal I _DN , and the reverse discharge control. The NMOS transistor NM43 and the PMOS transistor PM43 are in a conductive state according to the signal / I _DN , and the offset adjustment voltage discharge unit discharges the offset adjustment voltage through the second constant current source 410 ( 430), charging control No. (I _UP) and the inverted charge control signal yen according to (/ I _UP) MOS transistor (NM44) and a PMOS transistor (PM44) as an in each conductive state compensation and outputs a constant current of said first constant current source (400) The NMOS transistor NM45 and the PMOS transistor PM45 are in a conductive state according to the compensation voltage charging unit 440 which charges the voltage and the discharge control signal I _DN and the inverted discharge control signal / I _DN . While the compensation voltage discharge unit 450 discharges the compensation voltage through the second constant current source 410, the offset adjustment voltage and the compensation voltage by amplifying the oscillation control by the operational amplifier OP41. The buffer 460 outputs the voltage V _CON .

Another embodiment of the charge pump according to the present invention configured as described above may include a first constant current source 400 as a bias voltage BIASP is input at a predetermined level while operating power is applied to a power supply terminal V _DD (V _SS ). The PMOS transistor PM41 of the state is in a conductive state to supply a constant current of a predetermined level, and when the bias voltage BIASN of the predetermined level is input, the NMOS transistor NM41 of the second constant current source 410 is in a conductive state. To discharge a constant level of a predetermined level.

In this state, as the charge control signal I _UP and the discharge control signal I _DN are selectively output from the comparator 340, the offset adjustment voltage charging unit 420 and the offset adjustment voltage discharge unit 430 operate to offset the offset. In addition to charging and discharging the adjustment voltage, the compensation voltage charging unit 440 and the compensation voltage discharge unit 450 operate to charge and discharge the compensation voltage.

That is, the NMOS transistor NM42 and the PMOS transistor PM42 are in a conductive state in response to the charge control signal I _UP and the inverted charge control signal / I _UP . By passing the output current of the constant current source 400, the level of the offset adjustment voltage is increased, and the offset adjustment voltage discharge unit 430 is driven in accordance with the discharge control signal I _DN and the reverse discharge control signal / I _DN . As the MOS transistor NM43 and the PMOS transistor PM43 are in a conductive state, the offset adjustment voltage is discharged to the second constant current source 410 through the offset adjustment voltage discharge unit 430 so that the level of the offset adjustment voltage is lowered. do.

In addition, the compensation voltage charging unit 440 is connected to the NMOS transistor NM44 and the PMOS transistor PM44 according to a charge control signal I _UP and an inverted charge control signal / I _UP , and thus the first constant current. The level of the compensating voltage is increased by passing the output current of the circle 400, and the compensating voltage discharge part 450 has an NMOS according to the discharge control signal I _DN and the inverted discharge control signal / I _DN . As the transistors NM45 and PMOS transistors PM45 are in a conductive state, the compensation voltage is discharged to the second constant current source 410 through the compensation voltage discharge unit 450 to lower the level of the compensation voltage. .

As such, the offset adjustment voltage and the compensation voltage that are varied according to the charge control signal I _UP and the discharge control signal I _DN are inputted to the operational amplifier OP41 of the buffer 460, buffered and amplified, and then output as offset voltages. The output offset voltage is charged in the coupling capacitor 210 to determine the offset of the signal passing through the capacitor 210.

Unlike the above-described embodiment, the charge pump according to another embodiment of the present invention may be offset voltage adjusting part 420, offset voltage adjusting part 430, compensation voltage charging part 440, and compensation voltage discharge part ( Each of the 440 is formed as a pair of NMOS transistors NM42 to NM45 and PMOS transistors PM42 to PM45 to charge and discharge the offset control voltage and the compensation voltage to charge and discharge the charge control signal I _UP and the discharge control signal. Even if (I _DN ) fluctuates rapidly, the offset adjustment voltage and the compensation voltage input to the buffer 460 do not abruptly change, so that no jitter occurs in the offset voltage output from the charge pump and the offset voltage is stably stabilized. By setting, the input graphic signal can be converted into digital graphic signal accurately according to the resolution.

On the other hand, while the present invention has been shown and described with respect to specific preferred embodiments, various modifications and changes of the present invention without departing from the spirit or field of the invention provided by the claims below It can be easily understood by those skilled in the art.

As described above, the present invention sets the offset voltage of the analog-to-digital converter according to the resolution of the input analog graphic signal, thereby converting the analog graphic signal into a digital graphic signal of exactly 10 bits or 12 bits according to the resolution. As a result, the image quality of the graphic signal displayed on the flat panel is improved.

Claims (6)

A coupling capacitor for passing a preset offset adjustment reference signal; An analog / digital converter for converting the signal passing through the coupling capacitor into a digital signal; A comparator for comparing the output signal of the analog / digital converter with a reference offset value set according to the resolution of the analog graphic signal, and selectively generating a charge control signal or a discharge control signal according to a comparison result; And And a charge pump configured to increase or decrease an offset voltage according to the charge control signal or the discharge control signal and apply the charge pump to the capacitor. The method of claim 1, A switching unit configured to switch an analog graphic signal or the preset offset control reference signal to output the coupling capacitor; And And a buffer for buffering and amplifying the signal passing through the coupling capacitor and inputting the signal to the analog / digital converter. 2. The system of claim 1, wherein the charge pump; First and first constant current sources through which constant current flows according to the first and second bias voltages; An offset adjustment voltage generator disposed between the first constant current source and the second constant current source and configured to generate an offset adjustment voltage according to the charge control signal and the discharge control signal; A compensation voltage generator provided between the first constant current source and the second constant current source and generating a compensation voltage according to generation of the offset adjustment voltage according to an inversion charge control signal and an inversion discharge control signal; And And a buffer for buffering and amplifying the offset adjustment voltage generated by the offset adjustment voltage generator and the compensation voltage generated by the compensation voltage generator. 2. The system of claim 1, wherein the charge pump; First and second constant current sources through which constant current flows according to the first and second bias voltages; A phase regulating voltage charging unit configured to output a constant current of the first constant current source to charge a phase regulating voltage according to the charging control signal and the inverting charging control signal; A phase control voltage discharge unit configured to discharge the phase control voltage through the second constant current source according to a discharge control signal and an inverted discharge control signal; A compensation voltage charging unit configured to output a constant current of the first constant current source to charge a compensation voltage according to a charge control signal and an inverted charge control signal; A compensation voltage discharge unit configured to discharge the compensation voltage through the second constant current source according to a discharge control signal and an inverted discharge control signal; And And a buffer configured to buffer and amplify the phase control voltage and the compensation voltage to generate the oscillation control voltage. The method of claim 4, wherein each of the phase regulating voltage charger and the phase regulating voltage discharge part comprises: And an NMOS transistor and a PMOS transistor which are in a conductive state according to the charge control signal and the discharge control signal, connected in parallel. 5. The apparatus of claim 4, wherein each of the compensation voltage charger and the compensation voltage discharge part; And a PMOS transistor and an NMOS transistor which are in a conductive state according to the inversion charge control signal and the inversion discharge control signal, are connected in parallel.

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