KR20060098075A - Thin film transistor substrate and method of fabricating the same - Google Patents

Abstract

The present invention relates to a thin film transistor substrate and a method of manufacturing the same that can prevent corrosion and corrosion of signal lines and signal pads.

 The thin film transistor substrate according to the present invention comprises: a first signal pad electrode connected to a signal line and formed on an inorganic layer; An organic passivation layer formed to cover the first signal pad electrode; A first pad contact hole penetrating the organic passivation layer to expose the first signal pad electrode and the inorganic layer; A second signal pad electrode formed on the organic passivation layer so as to be connected to the first signal pad electrode and the inorganic layer through the first pad contact hole, wherein the first signal pad electrode is the first pad contact hole. It is characterized in that formed in the width smaller than the contact hole in the.

Description

Thin Film Transistor Substrate and Method for Manufacturing the Same {Thin Film Transistor Substrate And Method Of Fabricating The Same}

1 is a perspective view illustrating a conventional liquid crystal display panel.

FIG. 2 is a plan view and a cross-sectional view illustrating a signal pad connected to the signal line shown in FIG. 1.

FIG. 3 is a diagram for describing a pinhole phenomenon of the signal pad upper electrode illustrated in FIG. 2.

4 is a plan view illustrating a thin film transistor substrate according to a first exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a thin film transistor substrate taken along lines II-II ', III-III', and IV-IV 'of FIG. 4.

6A and 6B are plan views and cross-sectional views for describing the active layer forming process illustrated in FIGS. 4 and 5.

7A and 7B are a plan view and a cross-sectional view for explaining a process of forming a first conductive pattern group shown in FIGS. 4 and 5.

8A and 8B are plan views and cross-sectional views illustrating a process of forming the source contact hole, the drain contact hole, the first gate contact hole, and the first data contact hole shown in FIGS. 4 and 5.

9A and 9B are a plan view and a cross-sectional view for describing a process of forming a second conductive pattern group shown in FIGS. 4 and 5.

10A and 10B are plan views and cross-sectional views for describing a process of forming the pixel contact hole, the second gate contact hole, and the second data contact hole shown in FIGS. 4 and 5.

11A and 11B are a plan view and a cross-sectional view for describing a third conductive pattern group forming process illustrated in FIGS. 4 and 5.

12 is a cross-sectional view illustrating a thin film transistor substrate according to a second exemplary embodiment of the present invention.

13A and 13B are cross-sectional views illustrating pads of a thin film transistor substrate according to a third exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

1,11,101: substrate 2,102: gate line

4,104 data line 12 color filter

14 common electrode 16 liquid crystal

18 black matrix 22 pixel electrode

24,118,148: organic protective film 30,130: thin film transistor

70: thin film transistor substrate 80: color filter substrate

106: gate electrode 108: source electrode

110 drain electrode 112 gate insulating film

114: active layer 116: buffer film

120,124,146,148,158,168 Contact hole 122 Pixel electrode

126: interlayer insulating film 132: storage line

134: storage electrode 136: storage capacitor

150: gate pad 152: gate pad lower electrode

154: gate pad intermediate electrode 156: gate pad upper electrode

160: data pad 152: data pad lower electrode

154: data pad middle electrode 156: data pad upper electrode

The present invention relates to a thin film transistor substrate and a method of manufacturing the same, and more particularly, to a thin film transistor substrate and a method of manufacturing the same that can prevent the corrosion of signal lines and signal pads.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.

As shown in FIG. 1, the liquid crystal display panel includes a thin film transistor substrate 70 and a color filter substrate 80 bonded to each other with the liquid crystal interposed therebetween.

The color filter substrate 80 has a black matrix 18 for preventing light leakage, a color filter 12 for implementing color, a common electrode 14 forming a vertical electric field with the pixel electrode 22, and a liquid crystal alignment thereon. It consists of an upper alignment film applied for.

The thin film transistor substrate 70 is connected to the gate line 2 and the data line 4 formed to cross each other, the thin film transistor 30 formed at the intersection of them 2 and 4, and the thin film transistor 30. Pixel electrode 22 and a lower alignment film coated thereon for liquid crystal alignment.

The conventional thin film transistor substrate 70 further includes a signal pad 40 for supplying a driving signal to at least one of the gate line 2 and the data line 4 as shown in FIG. 2.

The signal pad 40 may include a signal pad lower electrode 42 connected to a signal line, a contact hole 44 penetrating the passivation layer (or a gate insulating layer / protective layer) 48 to expose the signal pad lower electrode 42. And a signal pad upper electrode 46 connected to the signal pad lower electrode 42 through the contact hole 44 and formed of a transparent conductive material resistant to corrosion and corrosion.

Here, the protective film 48 is formed of an organic insulating material to improve the opening ratio. The organic protective film 48 made of this organic insulating material is weaker to heat and moisture than the inorganic protective film made of the inorganic insulating material.

In this case, when the signal pad lower electrode 42 does not overlap the signal pad upper electrode 46 with the organic passivation layer 48 therebetween, the signal is caused by moisture introduced from the outside via the organic passivation layer 48. The pad lower electrode 42 is prone to corrosion and corrosion. Furthermore, the corrosion and corrosion of the signal lines connected to the signal pad lower electrode 42 are also spread and corrosion occurs.

In addition, pinholes (Pin) in the signal pad upper electrode 46 as shown in FIG. 3 due to a defect in the deposition process and the patterning process (exposure, development, and etching) of the transparent conductive film forming the signal pad upper electrode 46. Holes (PH) are often formed. The signal pad lower electrode 46 is exposed by the pinhole PH, and external moisture or the like penetrates through the pinhole PH, thereby causing the signal pad lower electrode 42 to corrode.

Accordingly, an object of the present invention is to provide a thin film transistor substrate and a method of manufacturing the same that can prevent the corrosion and corrosion of signal pads and signal lines.

In order to achieve the above object, the thin film transistor substrate according to the present invention comprises a first signal pad electrode connected to the signal line and formed on the inorganic film; An organic passivation layer formed to cover the first signal pad electrode; A first pad contact hole penetrating the organic passivation layer to expose the first signal pad electrode and the inorganic layer; A second signal pad electrode formed on the organic passivation layer so as to be connected to the first signal pad electrode and the inorganic layer through the first pad contact hole, wherein the first signal pad electrode is the first pad contact hole. It is characterized in that formed in the width smaller than the contact hole in the.

The thin film transistor substrate may include a pixel electrode formed on the organic passivation layer; And a thin film transistor connected to the pixel electrode and protected by the organic protective film.

The signal line is a gate line connected to a gate electrode of the thin film transistor, and a third signal pad electrode connected to the gate line; An interlayer insulating film formed between the first and third signal pad electrodes; And a second pad contact hole for exposing the third signal pad electrode through the interlayer insulating layer, which is the inorganic layer, to connect the third signal pad electrode and the first signal pad electrode.

The signal line is a data line connected to a source electrode of the thin film transistor and comprises a third signal pad electrode connected to the data line; An interlayer insulating film formed between the first and third signal pad electrodes; And a second pad contact hole for exposing the third signal pad electrode through the interlayer insulating layer, which is the inorganic layer, to connect the third signal pad electrode and the first signal pad electrode.

The thin film transistor substrate further includes a contact portion for connecting the data line and the third signal pad electrode, wherein the contact portion includes a data link extending from the third signal pad electrode; And a link contact hole exposing a gate insulating film formed to cover the data link.

The area of the second signal pad electrode formed on the organic passivation layer is increased as the distance between the edge of the first signal pad electrode exposed through the first pad contact hole and the edge of the organic passivation layer is closer. do.

The thin film transistor is characterized in that the polysilicon thin film transistor.

In order to achieve the above object, a method of manufacturing a thin film transistor substrate according to the present invention comprises the steps of forming a first signal pad electrode connected to the signal line on the inorganic film; Forming an organic passivation layer to cover the first signal pad electrode; Forming a first pad contact hole penetrating the organic passivation layer to expose the first signal pad electrode and the inorganic layer; Forming a second signal pad electrode on the organic passivation layer so as to be connected to the first signal pad electrode and the inorganic layer through the first pad contact hole, wherein the first signal pad electrode is formed on the first pad. The contact hole may have a smaller width than the contact hole.

The method of manufacturing the thin film transistor substrate includes forming a thin film transistor under the organic protective film; The method may further include forming a pixel electrode on the organic passivation layer.

The signal line is a gate line connected to a gate electrode of the thin film transistor, and forming a third signal pad electrode connected to the gate line; Forming an interlayer insulating film between the first and third signal pad electrodes; And forming a second pad contact hole through the interlayer insulating layer, which is the inorganic layer, to expose the third signal pad electrode to connect the third signal pad electrode and the first signal pad electrode. It features.

The signal line is a data line connected to a source electrode of the thin film transistor, and forming a third signal pad electrode connected to the data line; Forming an interlayer insulating film between the first and third signal pad electrodes; And forming a second pad contact hole through the interlayer insulating layer, which is the inorganic layer, to expose the third signal pad electrode to connect the third signal pad electrode and the first signal pad electrode. It features.

The method of manufacturing the thin film transistor substrate further includes forming a contact portion for connecting the data line and the third signal pad electrode, and the forming the contact portion includes data extended from the third signal pad electrode. Forming a link; And forming a link contact hole exposing the gate insulating film formed to cover the data link.

The area of the second signal pad electrode formed on the organic passivation layer is increased as the distance between the edge of the first signal pad electrode exposed through the first pad contact hole and the edge of the organic passivation layer is closer. do.

The forming of the thin film transistor may include forming a polysilicon active layer on a substrate; Forming a gate electrode on the gate insulating film formed to cover the active layer; And forming a source and a drain electrode on the interlayer insulating layer which is connected to each of the source region and the drain region of the active layer and covers the gate electrode.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 4 to 13B.

4 is a plan view illustrating a thin film transistor substrate of a liquid crystal display panel according to a first exemplary embodiment of the present invention, and FIG. 5 is a liquid crystal taken along lines II-II ', III-III', and IV-IV 'of FIG. 4. A cross-sectional view of a thin film transistor substrate of a display panel.

4 and 5, the TFT array substrate includes a TFT 130 connected to a gate line 102 and a data line 104, a pixel electrode 122 connected to a TFT 130, and a pixel electrode ( And a storage capacitor 136 for preventing the charged voltage variation of 122. The TFT 130 is formed of an N type or a P type, but only a case where the TFT 130 is formed of an N type will be described below.

The TFT 130 charges the pixel electrode 122 with the video signal. To this end, the TFT 130 includes a gate electrode 106 connected to the gate line 102, a source electrode included in the data line 104, and a pixel electrode through the pixel contact hole 120 passing through the passivation layer 118. The active layer 114 which forms a channel between the source electrode and the drain electrode 110 by the drain electrode 110 and the gate electrode 106 connected to 122 is provided.

The active layer 114 is formed on the lower substrate 101 with the buffer layer 116 interposed therebetween. The gate electrode 106 connected to the gate line 102 is formed to overlap the channel region 114C of the active layer 114 and the gate insulating layer 112 therebetween. The data line 104 and the drain electrode 110 are insulated from each other with the gate electrode 106 and the interlayer insulating layer 126 therebetween. The source electrode 108 and the drain electrode 110 included in the data line 104 may have a source contact hole 124S and a drain contact hole 124D passing through the interlayer insulating layer 126 and the gate insulating layer 112. The n + impurity is connected to each of the source region 114S and the drain region 114D through each of them. In addition, the active layer 114 may include a lightly doped drain (LDD) region (not shown) in which n− impurities are implanted between the channel region 114C and the source and drain regions 114S and 114D to reduce the off current. ) May be further provided.

The storage capacitor 136 keeps the video signal charged in the pixel electrode 122 stable. To this end, the storage capacitor 136 includes a storage line 132 crossing the pixel electrode 122, and a storage electrode 134 extending from the drain electrode 110 connected to the pixel electrode 122. ) And overlapping each other.

The gate line 102 is connected to a gate driver (not shown) through the gate pad 150. The gate pad 150 is provided through a gate pad lower electrode 152 connected to the gate line 102, and a first gate contact hole 158 penetrating through the gate pad lower electrode 152 and the interlayer insulating layer 126. And a gate pad upper electrode 156 connected through the gate pad intermediate electrode 154 connected through the gate pad intermediate electrode 154 and the second gate contact hole 148 penetrating through the organic passivation layer 118. .

The gate pad intermediate electrode 154 is formed of a relatively high conductivity source / drain metal to compensate for the resistance of the gate pad upper electrode 156 formed of a transparent conductive material having a relatively high resistance value. The gate pad intermediate electrode 154 is formed in the second gate contact hole 148 to have a smaller width than the second gate contact hole 148. Accordingly, the front and side surfaces of the gate pad intermediate electrode 154 and the interlayer insulating layer 126 are exposed through the second gate contact hole 148. In this case, the gate pad intermediate electrode 154 is formed to have a width such that a defective phenomenon due to contact resistance with the gate pad upper electrode 156 does not occur.

 The gate pad upper electrode 156 is formed to cover the front and side surfaces of the gate pad intermediate electrode 154 exposed through the second gate contact hole 148 and the interlayer insulating layer 126. Accordingly, the water flowing in from the outside is blocked by the gate pad upper electrode 156 and the edge of the gate pad middle electrode 154 is exposed by the interlayer insulating layer 126 exposed through the second gate contact hole 148. The distance between the edges of the organic passivation layer 118 is far away and the penetration path of moisture is farther away. As a result, corrosion and transfer of the gate pad intermediate electrode 154, the gate pad lower electrode 152, and the gate line 102 due to moisture introduced from the outside are prevented.

In addition, the contact area of the gate pad upper electrode 156 with the gate pad intermediate electrode 154 having a width smaller than that of the second gate contact hole 148 is relatively reduced. Accordingly, even if a pinhole phenomenon occurs in the gate pad upper electrode 156, the probability of corrosion of the gate pad intermediate electrode 154 is reduced.

The data line 104 is connected to a data driver (not shown) through the data pad 160. The data pad 160 may include a data pad lower electrode 162 connected to the data line 104, and a first data contact hole 168 penetrating the data pad lower electrode 162 and the interlayer insulating layer 126. The data pad intermediate electrode 164 connected through the data pad upper electrode 166 connected through the data pad intermediate electrode 164 and the second data contact hole 146 penetrating the organic passivation layer 118. do.

The data pad middle electrode 164 is formed of a relatively high conductivity source / drain metal to compensate for the resistance of the data pad upper electrode 166 formed of a transparent conductive material having a relatively high resistance value. The data pad intermediate electrode 164 is formed in the second data contact hole 146 to have a smaller width than the second data contact hole 146. Accordingly, the front and side surfaces of the data pad intermediate electrode 164 and the interlayer insulating layer 126 are exposed through the second data contact hole 146. In this case, the data pad intermediate electrode 164 is formed to have a width such that a failure phenomenon due to contact resistance with the data pad upper electrode 166 does not occur.

The data pad upper electrode 166 is formed to cover the front and side surfaces of the data pad intermediate electrode 164 exposed through the second data contact hole 146 and the interlayer insulating layer 126. Accordingly, the water flowing in from the outside is blocked by the data pad upper electrode 166 and the edge of the data pad middle electrode 164 is exposed by the interlayer insulating layer 126 exposed through the second data contact hole 146. The distance between the edges of the organic passivation layer 118 is far away and the penetration path of moisture is farther away. As a result, corrosion and spreading of the data pad middle electrode 164, the data pad lower electrode 162, and the data line 104 due to moisture introduced from the outside are prevented.

In addition, the data pad upper electrode 166 has a relatively smaller contact area with the data pad intermediate electrode 164 having a width smaller than that of the second data contact hole 146. Accordingly, even if a pinhole phenomenon occurs in the data pad upper electrode 166, the probability of corrosion of the data pad middle electrode 164 is reduced.

The data pad 142 connected to the data pad lower electrode 162 and the data line 104 located on a plane different from the data link 142 are connected through the link contact hole 144 to thereby provide a data pad. The lower electrode 162 and the data line 104 are electrically connected. The link contact hole 144 passes through the interlayer insulating layer 126 to expose the data link 142. At this time, the link contact hole 144 is located in the active region inside the sealing material (not shown).

The thin film transistor substrate according to the first embodiment of the present invention is formed by a manufacturing process as shown in Figures 6a to 11b.

6A and 6B, a buffer layer 116 is formed on the lower substrate 101, and an active layer 114 is formed thereon.

The buffer layer 116 is formed by depositing an inorganic insulating material such as SiO ₂ on the lower substrate 101.

The active layer 114 is formed by depositing amorphous silicon on the buffer layer 116, crystallizing with a laser to become poly-silicon, and then patterning the photolithography and etching processes.

7A and 7B, a gate insulating layer 112 is formed on the buffer layer 116 on which the active layer 114 is formed, and the gate electrode 106, the gate line 102, and the gate pad lower electrode are formed thereon. A first conductive pattern group including 152, a storage line 132, and a data pad lower electrode 162 is formed.

The gate insulating layer 112 is formed by depositing an inorganic insulating material such as SiO ₂ on the buffer layer 116 on which the active layer 114 is formed.

The gate electrode 106, the gate line 102, the gate pad lower electrode 152, the storage line 132, and the data pad lower electrode 162 form a gate metal layer on the gate insulating layer 112, and then the gate thereof. The metal layer is formed by patterning the photolithography process and the etching process.

The n + impurity is implanted into the active layer 114 using the gate electrode 106 as a mask to form a source region 114S and a drain region 114D of the active layer 114. The source and drain regions 114S and 114D of the active layer 114 face each other with the channel region 114C overlapping the gate electrode 106 interposed therebetween.

8A and 8B, an interlayer insulating layer 126 is formed on the gate insulating layer 112 on which the first conductive pattern group is formed, and the source contact hole 124S, the drain contact hole 124D, and the first gate contact are formed. The hole 158 and the first data contact hole 168 are formed.

The interlayer insulating layer 126 is formed by depositing an inorganic insulating material such as SiO ₂ on the gate insulating layer 112 on which the first conductive pattern group is formed.

Subsequently, the source contact hole 124S, the drain contact hole 124D, the first gate contact hole 158, and the first data contact penetrate through the interlayer insulating film 126 and the gate insulating film 112 by a photolithography process and an etching process. The hole 168 is formed. The source contact hole 124S penetrates the interlayer insulating layer 126 and the gate insulating layer 112 to expose the source region 114S of the active layer 114, and the drain contact hole 124D has the interlayer insulating layer 126 and the gate. The drain region 114D of the active layer 114 is exposed through the insulating layer 112, and the first gate contact hole 158 penetrates the interlayer insulating layer 126 to expose the gate pad lower electrode 152. The first data contact hole 168 passes through the interlayer insulating layer 126 to expose the data pad lower electrode 162.

9A and 9B, a data line 104, a source electrode 108, a drain electrode 110, a storage electrode 134, a data link 142, and a data pad intermediate electrode are formed on the interlayer insulating layer 126. A second conductive pattern group including 164 and a gate pad intermediate electrode 154 is formed.

The data line 104, the source electrode 108, the drain electrode 110, the storage electrode 134, the data link 142, the data pad middle electrode 164, and the gate pad middle electrode 154 are interlayer insulating films 126. After the source / drain metal layer is formed on the C), the source / drain metal layer is formed by photolithography and etching. The source electrode 108 and the drain electrode 110 are connected to each of the source region 114S and the drain region 114D of the active layer 114 through the source and drain contact holes 124S and 124D, respectively. The data pad middle electrode 164 and the gate pad middle electrode 154 are connected to the data pad lower electrode 162 and the gate pad lower electrode 152 through the first data and the first gate contact holes 168 and 158, respectively. .

10A and 10B, an organic passivation layer 118 is formed on the interlayer insulating layer 126 on which the second conductive pattern group is formed, and the pixel contact hole 120 and the second pass through the organic passivation layer 118. The gate contact hole 148 and the second data contact hole 146 are formed.

The organic passivation layer 118 is formed by depositing an organic insulating material on the interlayer insulating layer 126 on which the second conductive pattern group is formed. As the organic protective film 118, an organic insulating material such as photoacrylic or BCB is used.

Subsequently, the pixel contact hole 120, the second gate contact hole 148, and the second data contact hole 146 that pass through the organic passivation layer 118 are formed by a photolithography process and an etching process. The pixel contact hole 120 penetrates through the organic passivation layer 118 to expose the drain electrode 110 of the TFT 130, and the second gate contact hole 148 penetrates through the organic passivation layer 118 to form a gate pad intermediate electrode. 154 is exposed, and the second data contact hole 146 penetrates through the organic passivation layer 118 to expose the data pad intermediate electrode 164.

11A and 11B, a third conductive pattern group including the pixel electrode 122, the gate pad upper electrode 156, and the data pad upper electrode 166 is formed on the organic passivation layer 118.

The pixel electrode 122, the gate pad upper electrode 156, and the data pad upper electrode 166 are deposited by depositing a transparent conductive material on the passivation layer 118, and then patterning the transparent conductive material by a photolithography process and an etching process. Is formed. The pixel electrode 122 is connected to the drain electrode 110 of the TFT 130 through the pixel contact hole 120. The gate pad upper electrode 156 is connected to the gate pad intermediate electrode 154 through the second gate contact hole 148. The data pad upper electrode 166 is connected to the data pad intermediate electrode 164 through the second data contact hole 146.

12 is a cross-sectional view illustrating a thin film transistor substrate according to a second exemplary embodiment of the present invention.

The thin film transistor substrate shown in FIG. 12 has the same components as controlling the width of the contact hole and the width of the pad upper electrode correspondingly wider than that of the thin film transistor substrate shown in FIG. 5. Accordingly, detailed description of the same components will be omitted.

The second gate contact hole 148 exposes the gate pad middle electrode 154 in a width wider than that of the gate pad middle electrode 154, and also exposes the interlayer insulating layer 126 adjacent to the gate pad middle electrode 154. In this case, the second gate contact hole 148 is formed to have a smaller width than the second gate contact hole shown in FIG. 5 (W11> W21). Correspondingly, the gate pad upper electrode 156 formed on the organic passivation layer 118 having the second gate contact hole 148 is formed on the organic passivation layer 118 than the gate pad upper electrode illustrated in FIG. 5. Is widened (W12 <W22). Accordingly, the distance between the edge of the gate pad middle electrode 154 and the edge of the gate pad upper electrode 156 is farther away, so that the penetration path of moisture through the organic passivation layer 118 is farther away. As a result, corrosion and transfer of the gate pad intermediate electrode 154, the gate pad lower electrode 152, and the gate line 102 due to moisture introduced from the outside are prevented.

The second data contact hole 146 exposes the data pad middle electrode 164 in a wider width than the data pad middle electrode 164 and exposes the interlayer insulating layer 126 adjacent to the data pad middle electrode 164. In this case, the second data contact hole 146 is formed to have a smaller width than the second data contact hole shown in FIG. 5 (W11> W21). Correspondingly, the data pad upper electrode 166 formed on the organic passivation layer 118 having the second data contact hole 146 is formed on the organic passivation layer 118 rather than the data pad upper electrode illustrated in FIG. 5. Is widened (W12 <W22). Accordingly, the distance between the edge of the data pad middle electrode 164 and the edge of the data pad upper electrode 166 is farther away, so that the penetration path of moisture through the organic passivation layer 118 is farther away. As a result, corrosion and transfer of the data pad middle electrode 164, the data pad lower electrode 162, and the data line 104 due to moisture introduced from the outside are prevented.

As described above, the thin film transistor substrate according to the second embodiment of the present invention may include the gate pad intermediate electrode 154 and the data pad intermediate electrode exposed through the second gate contact hole 148 and the second data contact hole 146, respectively. The closer the separation distance between the edge of 164 and the edge of the organic passivation layer 118 is, the wider the area of the gate pad upper electrode 156 and the data pad upper electrode 166 formed on the organic passivation layer 118 is.

13A and 13B are cross-sectional views illustrating a thin film transistor substrate according to a third exemplary embodiment of the present invention.

The thin film transistor substrate shown in FIGS. 13A and 13B has the same components except for the gate pad and the data pad as compared to the thin film transistor substrate shown in FIG. 5. Accordingly, detailed description of the same components will be omitted.

The data pad 160 illustrated in FIG. 13A includes a data pad middle electrode 164 and a data pad upper electrode 166.

The data pad intermediate electrode 164 is formed of the same metal on the same plane as the data line 104 and is connected to the data line 104. The data pad intermediate electrode 164 is formed in the data contact hole 146 with a width narrower than that of the data contact hole 146.

The data pad upper electrode 166 is connected to the data pad intermediate electrode 164 and the interlayer insulating layer 126 exposed through the data contact hole 146. Accordingly, the water flowing from the outside is blocked by the data pad upper electrode 166 and the edge of the data pad middle electrode 164 and the organic passivation layer are interposed by the interlayer insulating layer 126 exposed through the data contact hole 146. The distance between the edges of 118 is farther away so that the path of penetration of moisture is farther away. As a result, corrosion and transfer of the data pad intermediate electrode 164 and the data line 104 due to moisture introduced from the outside are prevented.

In addition, the data pad upper electrode 166 has a relatively smaller contact area with the data pad intermediate electrode 164 having a width smaller than that of the data contact hole 146. Accordingly, even if a pinhole phenomenon occurs in the data pad upper electrode 166, the probability of corrosion of the data pad middle electrode 164 is reduced.

The gate pad 150 illustrated in FIG. 13B includes a gate pad lower electrode 152 and a gate pad upper electrode 156.

The gate pad lower electrode 152 is formed of the same metal on the same plane as the gate line 102 and connected to the gate line 102. The gate pad lower electrode 152 is formed to be narrower than the gate contact hole 148 in the gate contact hole 148 penetrating the gate insulating layer 112 and the interlayer insulating layer 126.

The gate pad upper electrode 156 is connected to the gate pad lower electrode 152 and the substrate 101 exposed through the gate contact hole 148. Accordingly, the water flowing from the outside is blocked by the gate pad upper electrode 156 and the edge of the gate pad lower electrode 152 and the organic passivation layer are exposed by the interlayer insulating layer 126 exposed through the gate contact hole 148. The distance between the edges of 118 is farther away so that the path of penetration of moisture is farther away. As a result, corrosion and transfer of the gate pad lower electrode 152 and the gate line 102 due to moisture introduced from the outside are prevented.

In addition, the contact area of the gate pad upper electrode 156 with the gate pad lower electrode 152 having a width smaller than that of the gate contact hole 148 is relatively reduced. Accordingly, even if a pinhole phenomenon occurs in the gate pad upper electrode 156, the probability of corrosion of the gate pad lower electrode 152 is reduced.

As described above, in the thin film transistor substrate and the manufacturing method according to the present invention, the first pad electrode connected to the signal line is formed in the pad contact hole with a narrower width than the pad contact hole. As a result, the second pad electrode is connected to the first pad electrode through the pad contact hole. Accordingly, moisture flowing from the outside is blocked by the second pad electrode and between the edge of the first pad electrode and the edge of the organic protective film by an inorganic film (eg, an interlayer insulating film and a substrate) exposed through the pad contact hole. The distance of the farther away the penetration path of moisture. As a result, corrosion and spreading of the pad electrode and the signal line due to moisture introduced from the outside are prevented.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (14)

A first signal pad electrode connected to the signal line and formed on the inorganic film; An organic passivation layer formed to cover the first signal pad electrode; A first pad contact hole penetrating the organic passivation layer to expose the first signal pad electrode and the inorganic layer; A second signal pad electrode formed on the organic passivation layer to be connected to the first signal pad electrode and the inorganic layer through the first pad contact hole; The first signal pad electrode may have a width smaller than the contact hole in the first pad contact hole. The method of claim 1, A pixel electrode formed on the organic protective film; And a thin film transistor connected to the pixel electrode and protected by the organic protective film.  The method of claim 2, The signal line is a gate line connected to the gate electrode of the thin film transistor, A third signal pad electrode connected to the gate line; An interlayer insulating film formed between the first and third signal pad electrodes; And a second pad contact hole for exposing the third signal pad electrode through the interlayer insulating layer, which is the inorganic layer, for connecting the third signal pad electrode and the first signal pad electrode. Transistor substrate. The method of claim 2, The signal line is a data line connected to the source electrode of the thin film transistor, A third signal pad electrode connected to the data line; An interlayer insulating film formed between the first and third signal pad electrodes; And a second pad contact hole for exposing the third signal pad electrode through the interlayer insulating layer, which is the inorganic layer, for connecting the third signal pad electrode and the first signal pad electrode. Transistor substrate. The method of claim 4, wherein And a contact unit for connecting the data line and the third signal pad electrode. The contact portion A data link extending from the third signal pad electrode; And a link contact hole exposing a gate insulating film formed to cover the data link. The method of claim 1, The area of the second signal pad electrode formed on the organic passivation layer is increased as the distance between the edge of the first signal pad electrode exposed through the first pad contact hole and the edge of the organic passivation layer is closer. Thin film transistor substrate.  The method of claim 2, The thin film transistor is a thin film transistor substrate, characterized in that the polysilicon thin film transistor. Forming a first signal pad electrode connected to the signal line on the inorganic layer; Forming an organic passivation layer to cover the first signal pad electrode; Forming a first pad contact hole penetrating the organic passivation layer to expose the first signal pad electrode and the inorganic layer; Forming a second signal pad electrode on the organic passivation layer so as to be connected to the first signal pad electrode and the inorganic layer through the first pad contact hole; The first signal pad electrode may have a width smaller than the contact hole in the first pad contact hole. The method of claim 8, Forming a thin film transistor under the organic protective film; And forming a pixel electrode on the organic passivation layer. The method of claim 9, The signal line is a gate line connected to the gate electrode of the thin film transistor, Forming a third signal pad electrode connected to the gate line; Forming an interlayer insulating film between the first and third signal pad electrodes; And forming a second pad contact hole through the interlayer insulating layer, which is the inorganic layer, to expose the third signal pad electrode to connect the third signal pad electrode and the first signal pad electrode. A method of manufacturing a thin film transistor substrate, characterized in that.  The method of claim 9, The signal line is a data line connected to the source electrode of the thin film transistor, Forming a third signal pad electrode connected to the data line; Forming an interlayer insulating film between the first and third signal pad electrodes; And forming a second pad contact hole through the interlayer insulating layer, which is the inorganic layer, to expose the third signal pad electrode to connect the third signal pad electrode and the first signal pad electrode. A method of manufacturing a thin film transistor substrate, characterized in that.  The method of claim 11, Forming a contact portion for connecting the data line and the third signal pad electrode; Forming the contact portion Forming a data link extending from the third signal pad electrode; And forming a link contact hole exposing the gate insulating film formed to cover the data link.  The method of claim 8, The area of the second signal pad electrode formed on the organic passivation layer is increased as the distance between the edge of the first signal pad electrode exposed through the first pad contact hole and the edge of the organic passivation layer is closer. Method of manufacturing a thin film transistor substrate. The method of claim 9, Forming the thin film transistor is Forming a polysilicon type active layer on the substrate; Forming a gate electrode on the gate insulating film formed to cover the active layer; And forming a source and a drain electrode on the interlayer insulating layer which is connected to each of the source region and the drain region of the active layer and covers the gate electrode.

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