KR20060096744A - Control apparatus for clock of modem - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a clock variable control apparatus, in particular, capable of varying a clock of a modem.

A clock variable control apparatus for a modem according to the present invention includes a clock generator for generating a system clock; A clock divider for dividing the generated clock into a predetermined value; A clock gating controller for outputting a clock gate signal for controlling the output of the clock; And a logic multiplication logic for generating an input clock of the demultiplexer using the clock and the clock gate signal.

Terminal, Modem, Clock, Division, Demultiplexer

Description

Control apparatus for clock of modem

1 is a block diagram showing a clock control device of a conventional modem.

FIG. 2 is a diagram showing an example of clock waveforms in each part of FIG.

3 is a block diagram illustrating an apparatus for controlling a variable clock of a modem according to an exemplary embodiment of the present invention.

FIG. 4 is a diagram showing an example of clock waveforms in each part of FIG.

<Description of the symbols for the main parts of the drawings>

201 ... clock generator 202 ... clock gating controller

203 ... clock divider 204 ... lookup table

205 Logical logic 206 Output buffer

207 Demultiplexer 208 Receiver

The present invention relates to a clock generation control device of a modem, in particular in a mobile communication system.

In the Wide-band Code Division Multiple Access (WCDMA) standard, a specific service class is assigned according to the performance of the terminal, and the maximum data rate to be processed by the demultiplexer is determined according to the class. For example, for a 384 Kbps terminal, the final output of the demultiplexer cannot exceed a maximum of 6400 bits per 10msec and the input cannot exceed 19200 bits per 10msec. This limitation of the specification defines the maximum operating clock of the demultiplexer implemented in hardware. A clock control apparatus for controlling such an operation clock is shown in FIG.

1 is a block diagram showing a clock control apparatus of a conventional modem.

Referring to FIG. 1, a clock gating controller for outputting a clock gate signal to supply a clock only to an operation of the clock generator 100 and a demultiplexer 104 generating a system clock. 101, AND logic 102 in which an AND clock is actually performed, and a clock for delivering the output of the AND logic 102 to the demultiplexer 104 at a predetermined intensity. A buffer 103, a demultiplexer 104 for receiving a clock from the clock buffer 103, and demultiplexing a signal input from a receiver 105, and a receiver 105.

Such a clock control device is as shown in FIG.

The demultiplexer 104 of the modem operates only in a section in which a clock is supplied. To this end, when the clock is generated by the clock generator 100, the clock gating controller 101 controls the clock supply using the clock gate signal clock_gate.

When the clock gate signal is output from the clock gating control unit 101, the AND logic 102 outputs the AND result of the clock and the gate signal of the clock generator 100, and the output of the AND logic 102 is a clock buffer. Amplified to sufficient intensity by 103 and passed to demultiplexer 104. Accordingly, the demultiplexer 104 operates, and demultiplexes the data transmitted from the receiver 105. Here, the clock gating controller 101 may be external logic or a microprocessor.

Referring to FIG. 2, the output of the clock generator 100 is a system clock 110, the clock gate signal 111 is a mask signal generated by the clock gating control unit 101, and a demultiplexer. Will define the interval to operate. This is the interval of the clock (Demux clock) 112, which is supplied to the demultiplexer 104 by the clock gate signal 111 by the logical product of the AND logic 102.

In other words, the demultiplexer clock 112 is an operation of supplying the signals of the clock gate signal 111 and the system clock 110 to the demultiplexer 104 via the AND logic 102 and the clock buffer 103. It is a clock. Therefore, the demultiplexer 104 receives the clock only in a defined operating period instead of receiving the system clock 110, thereby avoiding unnecessary power consumption through clock switching.

Here, the demultiplexer clock 112 actually operates in a clock for active period, and the additional clock intervals correspond to an approximate operating period.

However, in the related art, the clock provided to the demultiplexer uses a system clock determined according to the maximum operating speed of the demultiplexer. Accordingly, the clock gate period is determined not by the demultiplexer's operation (active), but by external logic or by the microprocessor's decision, and thus, the approximate operation period is determined instead of determining the correct operation period of the demultiplexer.

Therefore, in the demultiplexer, high-speed clock switching occurs in an unnecessary operating period, thereby increasing unnecessary power consumption. In addition, high-speed clock switching of the demultiplexer during the actual operation of the demultiplexer is not performed because all the modules of the demultiplexer operate simultaneously in the interval, but the configuration functions operate sequentially. Even unnecessary power consumption is required.

The first object of the present invention is to control the clock so that the demultiplexer of the modem does not unnecessarily fast switch.

The second object of the present invention is to allow a system clock speed to be varied and output according to the service data rate of the modem.

Clock variable control apparatus of the modem according to the present invention for achieving the above object,

A clock generator for generating a system clock;

A clock divider for dividing the generated clock into a predetermined value;

A clock gating controller for outputting a clock gate signal for controlling the output of the clock;

And a logic multiplication logic for generating an input clock of the demultiplexer using the clock and the clock gate signal.

The clock divider may further include a lookup table configured to adjust the system clock to be divided by a predetermined divider value in order to divide the operating clock of the demultiplexer at a required speed.

Preferably, the lookup table is configured to vary the divided value according to the service data rate of the modem.

Hereinafter, with reference to the accompanying drawings as follows.

3 is a block diagram illustrating a clock variable control apparatus of a modem according to the present invention.

3, a clock generator 201; A clock gating controller (202) for outputting a clock gate signal, and a clock divider (203) for dividing a clock generated from the clock generator (201); A lookup table 204 for outputting a divided value selected by the division select signal divisor_sel to the clock divider 203; Logic logic 205 for generating an input clock using the divided clock and the clock gate signal, a clock buffer 206 for amplifying the output of the logic logic 205 to a required intensity, and a clock buffer 206. The demultiplexer 207 is operated by a clock input from the input signal, and a receiver 208 is provided for providing information necessary for the demultiplexer 207.

Referring to the accompanying drawings, a clock variable control apparatus of a modem according to an embodiment of the present invention as described above is as follows.

As shown in FIG. 3, a clock divider 203 is configured at an output terminal of the clock generator 201, and the clock divider 203 preferably includes a specific division among the divided values stored in the lookup table 204. It is divided by value. At this time, the lookup table 204 selects a specific division value by the division selection signal divisor_sel.

A plurality of division values are stored in the lookup table 204. Each of the stored items Divisor # 1 to #N is divided into division values for dividing the output clock of the clock generator 201 according to the service data rate of the demultiplexer 207. Is defined. When a call is connected to a terminal, the base station and the terminal negotiate a service grade to determine a processing data rate. At this time, when the processing data rate is determined, the division value of each item (Divisor # 1 to #N) of the lookup table 204 is set to correspond one-to-one.

Accordingly, the lookup table 204 selects the division value by the division selection signal divisor_sel and outputs it to the clock divider 203. Then, the output clock of the clock generator 201 is output from the clock divider 203 at the speed of division (system clk / Divisor i, i is an item index). The divided clock is input to the AND logic 205, and the AND logic 205 logically multiplies the clock gate signal (clock_gate) of the clock gating control unit 202 and the divided clock to an input clock of the demultiplexer 207. The demultiplexer 207 outputs the clock buffer 206 at the required intensity, and the demultiplexer 207 operates by the input clock to demultiplex.

For example, in the case of a 384kbps class terminal, 1 corresponding to the maximum data rate is stored in Divisor # 1 of the lookup table 204, 2 is stored in Divisor # 2, and 4 is stored in Divisor # 3. If the terminal is connected to the base station at 384kbps, Divisor # 1 is selected as the frequency division selection signal divisor_sel corresponding to the data rate. At this time, the clock divider 203 generates and outputs a clock having the same speed as that of the clock generator 201, and is input to the demultiplexer by an AND logic by a clock gate signal.

However, if the terminal is connected at 32 kbps, the maximum output bit of the demultiplexer 207 per 10 msec is 1280 bits, and the maximum input data is 1200 bits. This can be sufficiently handled even with a quarter of the output clock rate of the clock generator 201. Accordingly, in this case, a divisor # 3 of the lookup table is selected through the division select signal to output a clock divided by four divisions (system clock / 4), and the gate is input to the demultiplexer 207. .

An example of such an operation is shown in FIG. 4. In FIG. 4, reference numeral 120 denotes a system clock generated by the clock generator 201 and a clock divided by a divider value (divisor # 1) in the clock divider 203 (Case A). When 121 is selected Divisor # 3 of the lookup table, the clock 121 is a clock of 1/4 of the system clock output through the clock divider 203 (Case B). 122 is a clock gate control signal output from the clock gating control unit 202, 123 is a clock generated by inputting 120 and 122 into the AND logic 205, and 124 is generated by inputting 121 and 122 into the AND logic It is a clock.

In this way, when the division selection signal is applied according to the service data rate of the demultiplexer, the division value is determined by the division selection signal, and the system clock can be divided by the determined division value. It is to be divided into the clock required for the period actually operated.

So far, the present invention has been described with reference to the preferred embodiments, and those skilled in the art to which the present invention pertains to the detailed description of the present invention and other forms of embodiments within the essential technical scope of the present invention. Could be implemented. Here, the essential technical scope of the present invention is shown in the claims, and all differences within the equivalent range will be construed as being included in the present invention.

As described above, the apparatus for controlling a variable clock of a modem may optimize power consumption of the demultiplexer by varying a clock input to the demultiplexer according to a service rate of a connected call. By dividing the input clock as needed, the clock speed can be minimized in unnecessary clock periods to minimize logic switching and reduce power consumption.

In addition, power consumption can be reduced by minimizing the operation of the human module in the actual operating region of the demultiplexer, and power of the clock buffer can also be minimized by reducing switching during the unit time.

Claims (3)

A clock generator for generating a system clock; A clock divider for dividing the generated clock into a predetermined value; A clock gating controller for outputting a clock gate signal for controlling the output of the clock; And a logic multiplication logic for generating an input clock of the demultiplexer using the clock and the clock gate signal. The method of claim 1, The clock divider further comprises a look-up table for adjusting the system clock to divide the system clock by a predetermined dividing value in order to divide the operation clock of the demultiplexer at a required speed. . The method of claim 1, And the lookup table varies the divided value according to the service data rate of the modem.

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