KR20060096385A - Frame structure for fec supporting transmission of variable-length frames in tdma system - Google Patents

Abstract

The FEC frame structure according to the present invention includes a frame start part for notifying the start of a Forward Error Correction (FEC) frame, a message part including a message which is Ethernet MAC data or variable length frame data, and a first message for notifying the end of the message. And a second terminating part which notifies the end of the forward error correction frame, and a parity part carrying a parity value for the message and originating from a transmission medium using a Reed-Solomon coded FEC. In the process of correcting the error, the FEC encoding / decoding of the frame unit is processed, and bypassing the FEC during operation does not affect the overall transmission delay time, optimizes the time delay by the shortened codeword, and The FEC encoding / decoding processing delay time can be managed for the same frame.

FEC, Reed-Solomon, RS, PON, EPON, Ethernet-PON, TDMA

Description

Frame structure for FEC supporting transmission of variable-length frames in TDMA system}

1 is an Ethernet-PON system as an example of a prior art TDMA system.

2 is a block diagram of a general Reed-Solomon encoder according to the prior art.

3 is a block diagram of a general Reed-Solomon decoder according to the prior art.

4 is a structural diagram of a variable length data frame according to the present invention.

5 is a block diagram showing the configuration of a Reed-Solomon encoder according to the present invention.

6 is a block diagram showing the configuration of a Reed-Solomon decoder according to the present invention.

7 is a flowchart illustrating a process of a method of transmitting an FEC frame according to the present invention.

8 is a flowchart illustrating a process of receiving a FEC frame according to the present invention.

9 is a timing diagram of a Reed-Solomon decoder according to the present invention.

The present invention performs frame-by-frame forward error correction (hereinafter referred to as "FEC") encoding / decoding for frames of various lengths in a time division multiplex transmission system, and is optimized for a transmission rate that provides the same processing delay time for all frames. In addition, the present invention relates to an FEC frame structure for variable length frame transmission in a time division multiplex transmission system.

In order to understand the effect of the processing delay time of FEC (Forward Error Correction) in the TDMA system, an example of a full duplex time division multiplex transmission system is a prior art Ethernet-PON (Passive Optical Network) system.

As shown in FIG. 1, an Ethernet-PON (Passive Optical Network) system is branched by using an optical link termination (OLT) as a vertex, and in an PON distribution network structure consisting of an optical network unit (ONU) connected to each branch point, It performs physical matching and Ethernet link matching for communication between ONUs and for communication between ONUs and ONUs. The transmission from the ONU side to the OLT is called upstream and the transmission from the OLT to the ONU is called downstream. In the PON structure, the downlink Ethernet frame has a broadcast transmission characteristic that all ONUs receive. However, uplink transmission is characterized in that one ONU cannot directly transmit an Ethernet frame to another ONU other than the OLT.

Due to the characteristics of the PON structure, when a plurality of ONUs transmits an Ethernet frame uplink to the OLT, a multipoint control protocol (MPCP) function is used to control the frame transmission time of each ONU so that no collision between frames occurs. The OLT determines the uplink transmission time available to each ONU and informs the ONU. The ONU transmits the Ethernet frame uplink to the OLT during the transmission time determined by the OLT.

At this time, since the OLT needs to know whether there is an Ethernet frame to be transmitted from each ONU to the OLT in order to determine the transmission time, the ONU notifies the OLT in advance of the existence of an Ethernet frame to be transmitted upward. As described above, information for uplink TDMA is transferred between the OLT and the ONU, and the MAC (Media Access Control) Control sublayer generates and terminates an MPCP MAC Control frame having this information.

In the PON distribution network, each ONU is located at an arbitrary distance from the OLT. Therefore, when allocating an uplink transmission time to an ONU by TDMA method, it should be corrected by RTT (transmission delay time, round trip time) so that the collision is not time-aligned when receiving the uplink signal from the OLT. Therefore, in order to compensate for the RTT, the RTT needs to be measured. This process is called ranging. In order to accurately achieve this ranging, the data processing delay time of each OLT and ONU must be constant for all Ethernet frames, and the same applies to the FEC.

When using FEC, additional information must be conveyed in addition to the transmission data for error correction, which reduces the overall data rate. Therefore, if the transmission medium is good, the FEC function should be turned off. Referring to the Ethernet-PON system of FIG. 1 as an example, since the distance between the OLT and each ONU is different, each link has different transmission medium characteristics. Thus, any link must employ the FEC to satisfy the link quality required by the system, while other arbitrary links may satisfy the required link quality without the FEC. In this case, the ONU of the link that does not require FEC can block the FEC function to prevent the rate reduction due to the transmission of additional information for the FEC.

However, in this case, the OLT receives both FEC encoded frames and unencoded frames from a plurality of ONUs sharing a transmission medium, and data frames transmitted to any ONU are transmitted by FEC encoding and other arbitrary ONUs. The data frame to be sent must be transmitted without FEC encoding. Therefore, the FEC located in the OLT should be able to turn on / off the FEC function on a frame-by-frame basis. The simplest method is to bypass the FEC function.

However, bypassing the FEC function during data transmission in the TDMA system has the same effect as changing the delay time of the FEC, making it difficult for the master to control the medium. Therefore, FEC bypass must be made through matching delay considering processing delay time in FEC functional block.

Reed-Solomon code, widely used in FEC, is the most powerful block code for burst error, and is generally operated on Galois Field GF 256 and represented by RS (n, k, t). Where n is the length of the Reed-Solomon codeword, k is the length of the message, and t is the number of bytes for which error correction is possible. In other words, the Reed-Solomon code has n bytes of codeword c (x) by adding (nk) bytes of parity r (x) to k bytes of message m (x) as shown in Equation 1 below. In this case, all errors up to an arbitrary t byte occurring within the n byte codeword can be corrected.

The Reed-Solomon encoder multiplies m (x) by x ^2t and adds the remainder divided by g (x) to m (x) to generate c (x), and generally has a structure as shown in FIG. .

2 shows an encoder of RS (255, 239, 8) as an example. When the selection signal X is '1', the Reed-Solomon encoder receives an input message and divides the generated polynomial by g (x). After the last message is entered, r (x) is stored in the register. When the selection signal becomes Y, the stored r (x) is sequentially output.

The Reed-Solomon decoder finds the position and size of the error from the received codeword r (x) = c (x) + e (x) and generates the error e (x), and the error e (x) from r (x). It is responsible for the function of restoring the c (x) by removing the, for this purpose generally as shown in Figure 3 (syndrome generation block 301, error location polynomial block 302, error location detection block 303, It consists of an error magnitude detection block 304 and an error correction block 305. The syndrome generation block 301 generates a syndrome polynomial S (x) for an error by substituting the root of the generation polynomial g (x) into the received data r (x).

및 에러 크기 다항식

를 생성한다. 에러 위치 검출기(303) 는 일반적으로 Chien search 알고리즘을 이용하여 에러 위치 다항식

로부터 에러의 위치를 검출하고, 에러 크기 검출기(304)는 일반적으로 Forney 알고리즘을 이용하여 에러 크기 다항식

로부터 에러의 크기를 검출한다. 검출된 에러의 크기 및 위치는 논리곱(AND) 되어 해당 위치의 에러값 e(x)가 되며, e(x)는 에러 보정 블록(305)에서 Reed-Solomon 디코딩 처리 시간만큼 지연된 r(x)에서 빼지게 되어 에러가 정정된 코드워드 c(x)를 출력한다.The error position polynomial block 302 is an error position polynomial from the calculated syndrome polynomial S (x).

And error magnitude polynomials

Create The error location detector 303 generally uses the Chien search algorithm to find the error location polynomial

Detect the location of the error, and the error magnitude detector 304 generally uses the Forney algorithm to determine the error magnitude polynomial

The magnitude of the error is detected from The magnitude and position of the detected error are ANDed to become the error value e (x) of the corresponding position, and e (x) is r (x) delayed by the Reed-Solomon decoding processing time in the error correction block 305. The codeword c (x) is corrected by subtracting from the error.

The Reed-Solomon encoder outputs the input message directly, so there is no theoretical delay. However, when processing shortened code, there is a delay caused by zero-padding. For example, if the length of the message is (k-l), the actual message is shown in Equation 2 below, and the zero-padding message is shown in Equation 3 below.

With zero-padding, the initial l bytes of the codeword are zeros, which are removed before the output of the Reed-Solomon encoder. In this process, there are l bytes of space between successive Reed-Solomon codewords and shortened codewords. To compensate for this, the output of the normal codeword must be delayed by l byte time. In the Reed-Solomon decoder, zero-padding is processed as in the encoder and the padded zero is removed in the final error corrected codeword output process, which also causes a processing delay. In case of continuous Ethernet frame transmission, delay caused by zero-padding causes overlapping of codewords between adjacent frames. To prevent this, inter-frame gap (IFG) must be given between consecutive frames in consideration of zero-padding. . This results in a substantial increase in frame length, leading to a decrease in transmission rates. In a real Ethernet frame transmission environment, zero-padding causes a reduction in transmission rates of about 35%.

Therefore, there is a need for a method that can effectively reduce the rate reduction due to zero-padding, and a method that can guarantee the same delay for different length frames in this process.

The technical problem to be solved by the present invention is to solve the above problems, and in a full-duplex time division multiplexing system that transmits frames of different lengths, the error caused by the transmission medium is corrected using a Reed-Solomon code. By processing FEC encoding / decoding per frame in the process of processing, bypassing FEC during operation does not affect the overall transmission delay time, and virtually processes zero-padding required in processing shortened codewords. It is to provide an FEC frame structure for variable length frame transmission in a time division multiplex transmission system to eliminate zero-padding delay time and to equalize the FEC encoding / decoding processing delay time for different length frames.

In order to achieve the above technical problem, the FEC frame structure according to the present invention includes a message message including a frame start part for notifying the start of a forward error correction (FEC) frame, Ethernet MAC data, or variable length frame data. And a first terminating unit notifying the end of the message, a parity unit carrying a parity value for the message, and a second terminating unit notifying the end of the forward error correction frame.

In order to achieve the above technical problem, the FEC frame transmission apparatus according to the present invention comprises: a selection unit for receiving input data and determining whether to perform forward error correction encoding; A Reed-Solomon encoding assembler which receives the data for which the selection unit decides to perform forward error correction encoding and divides the data into k-byte units (where k is a positive integer) and outputs the divided data block; A Reed Solomon encoder receiving the message block and performing Reed Solomon encoding; And an output control unit which receives the parity generated as a result of the Reed Solomon encoding and sequentially outputs the message block and the parity, or outputs input data determined by the selection unit to perform forward error correction encoding is unnecessary. .

In order to achieve the above technical problem, the FEC frame receiving apparatus according to the present invention comprises: a first receiving unit which determines whether a received frame is an FEC encoded frame; A Reed Solomon decoder which receives the FEC encoded frame from the first receiver and performs Reed Solomon decoding with the same processing time regardless of the length of the FEC encoded frame; A matching delay unit which receives a non-FEC encoded reception frame from the first receiver and delays the FEC encoded reception frame by a time for decoding or delays and outputs the FEC frame identifier; And a frame recombination unit configured to form and output an original FEC frame based on the FED frame identifier passed through the Reed Solomon decoded codeword and the matching delay unit.

According to an aspect of the present invention, there is provided a method for transmitting an FEC frame, comprising: determining whether to perform FEC encoding on a frame to be transmitted based on a predetermined identifier of the frame; When performing the FEC encoding, dividing the data in the frame into message blocks in units of k bytes (k is a positive integer) to perform ReedSolomon encoding; And transmitting a frame in which the parity generated as a result of performing the Reed Solomon encoding on the message block and the message block is sequentially combined, or a frame that is not FEC encoded according to the determination of whether to perform the FEC encoding. It is characterized by.

 According to an aspect of the present invention, there is provided a method for receiving an FEC frame, comprising: determining whether a received frame is an FEC encoded frame; If it is determined that the frame is an FEC encoded frame, performing Reed Solomon decoding on the FEC encoded frame with the same processing time regardless of its length; If it is determined that the frame is not FEC-encoded, delaying the FEC-encoded received frame by a time for decoding or delaying and outputting the FEC frame identifier; And forming the original FEC frame based on the decoded codeword and the identifier of the delayed FEC frame as a result of the decoding of the Reed Solomon decoding step.

To achieve virtual zero-padding for shortened codewords and to ensure the same processing time delay for different length frames, the Reed-Solomon encoder outputs the parity output in parallel to one clock, and the Reed-Solomon decoder produces an error. Pipelining the error position polynomial and the error magnitude polynomial, which are output values of the position polynomial block, is passed to the error position detection block and the error size detection block, and the initial values of the error position detection block and the error size detection block are look-up according to the frame length. It gets input from the table. In this way, the delay caused by the actual zero-padding does not occur in the process of shortened codewords, but since the virtual zero-padding is performed, accurate error correction is performed in the same way as in the case of zero-padding. Solomon encoding / decoding delays are managed equally.

Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the device and method for a preferred embodiment of the present invention.

First, the FEC frame will be described with reference to FIG. 4. 4 shows the structure of an FEC frame for a forward error correction apparatus for variable length frame transmission in a time division multiplex transmission system. The FEC frame receives an Ethernet frame having a maximum length of 1522 bytes or an arbitrary variable length frame 402 and adds 5 bytes of S_FEC 401 which is an identifier indicating the start of the FEC frame before the first byte position of the frame. The T_FEC 403, which is an identifier indicating the end of the message frame, is added after the last byte of the frame. After T_FEC is added, space 404 for parity, which is additional information of FEC, is added, and T_FEC 405, which is an identifier indicating the end of the FEC frame, is added after the space for parity.

The frame for bypassing without FEC encoding / decoding has no space 404 for parity storage and no T_FEC 405, an identifier indicating the end of FEC, in the FEC frame, and a simplified form of S_FEC 401 and T_FEC 403. Is used to distinguish it from the FEC frame.

The reason why the identifier of the FEC frame is longer than that of the non-FEC frame is to accurately distinguish the beginning and the end of the frame in an error-prone transmission medium environment.

In the present invention, a Reed-Solomon code resistant to burst error is used for FEC encoding / decoding for a variable length frame, and the Reed-Solomon code is operated on the GF 256 so that a codeword of up to 255 bytes is used. Support. As described above, a codeword is generated by adding a message and a parity, and in case of adopting RS (n, k, t), one Reed-Solomon codeword is composed of k bytes of message and (nk) bytes. It consists of parity. Therefore, the length of the transmission frame should not exceed the length k of the message, and as shown in FIG. 4, if the length of the transmission frame, that is, the message exceeds k bytes, the transmission frame is divided into message blocks of k bytes and then Reed-Solomon Sign processing.

In FIG. 4, one transmission frame is divided into M message blocks 406, and the final Mth message block 407 has a length of r (0 <r <k) bytes to form a shortened codeword. . The parity in (n-k) bytes as the result of the Reed-Solomon encoded for each message block is stored in the parity storage space 408 in order. Reed-Solomon decoding requires the reverse process. That is, when one FEC frame is received, the message block and the parity corresponding to the message block are summed from the received frame, reconstructed into one Reed-Solomon codeword, and then decoded. This will be described later.

Next, let's look at the FEC transmitter and its method. In the present invention, the FEC uses a Reed-Solomon code, so the FEC encoder uses a Reed-Solomon encoder. In general, the Reed-Solomon encoder generates a codeword c (x) by multiplying a message m (x) by x ^2t and then adding the remainder divided by the polynomial g (x) to m (x) as shown in FIG. 2. It is composed. However, the existing Reed-Solomon encoder alone is insufficient to process a message having a variable length in accordance with the FEC frame according to the present invention.

Therefore, the FEC frame transmission apparatus according to the present invention includes a Reed-Solomon encoder having an improved structure as shown in FIG. The first input data frame recognizes S_FEC as a FEC frame start identifier or S_FEC in a short form as a non-FEC frame identifier in the bypass control block 510 and determines whether the currently input frame is a frame to be FEC encoded. If the frame is not to be FEC encoded, it is immediately output (step 710). However, if the frame is to perform FEC encoding, the data is input to the Reed-Solomon encoding block assembler 520 and combined into a message block of k-byte units. This message is applied to the division circuit of the Reed-Solomon encoder to generate parity. Immediately after m ₀ is input, the register value of the division circuit becomes a parity value. After the m ₀ is input, all the M message blocks are input in a format in which the m _k of successive message blocks is input to the next clock. At this time, as m _k is input, the MUX 530 of the register input terminal selects 0 to reset the register, and the value of the register is simultaneously stored in the parity buffer 550. In the drawing, the MUX and the register are made corresponding to the number of generated message blocks and perform the same function. Therefore, only one reference number is shown.

In this way, when the Reed-Solomon encoding process for all M message blocks is completed, the Reed-Solomon encoder outputs S_FEC and M message blocks among all FEC frames to date, and the parity buffer 550 outputs M message blocks. M (nk) byte parity generated as a result of encoding are stored (step 720). The output control block 560 outputs the T_FEC 403 immediately after the output of the Mth message block, and then sequentially reads and outputs the parity from the parity buffer 550 and then outputs the T_FEC 405. In this way, the encoding of the shortened code as well as the normal codeword having a length of n bytes can be completed.

In the case of shortened code, the message is composed as shown in Equation 4 below, and the value of the first l byte becomes 0. Since this value keeps all register values the same as the reset state even though the value is input to the Reed-Solomon encoder, Because you do not have to.

In this way, the Reed-Solomon encoder has the same effect as zero-padding for shortened code (step 730).

Next, an FEC frame receiving apparatus and a method thereof will be described. In the present invention, the FEC decoder also uses the Reed-Solomon decoder, and the Reed-Solomon decoder also improved the structure of the general form of the decoder as shown in FIG. First, the received frame is input to the Reed-Solomon decoding block re-assembler 610 to find an S_FEC or a simple S_FEC identifier and distinguish whether or not the frame is FEC-encoded. Output is through (step 810).

Matching delay (620) is to give the same time delay as the processing time delay of the Reed-Solomon decoder. When both FEC encoded frames and FEC unencoded frames have to be processed, In order to prevent a problem in that the first inputted FEC encoded frame is output later than the late inputted FEC encoded frame or simultaneously outputted due to the processing time delay occurring during the decoding process (step 830).

The Reed-Solomon decoding block re-assembler 610 receives one input FEC frame as a frame buffer and divides it into M message blocks and M parities and stores them in the data buffer 611 and the parity buffer 613, respectively. In this case, the data buffer 611 and the parity buffer 613 are elastic buffers, respectively, and sequentially store input frame data, and provide the same time delay for all input data. FEC frame identifiers other than messages and parity are not stored in the buffer, and they are directly applied to the frame re-assembler 640 through a matching delay 620.

The frame re-assembler 640 reconstructs the original FEC frame using the Reed-Solomon decoded codeword and the identifier passed through the matching delay 620. Messages and parities stored in the data buffer 611 and the parity buffer 513 are sequentially input to the Reed-Solomon decoder, and the input order is the first message, the first parity, the second message, the second parity,... This is the same as the M-th message and the M-th parity. By doing so, M Reed-Solomon codewords are input.

The Reed-Solomon decoder first calculates the syndrome with the input codeword. In general, the syndrome calculation is obtained by adding the result of substituting all the roots of the polynomial of the generated polynomial to the n-byte codeword inputted. The syndrome is output immediately after the last codeword is input. The codeword length counter 640 measures the length of an input codeword while calculating the syndrome in the syndrome generating circuit 630. This is to accurately measure the length of the shortened codeword. The calculated syndrome S (x) is input to the error locator polynomial block 650 and used to generate the error position polynomial Λ (x) and the error magnitude polynomial Ω (x).

The error locator polynomial block 650 is implemented using a recursive modified Euclid algorithm to have the same time delay, and the processing time delay takes 16 byte clock regardless of the codeword length. The error location polynomial Λ (x) and error magnitude polynomial Ω (x), which are outputs of the error locator polynomial block 650, are then input to the error locator 670 and the error magnitude block 675 to be used to find the error location and magnitude. do.

However, as shown in the Reed-Solomon decoding timing example of FIG. 7, when the input codeword is composed of one long codeword and several short codewords consecutively, the error position polynomial Λ (x) and the error magnitude polynomial Ω ( Up to x) has the same time delay and is output in accordance with the codeword length, but the error position detector using the Chien search algorithm and the error magnitude detector using the Forney algorithm use the output Λ (x) and Ω (x). Since the processing time of the time corresponding to the length of the codeword used to generate the corresponding Λ (x) and Ω (x) is required, a short length codeword when Λ (x) and Ω (x) is directly input Generated by Λ (x) and Ω (x) are lost. This phenomenon is caused by supporting frames of different lengths at the same time. This problem occurs because the encoder does not zero-padding while processing the shortened codeword.

In the present invention, after storing Λ (x) and Ω (x) in the buffers 661 and 662, the error position detector 670 and the error magnitude detector 675 have processed one codeword, The problem is solved by the method of giving x) and Ω (x) values, and the three buffers 661, 662 and 663 of FIG. 6 buffer Λ (x), Ω (x) and the length of the codeword, respectively. Through this buffering, Λ (x) and Ω (x) change time delays such as Λ '(x) and Ω' (x), and as shown in FIG. 7, Λ '(x) and Ω' It can be seen that (x) provides the same time delay for codewords of different lengths.

의 값을 순차적으로 대입하여 다항식을 계산하여 그 결과 값이 0 이 되면 해당하는 위치가 에러의 위치임을 알 수 있다.As a result, by buffering the lengths of Λ (x), Ω (x) and codewords, the Reed-Solomon decoder uses the same time delay for all frames of varying length without zero-padding to process shortened codewords. Will be provided. However, despite all the same time delays, another problem remains. Using the Chien search algorithm, a common method used in error location detectors, the inverse of the error location polynomial contains information at the location of the error, so to find the location of the error,

The polynomial is calculated by sequentially substituting the value of, and when the result is 0, the corresponding position is the position of error.

중에서 하나가 된다.In the process of implementing the Chien search algorithm, one modern assignment circuit is repeated n times to reduce hardware. If the length of the input codeword is n (= 255), the initial value is α ^0, but the codewords having different lengths are used. If is entered, the initial value is

Becomes one of

Therefore, in the present invention, 255 initial values are configured in a look-up table in ROM format, and the codeword length checked by the codeword length counter 640 is used as an address for selecting a value of the look-up table. The initial value was selected according to the length of. At this time, the selected initial value is used in the same error magnitude detector using the Forney algorithm, so only one look-up table needs to be configured. When both the position and the magnitude of the error are determined through the above process, the error value is obtained in the form of an AND 685 of the error position and the magnitude. If the error value e (x) is obtained, the error value is subtracted from the codeword passing through the buffer 690 considering the processing time delay of the Reed-Solomon decoder, and as a result, the error is corrected (step 820). . The error-corrected codeword is input to the frame re-assembler block 640 and reconstructed into an FEC frame, and then the parity storage space 408 is zero padded and output (step 840).

The present invention guarantees the same delay for a frame having an arbitrary length and optimizes the rate reduction due to a shortened code. The present invention divides various lengths of transmission frames into arbitrary length block combinations and encodes / decodes each of them. In this case, if the final block divided is smaller than the required length, virtual zero-padding is processed. In this case, overlapping between codewords occurs in the process of processing blocks of different lengths, which is solved by processing the pipeline. Also, the initial values of the error position and magnitude detector are loaded using the look-up table. Therefore, the same delay is guaranteed for frames having arbitrary lengths, and the rate reduction caused by the shortened code can be optimized.

The FEC frame transmission and reception method according to the present invention can also be embodied as computer readable codes on a computer readable recording medium. Computer-readable recording media include all types of recording devices that store data that can be read by a computer system. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage, and the like, which are also implemented in the form of a carrier wave (for example, transmission over the Internet). It also includes. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

The best embodiments have been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, according to the FEC frame structure according to the present invention, using the FED of the Reed-Solomon coded method to process the FEC encoding / decoding of the frame unit in the process of correcting the error caused by the transmission medium, and operating the FEC Even if bypassed, it does not affect the overall transmission delay time, optimizes the time delay caused by the shortened codeword, and manages the same FEC encoding / decoding processing delay time for different length frames.

Claims (3)

A frame start unit for indicating a start of a Forward Error Correction (FEC) frame; A message unit including a message which is Ethernet MAC data or variable length frame data; A first terminating unit notifying the end of the message; A parity unit carrying a parity value for the message; And And a second terminating unit notifying the end of the forward error correcting frame. The forward error correcting frame structure for variable length frame transmission in a time division multiplexing system. The method of claim 1, wherein the parity unit The message is divided into a message block consisting of k bytes (where k is a positive integer), and the variable length frame transmission is performed in a time division multiplex transmission system, characterized by parity values calculated for each divided message block. Forward error correction frame structure. The method of claim 1, The forward error correction frame structure for variable length frame transmission in a time division multiplexing transmission system, characterized in that it does not include the parity unit and the second termination unit when no forward error correction is applied.

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