KR20060094999A - Light emitting display and driving method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting display device and a driving method thereof capable of improving the image quality by accelerating the charging time of low grayscale data.

According to the present invention, there is provided a light emitting display device comprising: an image display unit including pixel cells formed in regions defined by gate lines and data lines; A gate driver for driving the gate line; A current type data driver for generating a gradation current signal corresponding to the gradation value of the input data signal and supplying the gradation current signal to the data line; And a low gradation voltage supply driver for generating a low gradation voltage according to the gradation value of the data signal, and supplying the generated low gradation voltage to the data line simultaneously with the gradation current signal.

According to this configuration, when the gradation current signal supplied to the pixel cell is low gradation, the charging time of the pixel cell for low gradation data can be increased by supplying the low gradation voltage to the data line at the same time as the low gradation current signal. . Therefore, the present invention can prevent the deterioration of image quality due to the charging time of the pixel cell when displaying low grayscale data.

Pixel cell, charging time, low gradation, current signal, decoder

Description

LIGHT EMITTING DISPLAY AND DRIVING METHOD THEREOF

1 is a view showing a light emitting display device according to the related art.

FIG. 2 is a circuit diagram illustrating a pixel cell shown in FIG. 1.

3 illustrates a light emitting display device according to an exemplary embodiment of the present invention.

4 is a diagram illustrating the low gray voltage supply driver shown in FIG. 3; FIG.

<Explanation of Signs of Major Parts of Drawings>

16, 116: image display unit 18, 118: gate driver

20, 120: data driver 28, 128: timing controller

30: pixel circuit 122: low gradation voltage supply driver

140: low gray voltage generator 142: decoder

144: shift register 146: output unit

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a light emitting display device, and more particularly, to a light emitting display device and a driving method thereof capable of improving the image quality by accelerating the charging time of low grayscale data.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such flat panel displays include a liquid crystal display, a field emission display, a plasma display panel, a light emitting display, and the like.

Among flat panel displays, a light emitting display device is a self-light emitting device that emits a phosphor by recombination of electrons and holes, and is classified into an inorganic light emitting device using an inorganic compound as a phosphor and an organic light emitting device using an organic compound as a phosphor. Such a light emitting display device is expected to be a next generation display device because it has many advantages such as low voltage driving, self-emission, thin film type, wide viewing angle, fast response speed, and high contrast.

The organic light emitting device is usually composed of an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer stacked between a cathode and an anode. In the light emitting display device using the organic light emitting diode, when a predetermined voltage is applied between the anode and the cathode, electrons generated from the cathode move to the light emitting layer through the electron injection layer and the electron transport layer, and holes generated from the anode are injected into the hole injection layer. It moves toward the light emitting layer through the hole transport layer. Accordingly, the light emitting layer emits light by recombination of electrons and holes supplied from the electron transporting layer and the hole transporting layer.

Referring to FIG. 1, a light emitting display device according to a related art includes an image display unit 16 including pixel cells PE formed in regions defined by a gate line GL and a data line DL, and A gate driver 18 driving the gate lines GL, a gradation current signal to the data lines DL, a current type data driver 20, a gate driver 18 and a current type data driver 20 It includes a timing controller 28 for controlling.

The timing controller 28 generates gate control signals GCS for controlling the driving timing of the gate driver 18. In addition, the timing controller 28 generates a data control signal DCS for controlling the driving timing of the current type data driver 20, and the external source data RGB suitable for driving the image display unit 16. Arranged so as to supply to the current data driver 20 as a data signal (Data).

The gate driver 18 generates gate pulses for sequentially selecting the gate lines GL in response to the gate control signals GCS from the timing controller 28, and sequentially supplies the gate pulses to the gate lines GL. do.

The current type data driver 20 converts the data signal Data from the timing controller 28 into a gradation current signal in response to the data control signals DCS supplied from the timing controller 28 to convert the data lines DL. ) Is supplied to the pixel cell PE. That is, the current type data driver 20 generates a gradation current signal corresponding to the gradation value of the data signal Data and supplies it to the data lines DL.

Each of the pixel cells PE is selected when a gate pulse is applied to the gate lines GL to generate light corresponding to the gradation current signal supplied to the data line DL, as shown in FIG. 2. Each of the pixel cells PE is equivalently represented by a diode Diode connected between the data line DL and the gate line GL.

Each of the pixel cells PE includes a first power line VDD, a pixel circuit 30 connected to a data line DL and a gate line GL, and a pixel circuit 30 and a second power line GND. And a light emitting element (OLED) connected therebetween.

The pixel circuit 30 includes a first thin film transistor (TFT) T1 connected between the first power supply line VDD and the light emitting device OLED, and the first TFT T1. And a second TFT (T2) formed to form a current mirror circuit, a third TFT (T3) connected to a data line (DL) and a second TFT (T2), and a first and a second TFT ( A capacitor connected to the first node n1, which is the gate electrode of T1, T2, and the fourth TFT T4 connected to the third TFT T3, and to the first node n1 and the first power line VDD. (Cst) is provided. Here, the TFT may be a P-type electron metal oxide semiconductor field effect transistor (MOSFET, Metal-Oxide Semiconductor Field Effect Transistor).

The source electrode of the first TFT T1 is electrically connected to the first power line VDD, and the drain electrode is electrically connected to the anode electrode of the light emitting element OLED. Further, the gate electrode of the first TFT (T1) is electrically connected to the first node n1, that is, the gate electrode of the second TFT (T2).

The source electrode of the second TFT T2 is electrically connected to the first power line VDD, and the drain electrode is commonly connected to the drain terminal of the third TFT T3 and the source terminal of the fourth switching TFT T4. do. In addition, the gate electrode of the second TFT T2 is electrically connected to the first node n1, that is, the gate electrode of the first TFT T1. This second TFT T2 is electrically connected with the first TFT T1 to form a current mirror circuit. Accordingly, assuming that the first and second TFTs T1 and T2 have the same channel width, the magnitudes of the gradation current signals flowing through the first and second TFTs T1 and T2 are the same for the same gradation current signals. Done.

The source electrode of the third TFT T3 is electrically connected to the data line DL, and the drain electrode is electrically connected to the source electrode of the fourth TFT T4. In addition, the gate electrode of the third TFT T3 is electrically connected to the gate line GL.

The source electrode of the fourth TFT T4 is electrically connected to the drain electrode of the third TFT T3, and the drain electrode is electrically connected to the first node n1. In addition, the gate electrode of the fourth TFT T4 is electrically connected to the gate line GL.

The first electrode of the capacitor Cst is electrically connected to the first node n1, and the second electrode is electrically connected to the first power line VDD. The capacitor Cst stores a voltage corresponding to the gradation current signal supplied to the first node n1 using the difference voltage between the first node n1 and the first power line VDD, and stores the stored voltage. By using this method, the turn-on state of the first TFT T1 is maintained for one frame.

The anode electrode of the light emitting element OLED is electrically connected to the drain electrode of the first TFT T1, and the cathode electrode is electrically connected to the second power line GND. The light emitting device OLED generates light corresponding to the magnitude of the gradation current signal supplied from the first TFT T1.

The driving method of the light emitting display device according to the related art will be described as follows.

First, the third and fourth TFTs T3 and T4 are turned on by a gate pulse in a low state supplied from the gate driver 18 to the gate line GL. Since the third and fourth TFTs T3 and T4 are turned on at the same time, the gradation current signal supplied from the current type data driver 20 to the data line DL is passed through the third and fourth TFTs T3 and T4. Is supplied to the first node n1. Accordingly, the first and second TFTs T1 and T2 are turned on by the voltage on the first node n1 to emit currents corresponding to the gradation current signals supplied on the first node n1. OLED to emit light. At this time, the capacitor Cst stores the voltage corresponding to the grayscale current signal supplied to the first node n1.

Subsequently, a gate pulse in a high state is supplied from the gate driver 18 to the gate line GL, so that the third and fourth TFTs T3 and T4 are turned off at the same time. By turning off the third and fourth TFTs T3 and T4, the capacitor Cst maintains the turn-on state of the first TFT T1 using the stored voltage. Accordingly, the light emitting device OLED generates light corresponding to the magnitude of the gradation current signal supplied through the first TFT T1 maintained in the on state by the capacitor Cst.

Such a light emitting display device according to the related art supplies a grayscale current signal corresponding to a desired grayscale from the current type data driver 20 to the data line DL in order to drive the pixel cells PE. The voltage of the first node n1 is controlled according to the gradation current signal supplied to the DL to control the amount of current supplied to the light emitting device OLED to generate light having a desired gradation.

In order to drive the pixel cell PE normally, the light emitting display device according to the related art needs to rapidly change the voltage level of the first node n1 to supply a current corresponding to a desired gray level to the light emitting device OLED. At this time, the voltage level of the first node n1 changes rapidly as the magnitude of the gradation current signal supplied to the data line DL changes, but becomes slow as the size becomes smaller.

Accordingly, the light emitting display device according to the related art has a voltage charging time of the first node n1 at a high gray level (eg, 10 grays or more) that supplies a high current to the data line DL when the pixel cell PE is driven. Although there is no problem in the low gray level supplying a low current to the data line DL, a problem occurs in the voltage charging time of the first node n1.

Accordingly, the light emitting display device according to the related art has a problem in that image quality is deteriorated when low grayscale data is displayed.

Accordingly, in order to solve the above problems, the present invention is to provide a light emitting display device and a method of driving the same to improve the image quality by speeding up the charging time of low grayscale data.

In accordance with one or more exemplary embodiments, a light emitting display device includes: an image display unit including pixel cells formed in regions defined by gate lines and data lines; A gate driver for driving the gate line; A current type data driver for generating a gradation current signal corresponding to the gradation value of the input data signal and supplying the gradation current signal to the data line; And a low gradation voltage supply driver for generating a low gradation voltage according to the gradation value of the data signal, and supplying the generated low gradation voltage to the data line simultaneously with the gradation current signal.

In the light emitting display device, the low gray voltage supply driver supplies the low gray voltage to the data line when the gray value of the data signal is 10 gray or less.

In the light emitting display device, the low gray voltage supply driver includes a low gray voltage generator generating n low gray voltages, a shift register generating a shift signal, and decoding the data signal. And a decoder for selecting any one of the n low gray voltages and outputting the same through an output line, and an output unit for supplying a low gray voltage from the decoder to the data line according to the shift signal.

A driving method of a light emitting display device according to an exemplary embodiment of the present invention includes a method of driving a light emitting display device having an image display unit including pixel cells formed in regions defined by gate lines and data lines; Supplying a gate pulse to the gate line; Generating a gradation current signal corresponding to a gradation value of an input data signal and supplying the gradation current signal to the data line in synchronization with the gate pulse; And generating a low gray voltage according to the gray value of the data signal, and supplying the generated low gray voltage to the data line simultaneously with the gray current signal.

In the driving method of the light emitting display device, supplying the low gray voltage to the data line may include generating n low gray voltages, generating a shift signal, Decoding one of the n low gray voltages and outputting the selected low gray voltage; and supplying the selected low gray voltage to the data line according to the shift signal.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

3 is a diagram schematically illustrating a light emitting display device according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a light emitting display device according to an exemplary embodiment of the present invention may include pixel cells PE formed in regions defined by a plurality of gate lines GL1 through GLn and a plurality of data lines DL1 through DLm. An image display unit 116 including the image display unit, a gate driver 118 driving the gate lines GL1 to GLn, and a gray level current signal corresponding to the gray level of the input data signal Data. A low gray voltage is generated in the data lines DL1 through DLm in response to the current type data driver 120 supplied to the DL1 through DLm and the low gray level data signal Data. The low gray voltage supply driver 122, the gate driver 118, and the current type data driver 120 supplying the to the corresponding data lines DL1 to DLm at the same time as the gray level current signal corresponding to the low gray level data signal Data. Controlling the above And a timing controller 128 for supplying a data signal (Data) to the current-type data driver 120 and the low gray level voltage supply driver 122.

Each of the pixel cells PE is selected when a gate pulse is applied to the gate lines GL to generate light corresponding to the gradation current signal supplied to the data line DL. Each of the pixel cells PE is equivalently represented by a diode Diode connected between the data line DL and the gate line GL.

As illustrated in FIG. 2, each of the pixel cells PE includes a first power line VDD, a pixel circuit 30 connected to a data line DL, and a gate line GL, and a pixel circuit 30. And a light emitting device OLED connected between the second power line GND. The description of each pixel cell PE will be replaced with the description of FIG. 2.

Meanwhile, in each of the pixel cells PE shown in FIG. 2, when the third and fourth TFTs T3 and T4 are turned off at the same time by the gate pulses, the gate pulses are not completely square waves, thereby being turned off. The output resistance of the third TFT T3 is increased while the drain voltage is increased to the voltage supplied to the first power line VDD in a short time. Accordingly, as the drain voltage of the third TFT T3 increases, the gate-source voltage Vgs of the first TFT T1 is dropped to change the amount of current flowing through the light emitting device OLED, thereby reducing the luminance.

In order to solve this problem, the gate electrodes of each of the third and fourth TFTs T3 and T4 are connected to different gate lines GL. In this case, the third and fourth TFTs T3 and T4 are turned on at the same time to different gate lines GL, and are applied to gate pulses for turning off at different times.

Accordingly, after the third and fourth TFTs T3 and T4 are turned on at the same time by the gate pulse, the third TFT T3 is turned off after the fourth TFT T4 is first turned off. Thus, by turning off the fourth TFT T4 before the third TFT T3, the fourth TFT T4 is brought into a high impedance state in advance so that the voltage of the first node n1 maintains the gradation current signal. . The fourth TFT T4 is first turned off and then the third TFT T3 is turned off so that the drain voltage of the third TFT T3 is increased to the voltage supplied to the first power line VDD. The driving is performed so as not to affect the voltage of the first node n1.

The timing controller 128 aligns the source data RGB from the outside with the data signal Data so as to be suitable for driving the image display unit 116 to the current type data driver 120 and the low gradation voltage supply driver 122. Supply.

The timing controller 128 generates gate control signals GCS for controlling the driving timing of the gate driver 118 and supplies the gate control signals GCS to the gate driver 118. In addition, the timing controller 128 generates a data control signal DCS for controlling the driving timing of the current type data driver 120 and supplies it to the current type data driver 120 and the low gray voltage supply driver 122. .

The gate driver 18 generates gate pulses for sequentially selecting the gate lines GL in response to the gate control signals GCS from the timing controller 28, and sequentially supplies the gate pulses to the gate lines GL. do.

The current type data driver 20 converts the data signal Data from the timing controller 28 into a gradation current signal in response to the data control signals DCS supplied from the timing controller 28 to convert the data lines DL. ) Is supplied to the pixel cell PE. That is, the current type data driver 20 generates a gradation current signal corresponding to the gradation value of the data signal Data and supplies it to the data lines DL.

The low gradation voltage supply driver 122 generates the low gradation voltage according to the data signal Data from the timing controller 128 and the low gradation voltage generated according to the data control signal DCS from the timing controller 128. Is supplied to the corresponding data line DL.

To this end, the low gradation voltage supply driver 122 may include a low gradation voltage generator 140 generating n different low gradation voltages as illustrated in FIG. 4, and a data signal from the timing controller 128. M select signals SS1 to 1 using the decoder 142 which selects and outputs any one of the n low gray voltages G0 to Gn according to the &lt; RTI ID = 0.0 &gt; A shift register 144 for sequentially outputting SSm, and an output unit 146 for supplying the low gray voltage from the decoder 142 to the data line DL according to the selection signals SS1 to SSm. .

The low gray voltage generator 140 generates n different low gray voltages G0 to Gn to the decoder 142 by using an input power Vin input from the outside. At this time, each of the n different low gray voltages G0 to Gn has a gray voltage corresponding to each of the 0 gray voltage to the n gray voltage of the data signal Data.

The decoder 142 decodes the data signal Data corresponding to each pixel PE from the timing controller 128, and the n low gray voltages G0 supplied from the low gray voltage generator 140 according to the decoding value. To Gn) is selected and supplied to the output unit 146. In this case, the decoder 142 selects one of the n low gray voltages G0 to Gn when the data signal Data corresponding to each pixel PE is low gray. In other words, when the gray level of the data signal Data is low, the decoder 142 selects one of the n low gray voltages G1 to G10 and supplies it to the output unit 146 through the output line 143. do. Here, it is assumed that the case where the data signal Data is 10 gradations or less is low gradation.

The shift register 144 sequentially shifts the source start pulse SSP according to the source shift clock SSC from the timing controller 128 to supply the m select signals SS1 to SSm to the output unit 146. .

The output unit 146 includes an output line 143 of the decoder 142 and m transistors M1 to Mm connected to the output terminals of each data line DL and the shift register 144.

The source electrode of each transistor M1 to Mm is electrically connected to the output line 143 of the decoder 142, and the drain electrode is electrically connected to the data line DL. The gate electrodes of the transistors M1 to Mm are electrically connected to the output terminals of the shift register 144.

Each of the transistors M1 to Mm receives the low gray voltages G0 to Gn supplied from the output line 143 of the decoder 142 in response to the selection signals SS1 to SSm from the shift register 144. The data line DL is supplied to the data line DL.

As such, when the data signal Data supplied from the timing controller 128 is low gray, the low gray voltage supply driver 122 may convert the low gray voltage corresponding to the gray level current signal corresponding to the data signal Data. By supplying to the supplied data line DL, the charging time of the pixel cell PE with respect to the low gradation data is accelerated.

Accordingly, the light emitting display device and the driving method thereof according to an exemplary embodiment of the present invention accelerate the charging time of the pixel cells PE with respect to the low grayscale data, thereby causing the charging time of the pixel cells PE when displaying the low grayscale data. The deterioration of image quality can be prevented.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention It will be apparent to those skilled in the art.

As described above, the light emitting display device and the driving method thereof according to the present invention provide a low gray level voltage by supplying a low gray level voltage to the data line simultaneously with the low gray level current signal when the gray level current signal supplied to the pixel cell is low gray level. It is possible to speed up the charging time of the pixel cell. Therefore, the present invention can prevent the deterioration of image quality due to the charging time of the pixel cell when displaying low grayscale data.

Claims (9)

An image display unit including pixel cells formed for each region defined by the gate lines and the data lines; A gate driver for driving the gate line; A current type data driver for generating a gradation current signal corresponding to the gradation value of the input data signal and supplying the gradation current signal to the data line; And a low gradation voltage supply driver for generating a low gradation voltage according to the gradation value of the data signal and supplying the generated low gradation voltage to the data line at the same time as the gradation current signal. The method of claim 1, And the low gray voltage supply driver supplies the low gray voltage to the data line when the gray level of the data signal is 10 grays or less. The method of claim 1, The low gray voltage supply driver, a low gray voltage generator for generating n low gray voltages (where n is a positive integer), A shift register for generating a shift signal, A decoder which decodes the data signal and selects one of the n low gray voltages and outputs the same through an output line; And an output unit for supplying a low gradation voltage from the decoder to the data line in response to the shift signal. The method of claim 3, wherein And the output part includes a plurality of transistors controlled by the shift signal and connected between an output line of the decoder and the data line. The method of claim 3, wherein And the n low gray voltages are voltages corresponding to 0 to n gray values of the data signal. A method of driving a light emitting display device having an image display unit including pixel cells formed in regions defined by gate lines and data lines; Supplying a gate pulse to the gate line; Generating a gradation current signal corresponding to a gradation value of an input data signal and supplying the gradation current signal to the data line in synchronization with the gate pulse; And generating a low gray voltage according to the gray value of the data signal, and supplying the generated low gray voltage to the data line simultaneously with the gray current signal. The method of claim 6, And the low gray voltage is supplied to the data line when the gray level of the data signal is 10 grays or less. The method of claim 6, The step of supplying the low gray voltage to the data line, generating n low gray voltages, where n is a positive integer, Generating a shift signal, Decoding the data signal and selecting and outputting any one of the n low gray voltages; And supplying the selected low gradation voltage to the data line in response to the shift signal. The method of claim 8, And the n low gray voltages are voltages corresponding to 0 to n gray values of the data signal.

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