KR20060092799A - Semiconductor device - Google Patents

Abstract

The present invention provides a channel region in a p-channel M0S transistor which improves the operation speed by applying compressive stress using a SiGe mixed crystal layer region epitaxially grown on a silicon substrate in a channel direction in the channel direction as a stress source. It is an object to further increase the applied stress to realize a new improvement in operating characteristics.

A compressive stress film is applied on the p-type SiGe mixed crystal layer region formed corresponding to the source / drain region of the p-channel M0S transistor, and the p-type SiGe mixed crystal layer region is compressed in a direction perpendicular to the channel direction on the silicon substrate surface to channel By expanding in the direction, the compressive stress applied directly under the channel region is enhanced.

Source / drain regions, MOS transistors, gate insulating films, source / drain extension regions, device isolation regions, compressive stress films, tensile stress films

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

BRIEF DESCRIPTION OF THE DRAWINGS The figure which shows the principle of the semiconductor device which uses a SiGe mixed crystal layer as a compressive stress source.

2 is a diagram showing the configuration of a semiconductor device using a conventional SiGe mixed crystal layer as a compressive stress source.

3 is a plan view showing a configuration of a p-channel MOS transistor according to an embodiment of the present invention.

4A and 4B are cross-sectional views showing the configuration of the p-channel MOS transistor of FIG.

FIG. 5C is another cross-sectional view illustrating a configuration of the p-channel MOS transistor of FIG. 3.

FIG. 6 is a diagram illustrating characteristics of a p-channel MOS transistor of FIG. 3.

7 is a view for explaining another feature of the p-channel MOS transistor of FIG.

8A to 8C illustrate a step of forming an element isolation structure in the p-channel MOS transistor of FIG. 3 (No. 1).

9 (d) to (e) are views for explaining the process of forming the element isolation structure in the p-channel MOS transistor of FIG. 3 (No. 2).

10 (f) to 10 (g) illustrate a step of forming an element isolation structure in the p-channel MOS transistor of FIG. 3 (No. 3).

11 (h) to (i) are diagrams illustrating a step of forming an element isolation structure in the p-channel MOS transistor of FIG. 3 (No. 4).

FIG. 12 is a diagram showing the configuration of an n-channel MOS transistor integrated on the same silicon substrate together with the p-channel MOS transistor of FIG.

* Description of the symbols for the main parts of the drawings *

1, 11: silicon substrate

1A, 1B: SiGe mixed crystal layer region

1a, 1b, 10c, 10d, 21c, 21d: source / drain regions

2, 12: gate insulating film

3, 13, 23: gate electrode

4, 13S, 21SC: silicide layer

10: p-channel MOS transistor

10A, 10B: device region

10a, 10b, 21a, 21b: source / drain extension area

10CH: channel area

10I: device isolation region

11CVD: CVD oxide film

11OX ₁ , 11OX ₂ : thermal oxide film

11SN ₁ , 11SN ₂ : SiN film

11T: SiN tensile film

11T ₁ : first device isolation groove

11T ₂ : second device isolation groove

11TA, 11TB: Trench

11i: thermal oxide film

11SGS: NiSiGe film

14: compressive stress film

15: tensile stress film

20: n-channel MOS transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices having improved operating speed by applying stress and a method of manufacturing the same.

Advances in miniaturization technology make it possible to achieve ultrafine and ultrafast semiconductor devices having a gate length of 100 nm or less.

In such ultrafine and ultrafast transistors, the area of the channel region immediately below the gate electrode is very small compared to that of a conventional semiconductor device. Therefore, the mobility of electrons or holes traveling through the channel region is caused by the stress applied to the channel region. It is greatly affected. Thus, many attempts have been made to optimize the stress applied to such channel regions to improve the operating speed of semiconductor devices.

In general, in a semiconductor device having a silicon substrate as a channel, the mobility of holes is smaller than that of electrons. Therefore, it is desirable to improve the operation speed of a p-channel MOS transistor having holes as carriers in the design of semiconductor integrated circuit devices. It is becoming an important task.

In such a p-channel MOS transistor, it is known that the carrier mobility is improved by applying a uniaxial compressive stress to the channel region, and a schematic configuration shown in FIG. 1 has been proposed as a means for applying a compressive stress to the channel region.

Referring to FIG. 1, a gate electrode 3 corresponding to a channel region is formed on a silicon substrate 1 through a gate insulating film 2, and channels are formed on both sides of the gate electrode 3 in the silicon substrate 1. The p-type diffusion regions 1a and 1b are formed to define the region. In addition, sidewall insulating films 3A and 3B are formed on sidewalls of the gate electrode 3 so as to cover a part of the surface of the silicon substrate 1.

The diffusion regions 1a and 1b respectively act as source and drain extension regions of the M0S transistor, and the diffusion regions 1a and 1b each have a hole transported from the diffusion region 1a to the diffusion region 1b in the channel region immediately below the gate electrode 3. The flow is controlled by the gate voltage applied to the gate electrode 3.

In the configuration of FIG. 1, SiGe mixed crystal layers 1A and 1B are formed epitaxially with respect to the silicon substrate 1 on the outer side of the sidewall insulating films 3A and 3B in the silicon substrate 1. In the SiGe mixed crystal layers 1A and 1B, p-type source and drain regions continuous to the diffusion regions 1a and 1b are formed, respectively.

In the MOS transistor of FIG. 1, since the SiGe mixed crystal layers 1A and 1B have a larger lattice constant with respect to the silicon substrate 1, the compressive stress indicated by the arrow a in the SiGe mixed crystal layers 1A and 1B As a result, the SiGe mixed crystal layers 1A and 1B are deformed in a direction substantially perpendicular to the surface of the silicon substrate 1 indicated by the arrow b.

Since the SiGe mixed crystal layers 1A and 1B are formed epitaxially with respect to the silicon substrate 1, the deformation in the SiGe mixed crystal layers 1A and 1B indicated by the arrow b indicates a corresponding deformation in the silicon substrate. Although it is induced to appear as an arrow c in the channel region, a uniaxial compressive stress is induced to appear as an arrow d in the channel region according to this deformation.

In the M0S transistor of FIG. 1, the uniaxial compressive stress is applied to the channel region, and as a result, the symmetry of the Si crystals constituting the channel region is locally modulated, and the valence band and light weight of the heavy hole are changed according to the change of the symmetry. Since the degeneracy of the valence band of the hole is released, the hole mobility in the channel region is increased, and the operation speed of the transistor is improved. The increase in the hole mobility due to the stress locally induced in such channel regions and the improvement in the transistor operating speed are remarkable especially in ultrafine semiconductor devices having a gate length of 100 nm or less.

FIG. 2 is a diagram showing the configuration of a MOS transistor based on this principle described in Non-Patent Document 1. FIG. However, the same reference numerals are given to the above-described parts of the drawings, and description thereof will be omitted.

Referring to FIG. 2, the SiGe mixed crystal layers 1A and 1B are epitaxially filled to fill respective trenches formed in the silicon substrate 1, and the silicon insulating film 1 and the gate insulating film 2 shown by dotted lines in the figure are epitaxially filled. The side regions 1As and 1Bs, which are regrown to a level L higher than the interface, and which define the SiGe mixed crystal layers 1A and 1B and face each other, have a gap between the SiGe mixed crystal layers 1A and 1B. It is formed in a curved shape such that the inside of the silicon substrate 1 is continuously increased downward from the bottom surface of the insulating film 2.

In addition, in the conventional structure of FIG. 2, the silicide layer 4 is formed directly on the SiGe mixed crystal layers 1A and 1B grown up to the level L above. Similarly, the silicide layer 4 is also formed on the polysilicon gate electrode 3.

[Patent Document 1] US Patent No. 6621131.

[Patent Document 2] Japanese Unexamined Patent Publication No. 2004-31753.

[Patent Document 3] Japanese Unexamined Patent Application Publication No. 8-167718.

[Patent Document 4] Japanese Unexamined Patent Publication No. 2003-179157.

[Non-Patent Document 1] Thompson, S. E., et a1., IEEE Transactions on E1ectron

               Devices, Vo1.51, No. 11, November, 2004, pp. 1179-1797.

An object of the present invention is to provide a configuration in which a p-channel MOS transistor in which stress is applied to a channel region in this way can further increase stress in the channel region.

According to a first aspect of the present invention, an element region is defined by an element isolation region, and is formed through a silicon substrate including a channel region in the element region, and a gate insulating film corresponding to the channel region on the silicon substrate. A source electrode comprising a gate electrode each supporting a sidewall insulating film on a pair of opposing sidewall surfaces, and a p-type diffusion region formed by sandwiching the channel regions on both sides of the gate electrode of the silicon substrate, respectively. A source region and a drain region comprising an extension region and a drain extension region, a p-type diffusion region formed successively in the source extension and drain extension regions on the outer side of the pair of sidewall insulating films, among the silicon substrates, and the silicon substrate. In the middle, the source and drain regions outside the pair of sidewall insulating films In order to be enclosed, it consists of a pair of SiGe mixed crystal region epitaxially formed with respect to the said silicon substrate, and each of the said pair of SiGe mixed crystal region has a level higher than the gate insulating film interface of the said gate insulating film and a silicon substrate. There is provided a semiconductor device, wherein a compressive stress film is formed on an upper surface of the pair of SiGe mixed crystal layer regions.

3 is a plan view showing the overall configuration of the p-channel MOS transistor 10 according to an embodiment of the present invention, Figures 4 (a), (b) are each A-A 'of the p-channel MOS transistor 10. A cross-sectional view taken along line B-B ', and FIG. 5 (c) shows a cross-sectional view taken along line C-C' of the p-channel MOS transistor 10. FIG.

As shown in Figs. 3 and 4 (a), (b) and 5 (c), the p-channel MOS transistor 10 is an n-type device defined by an STI type device isolation structure 10I. It is formed on the silicon substrate 11 having the region 10A, and the device region 10A includes the channel region 10CH of the p-channel MOS transistor 10. The element region 10A protrudes upward from the element isolation region 10I surrounding it, forming a mesa structure M surrounded by a thick line in FIG.

The device isolation structure 10I includes a device isolation groove 11T formed in the silicon substrate 11 and a thermal oxidation liner film 11i formed on the surface of the device isolation groove 11T. The cavity inside the film 11i is filled by the CVD oxide film 11CVD through the SiN liner film 11N having tensile stress. Features of the device isolation structure 10I of the present invention will be described in detail in the following examples.

In particular, referring to FIG. 5C, a p + type polysilicon gate electrode 13 is formed on the channel region 10CH through a gate insulating film 12 which is typically made of a SiON film having a thickness of about 1.2 nm. Further, in the silicon substrate 11, p-type source extension regions 10a and p-type drain extension regions 100b are formed on both sides of the polysilicon gate electrode 13 in the channel direction. .

The sidewall surface of the polysilicon gate electrode 13 is covered by CVD oxide films 13A and 13B, respectively, typically 10 nm thick, and the CVD oxide films 13A and 13B are also exposed in the device region 10A. The surface of the silicon substrate 11 is continuously covered. Further, SiN sidewall insulating films 13C and 13D are formed outside the CVD oxide films 13A and 13B, respectively. In the silicon substrate 11, p + source regions 10c and p + drain regions 10d are formed corresponding to the outer ends of the SiN side wall insulating films 13C and 13D.

Of the mesa structures M constituting the device region 10A, the outer ends of the SiN sidewall insulating films 13C and 13D are further formed by the etching process combining dry etching and wet etching, so that the source region 10c and the drain region. The trenches 11TA and 11TB, which are removed in a range not exceeding 10d and are defined by a plurality of Si crystal surfaces, are formed. In addition, the p-type SiGe mixed crystal layer regions 11SGA and 11SGB, each containing Ge at a concentration of 20% or more, to fill the trenches 11TA and 11TB, respectively, are part of the source and drain regions 10c and 10d. As an example, the silicon substrate 11 is formed epitaxially. Such SiGe mixed crystal layer epitaxial regions 11SGA and 11SGB have a substrate temperature of 400 to 550 ° C., for example, by a reduced pressure CVD method using SiH ₄ and GeH ₄ gas as a gaseous raw material, and the SiH ₄ gas being It can be formed by supplying a GeH ₄ gas at a partial pressure of 1 to 10 Pa, at a partial pressure of 0.1 to 10 Pa, and with a HCl gas at a partial pressure of 1 to 10 Pa to a processing vessel.

In the examples of FIGS. 4A, 4B, and 5C, the SiGe mixed crystal layer regions 11SGA and 11SGB are at least 20 upwards from an interface between the silicon substrate 11 and the gate insulating layer 12. Nm is formed to protrude. In addition, the SiGe mixed crystal layer regions 11SGA and 11SGB formed in this way are defined as crystal surfaces, and in particular, the sidewall surfaces on the side facing the gate electrode 13 are oriented so that the distance from the gate electrode sidewall surfaces increases upward. The slope is defined by, for example, the Si (111) plane. In addition, the side wall surface on the side opposite to the inclined side wall surface is formed in contact with the element isolation structure 10I, and constitutes the side wall surface of the mesa structure M. Such p-type SiGe mixed crystal layer regions 11SGA and 11SGB may be formed by ion implantation of p-type impurity elements after epitaxial growth, but at the time of epitaxial growth, p-type impurity element gas such as diborane is used as the dopant gas. It is preferable to add. In addition, the p + type source and drain regions 11c and 11d are formed by ion implantation immediately after the trenches 11TA and 11TB are formed before the formation of the SiGe mixed crystal layer regions 11SGA and 11SGB. The p-type SiGe mixed crystal layers 11SGA and 11SGB having small band gaps can suppress the generation of the junction leakage current at the pn junction interface without directly contacting the device region 10A made of n-type Si crystals. .

In addition, a nickel silicide film 13S is formed on the top surface of the gate electrode 13 by a salicide process using a metal Ni film, and nickel germanium silicide (NiGeSi) is formed on the p-type SiGe mixed crystal layers 11SGA and 11SGB. The film 11SGS is also formed by a salicide process using a metal Ni film.

In this embodiment, as shown in Figs. 4 (a), (b) and 5 (c), the compressive stress film 14, which tends to shrink, covers the entirety of the p-channel MOS transistor, Formed.

By forming such a compressive stress film 14, in particular, as shown in the cross section of FIG. 4 (b), the SiGe mixed crystal layer regions 11SGA and 11SGB that form part of the p + type source and drain regions are formed in the channel region. On both sides, as indicated by arrow e in FIG. 4 (b), the compressive stress acts in a direction orthogonal to the channel direction in the plane of the silicon substrate, but as a result, the SiGe mixed crystal layer region 11SGA, 11 SGB) deforms and expands in the channel direction. At this time, as can be seen in the cross section of Fig. 5 (c), since the outer ends of the SiGe mixed crystal layer regions 11SGA and 11SGB are substantially pinned by the device isolation structure 10I, such SiGe mixed crystal layer regions 11SGA. , 11 SGB) generates a compressive stress in the channel region 10CH that further enhances the compressive stress d described above with reference to FIG. 1.

The compressive stress film 14 is preferable that the accumulated stresses 1.5GPa or more in absolute value, for example, has a thickness of 80㎚, a substrate temperature of 400 ℃ SiN film, under the pressure of 250Pa, SiH _4, and It can be formed by supplying NH ₃ at a flow rate of 600 SCCM and 1400 SCCM, respectively, as a gaseous raw material.

On the other hand, with reference to FIG. 4B again, such a compressive stress film 14 is formed on a surface substantially upright with respect to the substrate surface, such as, for example, sidewall surfaces of the SiGe mixed crystal layer regions 11SGA and 11SGB. In this case, the SiGe mixed crystal layer regions 11SGA and 11SGB are pressed down onto the silicon substrate 11. In this case, the upward expansion of the SiGe mixed crystal layer regions 11SGA and 11SGB, which causes the compressive stress in the channel region described above with reference to FIG. As a result, the magnitude of the horizontal compressive stress d applied to the channel region in the channel direction decreases.

Thus, in the present embodiment, on the surface almost upright with respect to such a substrate surface, it locally forms a tensile stress film 15 which is intended to expand, and compressive stress of the compressive stress film 14 acting on this surface. Cancel at least partially. Such a tensile stress film 15 is formed outside the sidewall insulating films 13A and 13B also on the sidewall surface of the gate electrode 13. Accordingly, in the gate, the electrode 13 compresses the channel region 10CH from the upper side by the compressive stress of the compressive stress film 14, thereby reducing the magnitude of the compressive stress d acting in the horizontal direction of FIG. The problem of reducing is avoided.

The tensile stress film 15 is preferably 1GPa or more accumulated stress in absolute value, and, for example, a film of SiN having a thickness 100㎚ a substrate temperature of 3 × 10 ⁴ Pa under pressure, of 500 ℃, SiH ₄ And NH ₃ can be formed as a gaseous raw material at a flow rate of 20 SCCM and 7000 SCCM, respectively, and subsequently etched back.

According to the configuration of the present embodiment, a compressive stress of up to 0.9 GPa is induced in the channel region in the channel region 10CH, so that the saturation current per gate width of the p-channel MOS transistor is obtained by the compression film 14 and the tension. It was confirmed that the film 15 was increased from 600 mV / m to 640 mV / m when no film 15 was provided.

On the other hand, when the film thickness of the tensile stress film 15 is increased beyond 80 nm, the drain-off current increases as shown in FIG. 6, the tensile stress film 15 is formed by using a SiN film having a gate length of 40 nm, a gate width of 500 nm, and a thickness of 50 nm in which a compressive stress of 1.0 GPa is accumulated as the compressive stress film 14. Fig. 3 shows the relationship between the drain-off current and the drain saturation current in the case where the SiN film having a tensile stress of 1.5 GPa is accumulated as the film thickness of the tensile stress film 15 is varied. From this, it is concluded that the film thickness of the tensile stress film 15 is preferably limited to 80 nm or less.

7 is another diagram for explaining the configuration of the p-channel MOS transistor 10. However, FIG. 7 corresponds to the cross section of FIG. 4 (b). In addition, "0rigina1 Si surface 1eve1" shows the interface A of the silicon substrate 11 and the gate insulating film 12 in FIG.5 (c).

Referring to FIG. 7, the SiGe mixed crystal layer regions 11SGA and 11SGB constituting part of the mesa M of FIG. 3 have a level B lower than the interface A by a depth D _SiGe according to the formation of the trenches 11TA and 11TB. Start to grow and grow beyond the interface A to a height U. At this time, in order to apply a compressive stress d of sufficient magnitude to the channel region 10CH by the mechanism described in FIG. 1, the height U is preferably more than 20 nm. Further, in the present embodiment, the device isolation structure 10I is formed at a position below the interface A by a depth D _{STI_1} , but the height of the CVD oxide film 11CVD in the device isolation structure 10I is the level B. It is preferable that the depth D _{STI_1} is formed to satisfy the relationship, D _SiGe < D _{STI_1} so as not to exceed. By setting the positional relationship in this way, when a Ni metal film is deposited on the SiGe mixed crystal layer regions 11SGA and 11SGB for formation of the silicide film 11SGS, and heat-treated, the Ni atoms in the Ni metal film form the SiGe mixed crystal. The problem of diffusing into the layer regions 11SGA and 11SGB, deeply penetrating into the thermal oxide film 11i constituting the element isolation structure 10I, and deteriorating the element isolation characteristics is avoided.

In addition, as shown in the cross-sectional view of Fig. 4A, in the present embodiment, the upper portion of the SiN film 11N constituting the device isolation structure 10I is shown in the left and right sides of the channel region 10CH. Care should be taken to increase the film thickness, such as in the enclosed area.

Referring to Fig. 4A, in the cross-sectional view of Fig. 4A, compressive stress is applied in the SiGe mixed crystal layer regions 11SGA and 11SGB located above and below the ground in the direction perpendicular to the ground. In order to efficiently increase the hole mobility in the channel region 10CH due to stress, it is necessary that the Si crystals deform efficiently from the ground to the left and right in the channel region 10CH.

In contrast, in the element isolation structure 10I arranged on the left and right sides of the channel region 10CH, the CVD oxide film 11CVD formed by the high density plasma CVD method generally accumulates compressive stress, and as a result, the channel region 10CH is subjected to compressive stress against the preferred deformation by the element isolation structure 10I from the left and right. The compressive stress due to such CVD oxide film 11CVD can be canceled to some extent by accumulating the tensile stress opposite to the SiN film 11N formed in the device isolation structure 10I. By increasing the film thickness of the SiN film 11N on both sides of the region 10CH, the effect of the compressive stress caused by such CVD oxide film 11CVD is suppressed.

8 (a) to 11 (i) show a manufacturing process of the p-channel MOS transistor 10 according to the present embodiment including the process of forming such an element isolation structure 10I. 8 (a) to 9 (e), FIG. 10 (f) and FIG. 11 (h) show the AA 'cross section of FIG. 3, and FIG. 10 (g) and FIG. 11 (i) show the BB of FIG. 'Represents the cross section.

Referring to FIG. 8A, in the silicon substrate 11, a first shallow element isolation groove 11T ₁ is formed through the thermal oxide film 11OX ₁ to correspond to the formation region of the element isolation region 10I. film to the (11SN ₁₎ as a mask, the first is formed by dry etching, and after removing the SiN film (11SN ₁₎ and the thermal oxide film (11OX ₁₎ in the process of Fig. 8 (b), a new thermal oxide film ( 11OX ₂₎ and, by etching back after the formation of the SiN film (11SN _2), the opening (11T _O) in the element isolation grooves (11T ₁₎ to form a self-aligning manner.

In the process of FIG. 8C, the silicon substrate 11 is dry-etched with the SiN film 11SN ₂ as a mask in the opening 11T _O to form the first device isolation groove 11T ₁ . In order to extend into the silicon substrate 11, a second device isolation groove 11T ₂ is formed. The first and second device isolation grooves 11T ₁ and 11T ₂ form a front device isolation groove 11T.

In the process of Fig. 8C, a thermal oxide film 11i and a CVD SiN film 11N are formed on the surface of the device isolation groove 11T, and are formed on the SiN film 11N by high density plasma CVD. CVD oxide film 11CVD is deposited. In addition, the CVD oxide film 11CVD is patterned to leave the CVD oxide film 11CVD in the device isolation groove 11T and to be removed from the surface of the silicon substrate 11.

In the process of Fig. 9 (d), the SiN film 11N and the thermal oxide film 11OX ₂ are removed by the CMP method so that the CVD oxide film 11CVD is flat and the newly exposed silicon substrate ( A high quality SiON gate insulating film 12 is formed on the surface of 11).

In the process of FIG. 9E, a polysilicon film is deposited on the gate insulating film 12 and patterned to form the polysilicon gate electrode 13.

In the process shown in Fig. 10 (f), sidewall insulating films 13A and 13B (not shown) made of CVD oxide films and sidewall insulating films 13C and 13D made of CVD SiN films are formed on the sidewall surfaces of the polysilicon gate electrodes 13. ) Is formed by a film forming and an etch back process. It can be seen that a recess is formed on the surface of the CVD oxide film 11CVD according to the formation process of the sidewall insulating film.

In the process of Fig. 10G, the trenches 11TA and 11TB are formed by an etching process in which dry etching and wet etching are combined in the formation portions of the source and drain regions 10c and 10d. As a result, the level of the silicon substrate surface is lowered from level A to level B of FIG. In addition, after the source and drain regions 10c and 10d are formed by ion implantation, the SiGe epitaxial layer 1111 SGA and 11SGB is thus grown by growing the SiGe epitaxial layer under the same conditions as described above. It is epitaxially grown in the formed trenches 11TA and 11TB.

In addition, in the processes of FIGS. 11 (h) and 11 (i) which are performed simultaneously, a Ni metal film is deposited on the polysilicon gate electrode 13 and the SiGe mixed crystal layer regions 11SGA and 11SGB, and this is underneath. By reacting with polysilicon or SiGe mixed crystals, a silicide film 13S is formed on the polysilicon gate electrode 13, and a NiGeSi layer 11SGS is formed on the SiGe mixed crystal layer regions 11SGA and 11SGB.

In the p-channel MOS transistor formed in this manner, as can be seen from FIG. 11 (h), in the element isolation structure 10I formed on the left and right sides of the channel region 10CH, the film thickness of the SiN film 11N that accumulates tensile stress. In addition, in the portion adjacent to the channel region 10CH, the compressive stress applied to the channel region 10CH by the CVD oxide film 11CVD is reduced.

12 shows the configuration of an n-channel MOS transistor 20 formed on the same silicon substrate 11 as the p-channel MOS transistor of FIGS. 4 (a) to 5 (c).

Referring to FIG. 12, the n-channel MOS transistor 20 is formed in the p-type device region 10B defined by the device isolation structure 10I on the silicon substrate 11. (11) a SiON gate insulating film 22, such as the SiON gate insulating film 12 formed corresponding to the channel region in the element region 10B, and an n + type poly silicon gate electrode formed on the gate insulating film 22 ( 23, an n-type source extension region 21a and an n-type drain extension region 21b are formed on both sides of the channel region in the device region 10B.

The polysilicon gate electrode 23 has both sidewall surfaces covered by the same CVD oxide films 23A and 23B as those of the CVD oxide films 13A and 13B, and on the outside thereof, the SiN sidewall insulating films 13C and 13D. SiN side wall insulating films 23C and 23D are formed, respectively.

In the silicon substrate 11, an n + type source region 21c and an n + type drain region 21d are formed outside the SiN sidewall insulating films 23C and 23D in the device region 10B. The silicide film 21SC is formed in the surface of the region 21c and the drain region 21d by the salicide process. The silicide film 21SC is also formed on the polysilicon gate electrode 23.

In the n-channel MOS transistor 20 of Fig. 12, a tensile stress film 15 used in the p-channel MOS transistor 10 of Figs. 4 (a) to 5 (c) is formed on the entire surface. As a result, biaxial tensile stress is applied to the channel region immediately below the gate electrode. Accordingly, the operating speed of the n-channel MOS transistor is improved as compared with the case where such stress is not applied.

Therefore, when fabricating a semiconductor integrated circuit device having the p-channel MOS transistor 10 of Figs. 4 (a) to 5 (c) and the n-channel MOS transistor 20 of Fig. 12 on a common silicon substrate, After forming the device structure on the device regions 10A and 10B, the tensile stress film 15 is uniformly deposited on the silicon substrate 11, and the formation region of the n-channel MOS transistor 20 is formed. Is covered with a resist mask to perform an etch back process, thereby leaving the tensile stress film 15 in the n-channel MOS transistor region, and selectively on a surface substantially perpendicular to the substrate surface in the p-channel MOS transistor region. Leave

Further, on this structure, the compressive stress film 14 is uniformly deposited at this time, and also removed from the n-channel MOS transistor region, thereby leaving the compressive stress film 14 only on the p-channel MOS transistor 10. .

By such a process, a semiconductor integrated circuit device having a p-channel MOS transistor and an n-channel MOS transistor on a common substrate, and in which both transistors increase their operation speed by applying stresses, does not complicate the manufacturing process. You can get it.

As mentioned above, although preferred embodiment of this invention was described, this invention is not limited to this specific embodiment, A various deformation | transformation and a change are possible within the summary described in a claim.

According to the present invention, a channel for connecting the source region and the drain region in a plane in which the SiGe mixed crystal layer region is parallel to the silicon substrate by forming a compressive stress film on each upper surface of the pair of SiGe mixed crystal layer regions. Direction, and as a result, the pair of SiGe mixed crystal layer regions respectively expand in the channel direction, thereby compressing the channel region in the channel direction. Accordingly, the compressive stress applied to the channel region by the mechanism described in FIG. 1 is further enhanced by the SiGe mixed crystal layer region, thereby further improving hole mobility in the channel region. At this time, in the present invention, since the device isolation structure is formed on the outer side of the SiGe mixed crystal layer region on the channel direction, the expansion of the device separated from the outside of the SiGe mixed crystal layer region, that is, the opposite side to the channel direction. Substantially impeded by the structure, expansion of the pair of SiGe mixed crystal layers occurs mainly in the direction of compressing the channel region. In addition, when such a compressive stress film is formed on the sidewall surface of the SiGe mixed crystal layer region, the SiGe mixed crystal layer region is also compressed in the vertical direction as the compressed film shrinks, so that the upper and lower portions of the channel region indicated by the arrow c in FIG. Direction deformation is inhibited, and the magnitude of the compressive stress indicated by the arrow d in FIG. 1 as a result decreases. Therefore, in the present invention, a tensile stress film is formed on the sidewall surface of the SiGe mixed crystal layer region, and the compressive stress in the vertical direction acting on the SiGe mixed crystal layer region is reduced. Further, by forming the same tensile stress film on the sidewall surface of the gate electrode, the gate electrode is pressed from the upper side to the channel region by the action of the compressive stress film, and as a result, the compressive stress formed to act in the vertical direction on the channel region is reduced. .

In addition, according to the present invention, in the element isolation structure arranged on the left and right sides of the channel region, the thickness of the tensile stress film formed along the element isolation groove is increased in a portion adjacent to the channel region, thereby increasing the thickness of the channel region. The pair of SiGe mixed regions formed at both ends of the channel direction of the channel region can be reduced by the element isolation insulating film filling the device isolation grooves of the channel region from the side with respect to the channel direction. From this, the lateral expansion of the channel region is promoted by the compressive stress acting in the channel direction. As a result, the improvement effect of the hole mobility by the compressive stress d described above in FIG. 1 is further enhanced.

Claims (10)

A silicon substrate including a channel region in the element region by defining an element region by an element isolation region; A gate electrode formed on the silicon substrate through a gate insulating film corresponding to the channel region, and supporting the sidewall insulating film on a pair of opposite sidewall surfaces, respectively; A source extension region and a drain extension region comprising p-type diffusion regions formed by sandwiching the channel regions on both sides of the gate electrode of the silicon substrate; A source region and a drain region formed of a p-type diffusion region formed continuously in the source extension region and the drain extension region, respectively, on the outer side of the pair of sidewall insulating films of the silicon substrate; A pair of SiGe mixed crystal regions epitaxially formed with respect to the silicon substrate so as to be surrounded by the source and drain regions outside the pair of sidewall insulating films of the silicon substrate, Each of the pair of SiGe mixed crystal layer regions is grown to a level higher than the gate insulating film interface between the gate insulating film and the silicon substrate, And a compressive stress film is formed on an upper surface of the pair of SiGe mixed crystal layer regions. The method of claim 1, Each of the pair of SiGe mixed crystal layer regions is grown to a position 20 nm or more higher than the gate insulating film interface. The method according to claim 1 or 2, Each of the SiGe mixed crystal layer regions has a tensile stress film on the sidewall surface. The method according to claim 1 or 2, The tensile stress film has a film thickness of 80 nm or less. The method according to claim 1 or 2, The tensile stress film accumulates a tensile stress of 1 GPa or more. The method according to claim 1 or 2, The compressive stress film accumulates a compressive stress of 1.5 GPa or more. The method according to claim 1 or 2, And the pair of SiGe mixed crystal layer regions is formed such that the lower end thereof is positioned above the upper end of the element isolation insulating film constituting the element isolation region in the cross-sectional view including the source region and the drain region. The method according to claim 1 or 2, The device isolation region is formed of an STI type device isolation structure including a device isolation groove formed in the silicon substrate and a device isolation insulating film filling the device isolation groove, and a tensile stress accumulated on the inner surface of the device isolation groove. An insulating film is formed, and said tensile insulating film has a film thickness larger than the other area | region on both sides of the said channel area | region. The method according to claim 1 or 2, And the compressive stress film comprises nitrogen and oxygen. The method according to claim 1 or 2, An n-channel M0S transistor is further formed on the silicon substrate, and the n-channel M0S transistor is entirely covered by a tensile stress film.

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