KR20060083848A - Method for cbr data transmission in obs network - Google Patents

Abstract

The present invention proposes a method of matching a bit rate of data input to an optical burst switching network with a bit rate of output data. To this end, the entry edge node constituting the optical burst switching network calculates and transmits information about the number of clocks per unit time of data having a fixed bit rate and the clock frequency per unit time, which is its own frequency. In addition, the core node calculates the difference between the number of clocks per unit time, which is a natural frequency of the received data, and the number of clocks per unit time, which is its own frequency, and includes the same in the control information. The advancing edge node calculates the clock number of the unit time at the time when the optical data flows into the optical burst switching network from the received control information, and restores and outputs the frequency of the received optical data to the original frequency. In this way, the optical data output from the optical burst switching network may have the same frequency as the frequency at which it is introduced.

OBS, CBR, Clock, Phase Information

Description

Fixed bit rate data transmission method in optical burst switching network {Method for CBR data transmission in OBS network}

1 is a diagram showing the structure of a typical optical burst switching network;

2 is a diagram illustrating a process of transmitting fixed bit rate data in a conventional optical burst switching network;

3 illustrates a process of transmitting fixed bit rate data in an optical burst switching network according to an embodiment of the present invention;

4 is a diagram illustrating a configuration of a core node according to an embodiment of the present invention;

5 is a diagram illustrating a configuration for acquiring a clock of an entry edge node at an entry edge node according to an embodiment of the present invention;

6 is a diagram illustrating a configuration of an entry edge node according to an embodiment of the present invention;

FIG. 7 is a diagram illustrating a configuration for acquiring a clock of CBR data input from an entry edge node to an entry edge node according to an embodiment of the present invention; and

8 is a diagram illustrating a configuration of an advance edge node according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical burst switching (OBS) network, and more particularly, to a method for matching a transmission rate of burst data input to an optical burst switching network and an output burst data.

In general, when transmitting and receiving optical signals through an optical fiber (link), an electrical switch was used. However, the electrical switch must perform a process of converting the optical signal into an electrical signal and a process of converting the electrical signal into an optical signal in order to process the received optical signal. This necessitates an additional need for the photoelectric converter for converting the optical signal into the electrical signal and the all-optical converter for converting the electrical signal into the optical signal. Occurred.

In order to solve such a problem, an optical burst switch capable of directly processing a received optical signal without converting it into an electrical signal has been proposed. Hereinafter, an optical burst switching network using an optical burst switch will be described.

In general, in an optical burst switching network, IP packets entering the optical domain are gathered from the edge node into burst data, and these burst data are collected by the core node (depending on their destination or quality of service). It is routed through the Core Node and sent to the destination node. In addition, burst control packets (BCP) and burst data (BD) are separately transmitted by offset time using different channels. That is, the BCP is transmitted in advance of the burst data by the offset time so that the burst data can be reserved in advance so that the burst data can be quickly transmitted through the optical network without buffering. Hereinafter, a process of transmitting optical data will be described with reference to FIG. 1.

1 illustrates nodes that transmit or receive burst data in an optical burst switching network. Hereinafter, a process of transmitting burst data in an optical burst switching network will be described.

Node A 100 generates burst data by collecting IP packets when IP packets are input as edge nodes. The edge nodes 100, 106 and 108 collect IP packets to form and transmit optical burst data packets or receive optical burst data packets and split them into IP packets. Core nodes 102 and 104 serve to optically switch burst data. When the burst data having a desired size is generated, the node A 100 generates a burst control packet (BCP) and transmits it to the node B 102, which is a core node, and transmits the burst data to the node B 102 after an offset time. . The BCP contains information on the destination address, source address, burst data size, QoS, offset time, and the like of the burst data.

The node B 102 uses the received BCP to check a destination address of the burst data to be received later, determine a light path, and reserve a time for light switching. In node B 102, the burst control packet is photoelectric / optical conversion, but the burst data follows the optical path only by optical switching without photoelectric conversion. Node B 102 optically switches burst data to Node D 106 or Node C 104 depending on whether the destination of burst data sent from Node A 100 is Node D 106 or Node E 108. can do.

Node B 102 has been described the process of delivering the burst data transmitted from Node A (100) to Node D (106) or Node E (108). However, Node B 102 may be the destination of burst data generated from Node A 100 or may directly generate burst data for delivery to Node D 106 or Node E 108. That is, NodeB 102, which is a core node, may have the function of an edge node.

However, in case of the node B, the burst data received from the node A and the burst data received from the node C are nodes D. In this case, since the node B cannot transfer the received burst data to the node D at one time, the node B selects one burst data and transmits the selected burst data first. In addition, the burst data that is not selected may be transmitted after delaying a predetermined time, thereby preventing the burst data from being lost.

Data input to the optical burst switching network can be classified into two types. The data is classified into data having a constant bit rate (CBR) such as voice data and data having a variable bit rate (VBR) such as packet data. Data having a fixed bit rate should be received at the receiving end at the same bit rate as the data rate transmitted from the transmitting end.

2 shows the bit rate of data input to an optical burst switching network. According to FIG. 2, the optical burst switching network includes an ingress node node A, an egress node node D, and core nodes node B and node C, which is a type of edge node. The nodes that make up the optical burst switching network have their own frequency (the number of clocks per unit time). According to FIG. 2, the natural frequency of node A is f _a , the natural frequency of node B is f _b , the natural frequency of node C is f _c , and the natural frequency of node D is f _d . Since phase is an integrated concept of frequency, phase, frequency, and the number of clocks per unit time are used in the same sense.

According to FIG. 2, the phase of data output from node A, the phase of data output from node C, the phase of data input to a demapper (not shown) constituting node D, and the data output from node D It can be seen that the phases of are different from each other. As described above, data having a fixed bit rate should transmit data at a constant transmission rate. However, the bit rate of the data input to the optical burst switching network and the output bit rate are different from each other. This problem is due not only to the difference in natural frequencies of each node, but also to the characteristics of the optical burst switching network. That is, the optical burst switching network does not transmit the circuit data but transmits the data in burst units composed of a plurality of packets. Therefore, the first packet data received must wait (delay) until other packet data is received. In addition, when there is no link to transmit burst data transferred to the core node, the burst data waits for a predetermined time in the core node until a link to be transmitted is created. As such, the data delivered to the optical burst switching network is delayed for various reasons, which makes it impossible to guarantee a fixed bit rate. Therefore, there is a need for a method that can match the bit rate of the data input to the optical burst switching network and the output bit rate.

An object of the present invention for solving the above problems is to propose a method of matching the bit rate of the data input to the optical burst switching network and the bit rate of the output data.

Another object of the present invention for solving the above problems is to propose a method for efficiently transmitting the data desired by the user by matching the bit rate of the data input to the optical burst switching network and the output data.

Therefore, in the core node for transmitting the optical data received from the entry edge node or the core node to the entry edge node or core node to achieve the objects of the present invention, in the method for transmitting the control information of the optical data, the transfer to the input link Calculating a difference between the number of clocks per unit time of optical data and the number of clocks per unit time of its natural frequency; And transmitting the calculated difference in the control information to transmit the control information in the optical burst switching network.

A calculation unit for calculating a difference between the number of clocks per unit time of optical data transmitted to an input link and the number of clocks per unit time of its own frequency in order to achieve the objects of the present invention; And a controller for adding and outputting a difference received from the calculator and a difference included in the control information transmitted to the input link.

A data processor for reading and processing data having a fixed bit rate stored according to a clock of the node itself to achieve the objects of the present invention; And a control unit for calculating information about the number of clocks per unit time and the number of clocks per unit time of the data having the fixed bit rate, and including the calculated information in control information of the optical burst switching network. We propose an entry edge node.

An entry edge node clock recovery PLL which calculates the number of clocks per unit time of the entry edge node from the received control information to achieve the objects of the present invention; A demipper for calculating the number of clocks per unit time of the incoming edge node and the number of clocks per unit time when the optical data received by the control information is received by the entry edge node; And a storage unit for outputting the optical data stored according to the number of clocks per unit time received from the demeaper.

Hereinafter, a method for matching the bit rate of the data of the data input to the optical burst switching network according to an embodiment of the present invention and the bit rate of the output data together with the accompanying drawings will be described.

3 illustrates an optical burst switching network composed of an entry edge node, an exit edge node, and a plurality of core nodes according to an embodiment of the present invention. Hereinafter, an operation performed in nodes constituting an optical burst switching network according to an embodiment of the present invention will be described with reference to FIG. 3.

3, each node processes data received by the natural frequency. That is, the natural frequency of node A is f _a , the natural frequency of node B is f _b , the natural frequency of node C is f _c , and the natural frequency of node D is f _d . Each node calculates the difference between its frequency and its natural frequency. That is, each node calculates the difference between the number of clocks per unit time of data transmitted through the input link and the number of clocks per unit time. In detail, each node calculates a value corresponding to a difference between the number of clocks and the number of clocks of data transmitted through an input link during its M cycle (typically, the length of a frame). Alternatively, each node calculates a value corresponding to the difference between the number of clocks and its clock number during M cycles of the input link.

Referring to the operation of the node B, the node B calculates the difference between f _a , the frequency of data transmitted through the input link, and f _b , its own frequency. The node B includes the calculated difference in the control signal and delivers the difference to the node C using the control channel. Node C calculates the difference between f _b , the frequency of data received on the input link, and f _c , its own frequency. Node C includes the calculated difference in the control signal and delivers the difference to Node D. The node D recognizes the natural frequency of the node A by using the difference included in the received control signal.

4 shows a configuration of a core node according to the present invention. According to FIG. 4, the core node includes a scheduler 400, a controller 402, a calculator 404, a synchronization acquirer 406, and an optical burst switch 408. Of course, in addition to the configuration shown in Figure 4 other configuration may be included in the core node, Figure 4 shows only the configuration necessary for convenience of description. In addition, the scheduler 400 and the controller 402 may operate in one configuration.

The scheduler 400 transmits the natural frequency of the core node to the controller 402 and the calculator 404. In addition, the scheduler 400 performs scheduling for transmitting the received data. The control unit 402 determines the transmission time and transmission link of the received data using the control information received from the scheduler 400. The control unit 402 also controls the synchronization acquisition unit 406 to match the processing time of the input burst data with its clock. The optical burst switch 408 switches the data received from the synchronization acquisition unit 406 according to the control command of the controller 402.

The calculator 404 receives the information on the frequency of the input link from the received control signal (BCP). In addition, the calculator 404 receives the natural frequency of the core node from the scheduler 400 and calculates a difference between the frequency of the received input link and the natural frequency. The calculated difference is transmitted to the control unit 402.

The controller 402 updates the vehicle by adding the received vehicle to the vehicle included in the control signal. The updated difference is transmitted to another core node or edge node included in the control signal. Of course, when the data received by the synchronization acquisition unit 406 or the optical burst switch 408 is delayed, the calculation unit 404 also transmits information on this to the control unit 402 at the same time.

When each core node repeatedly performs the operations performed in the configurations illustrated in FIG. 4, the advance edge node node may collect information on the difference in natural frequencies between the entry edge node and the last core node.

5 illustrates a structure of a PLL for obtaining a clock of an entry edge node at an exit edge node according to an embodiment of the present invention. The PLL includes an adder 500, a 1 / TS divider 502, a phase detector 504, a filter 506, a VCO 508, and a 1 / M divider 510. Obviously, the PLL may include other configurations in addition to the above-described configuration, but FIG. 5 illustrates only the configurations necessary for the convenience of description.

The adder 500 receives and adds the difference in clocks accumulated up to the previous core node and the number of clocks during M cycles. As described above, M means frame length. The value added by the adder 500 is transmitted to the 1 / TS divider 502. The 1 / TS divider 502 divides the clock of the previous node received from the input link by the clock received from the adder 500. In this way, the 1 / TS divider 502 transmits the signal converted into the low frequency instead of the high frequency signal to the phase detector 504. The reason for transmitting the low frequency signal instead of the high frequency signal to the phase detector 504 will be described later. The number of clocks per M cycle output from the 1 / TS divider 502 is equal to the number of clocks used by the entry edge node.

The phase detector 504 calculates a clock difference between the clock (phase, frequency) of the signal received from the 1 / TS divider 502 and the signal received from the 1 / M divider 510, and calculates the calculated clock difference. Pass to filter 506. The filter 506 filters out various abnormal frequencies occurring during a loop operation and changes the voltage of the VCO 508 control terminal through a change in the amount of charge accumulated using a capacitor. The VCO 508 delivers a signal having a specific frequency according to the voltage received from the filter. The frequency of the signal output through the VCO 508 of the present invention is equal to the frequency of the signal used at the entry edge node. The 1 / M divider 510 divides the frequency of the signal received from the VCO into M. That is, since the signal output from the VCO 508 is a high frequency signal, an error occurs in the operation of the phase detector 504 when it is used as it is. Therefore, the received high frequency signal is converted into a low frequency signal in order to reduce an error generated.

6 is a diagram illustrating a process of transferring data received from an entry edge node to a core node according to one embodiment of the present invention. Referring to FIG. 6, the entry edge node includes a storage unit 600, a CBR slot allocator 602, a scheduler 604, a data processor 606, a controller 608, a framer 610, and 1/2 ^n. And a divider 612 and a mapper 614.

The storage unit 600 stores CBR data according to the received CBR clock. In addition, the storage unit 600 outputs the CBR data stored according to the received local node clock (its clock). The data processor 606 is allocated a slot for transmitting the received CBR data according to the information received from the CBR slot allocator 602. The data processor 606 transfers the CBR data received in the allocated transmission slot to the framer 610. The framer 610 processes and outputs the received CBR data in units of frames. The CBR slot allocator 602 allocates a slot with the received CRB data. The scheduler 604 outputs the clock of the node itself and transfers its clock to each device including the framer 610 constituting the entry edge node.

The 1/2 ⁿ divider 612 divides the clock of the received local node into 1/2 ⁿ to divide the clock of the received local node into a clock of a low frequency component. 6 is limited to dividing the clock of the local node using the 1/2 ⁿ divider 612, but is not limited thereto. That is, it is apparent that the user may dispense by using another division unit in addition to the 1/2 ⁿ division unit 612. The reason for the division of the clock of the received local node is the same as described above. The mapper 614 extracts information about the clock of the received CBR data and the clock of the local node. That is, information about the difference between the clock of the CBR data and the clock of the local node is extracted, and the extracted information is transmitted to the controller 608. In this way, the advanced edge node can recognize the clock of the CBR data transferred to the advanced edge node.

FIG. 7 illustrates a PLL (demapper) for acquiring a clock number (frequency) per unit time of CBR data transmitted from an entry edge node to an entry edge node according to an embodiment of the present invention. According to FIG. 7, the PLL includes a 1/2 ⁿ divider 702, a 1 / TSm divider 704, an adder 700, a phase detector 708, a filter 708, a VCO 710, and 1 / Mm. The dispensing unit 712 is included. Operations performed by the phase detector 706, the filter 708, the VCO 710, and the 1 / Mm divider 712 are performed by the phase detector 504, the filter 506, and the VCO 508 illustrated in FIG. 5. Since the operation is the same as that performed by the 1 / Mm divider 510, it will be omitted.

The adder 700 adds the clock difference between the clock of the entry edge node and the CBR data received from the mapper and the number of clocks during M cycles. The adder 700 transfers the added clock to the 1 / TSm divider 704. The 1/2 ⁿ divider 702 receives the clock of the entry edge node and divides the received clock into 1/2 ⁿ . The 1/2 ⁿ divider 702 transfers the divided clock to the 1 / TSm divider 704. 1 / TSm division part 704 a division TSm transmitted clock transmitted from the 1/2 parts of ⁿ additions. The value output from the 1 / TSm divider 704 is equal to the clock of the CBR data input to the entry edge node.

FIG. 8 illustrates a configuration for transferring CBR data received from an advanced edge node to the outside of an optical burst switching network according to an embodiment of the present invention. Referring to FIG. 8, the advance edge node includes a data processor 800, a controller 802, an entry edge node clock recovery PLL 804, a storage unit 806, and a demapper 808.

The data processor 800 receives the optical burst data from the core node. The data processor 800 processes the received optical burst data into CBR data and then transfers the received optical burst data to the storage 806. The controller 802 receives control information on the optical burst data received from the core node using a control channel. The received control information is transmitted to the entry edge node clock recovery PLL 804. The entry edge node clock recovery PLL 804 uses its received clock and control information to obtain the natural frequency (clock count per unit time) of the entry edge node as shown in FIG. 5. The demapper 808 performs the same operation as the PLL shown in FIG. That is, the demapper 808 obtains the clock of the CBR data transferred to the entry edge node by using the difference between the clock of the entry edge node and the clock of the CBR data and the clock of the entry edge node. The obtained clock is transferred to the storage unit 806, and the storage unit 806 outputs the stored CBR data using the received clock.

As described above, the present invention can provide a service desired by a user by keeping the clock of the CBR data inputted to the optical burst switching network and the clock of the outputted CBR data the same. In other words, the CBR data inputted to the optical burst switching network cannot provide a service desired by the user by outputting data having a variable bit rate because of differences in natural frequencies and delays between nodes.

While the invention has been shown and described with reference to preferred embodiments for illustrating the principles of the invention, the invention is not limited to the construction and operation as such is shown and described. Rather, those skilled in the art will appreciate that many modifications and variations of the present invention are possible without departing from the spirit and scope of the appended claims. Accordingly, all such suitable changes, modifications, and equivalents should be considered to be within the scope of the present invention.

Claims (14)

In the core node for transmitting the optical data received from the entry edge node or the core node to the entry edge node or core node, Method for transmitting the control information of the optical data, Calculating a difference between the number of clocks per unit time of optical data transferred to an input link and the number of clocks per unit time of its own frequency; And And including the calculated difference in the control information and transmitting the control information. The control information in the optical burst switching network according to claim 1, wherein the calculated difference is added to the difference included in the received control information, and the calculated difference is included in the control information for transmission. Output method. The method of claim 1, wherein the control information includes a time taken to process the received optical data. The method of claim 1, wherein the departure edge node obtains the natural frequency of the entry edge node by using a difference included in the received control information. The method as claimed in claim 1, wherein the entry edge node outputs optical data obtained by converting data having a fixed bit rate, using the node's own natural frequency. The method of claim 5, wherein the control information, And information on the frequency of the data having the fixed bit rate and the natural frequency of the ingress edge node. The method of claim 6, wherein the advance edge node, Obtain the frequency of the data having the natural frequency and the fixed bit rate of the entry edge node by using the information included in the received control information, and the frequency of the optical data received by using the obtained information having the fixed bit rate And control information output in the optical burst switching network. A calculator configured to calculate a difference between the number of clocks per unit time of optical data transmitted through an input link and the number of clocks per unit time of its own frequency; And a controller configured to add and output a difference received from the calculator and a difference included in control information transmitted through the input link. The method of claim 8, wherein the core node, And a synchronization acquiring unit for delaying the optical data to match the received time point of the received optical data with a reference time point of its timeslot. A data processor for reading and processing data having a fixed bit rate according to a clock of the node itself; And And a control unit for calculating information about the number of clocks per unit time and the number of clocks per unit time of the data having the fixed bit rate, and including the calculated information in control information. Edge node. The entry edge node of the optical burst switching network according to claim 10, wherein the storage unit stores the received data having the fixed bit rate according to a clock of the data. An entry edge node clock recovery PLL for calculating a clock count per unit time of the entry edge node from the received control information; A demipper for calculating the number of clocks per unit time of the incoming edge node and the number of clocks per unit time when the optical data received by the control information is received by the entry edge node; And And a storage unit for outputting the optical data stored according to the number of clocks per unit time received from the dememper. The method of claim 12, wherein the control information, And an information about a clock per unit time of nodes located in a path transmitted by the optical data. The method of claim 13, wherein the control information, And the information about the difference between the clock frequency per unit time, the natural frequency of the previous node that transmitted the optical data, and the clock frequency per unit time, the natural frequency of the node receiving the optical data, is sequentially updated. Egress edge node of the switching network.

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