KR20060082752A - Plasma display panel - Google Patents

Abstract

The present invention relates to a plasma display panel, and more particularly, to a plasma display panel capable of high resolution.

A plasma display panel according to the present invention comprises: a panel having a plurality of electrodes formed on a substrate having at least one side inclined; A driving signal is supplied to the electrodes, and a plurality of driving units are disposed in an area corresponding to an edge of the substrate.

Description

Plasma Display Panel             

1 is a view showing an electrode arrangement of a plasma display panel.

2 is a view showing a plasma display panel of the present invention.

3 is a view illustrating the panel of FIG. 2 in more detail.

4 is a view illustrating a driving unit mounted on the panel of FIG. 2.

5 is a view illustrating a discharge cell formed in the panel of FIG. 2.

<Explanation of symbols for the main parts of the drawings>

9, 22: panels 10, 32, 52: data driver

11 scan driver 12 sustain driver

20: front case 24: heat dissipation sheet

26: frame 28: printed circuit board

30: back cover 35: first FPC part

34: second FPC section 37, 57: pad

38, 58: link 39, 55: non-display area

40, 54: display area

The present invention relates to a plasma display panel, and more particularly, to a plasma display panel capable of high resolution.

1 is a diagram illustrating an electrode arrangement of a general plasma display panel.

In FIG. 1, the discharge cell 1 is configured at each intersection of scan electrode lines Y1 to Ym, sustain electrode lines Z1 to Zm, and address electrode lines (or data electrode lines X1 to Xn). Able to know.

The scan electrode lines Y1 to Ym supply the scan pulse and the sustain pulse so that the discharge cells 1 are scanned in units of lines and the discharge is maintained in the discharge cells 1.

The sustain electrode lines Z1 to Zm commonly supply a sustain pulse to maintain the discharge in the discharge cells 1 together with the scan electrode lines Y1 to Ym. The address electrode lines X1 to Xn supply data pulses synchronized with scan pulses in line units so that the discharge cells 1 in which discharges are to be maintained are selected according to the logic value of the data pulses.

A driving unit for supplying a driving signal to each of the electrode lines X, Y, and Z is positioned around the electrodes. Usually, such a driving unit is installed on a printed circuit board (not shown) located on the back of the panel, and from this driving unit, a flexible printed cable (hereinafter referred to as "FPC") or a flat flexible cable (FFC) And pads of the electrodes formed on one side of the panel. In addition, the FPC or FFC is provided in a chip on film (COF) method in which some driver integrated circuits (DICs) of the drivers are formed on the cable, and the driving signals from the drivers are transmitted to the panel electrodes. Feed the fields.

The scan electrode Y, the sustain electrode Z, and the address electrode X formed on the panel 9 are arranged to intersect for the selection of the discharge cells 1. In addition, the data driver 10, the scan driver 11, and the sustain driver 12 are arranged as shown in FIG. 1 in order to supply driving signals to these electrodes efficiently.

Some of the drivers 10, 11, and 12 are also formed on the panel 9 by a chip on glass (COG) method. The reason for this is to efficiently use the space required for the configuration of the plasma display panel due to the large screen, and to consider the efficiency of driving signal transmission.

On the other hand, in order to realize high resolution in the PDP, more discharge cells must be formed in the panel 9 having the same area. Also, as more discharge cells are formed, more electrode lines must be formed. This means that the number of driving integrated circuits of the driving unit increases. That is, it is possible to increase the resolution of the PDP by forming smaller discharge cells in the panel 9 and reducing the width of the electrode lines by using a material having a lower resistance value. However, the driving circuit for supplying signals to the electrode lines needs a certain space for connecting with the electrode lines, it is not easy to reduce the size of the driving integrated circuit mounted on the driving circuit.

That is, there is a problem in that the number of discharge cells and electrode lines increases, and a space for mounting the driving unit and a space for connecting the driving unit and the electrode lines are insufficient.

Accordingly, an object of the present invention is to provide a plasma display panel capable of high resolution.

In order to achieve the above object, a plasma display panel according to the present invention comprises a panel having a plurality of electrodes formed on a substrate inclined at least one side; A driving signal is supplied to the electrodes, and a plurality of driving units are disposed in an area corresponding to an edge of the substrate.

The driving unit is connected to the electrodes by a connection film.

The connection film includes a flexible printed circuit (FPC), a tape carrier package, and a chip on film.

The driving unit is mounted on a region corresponding to the inclined surface of the substrate by a chip on glass method.

A second driving unit is further provided at a region corresponding to at least one surface except the inclined surface of the substrate.

Other features and effects of the present invention in addition to the above object will be revealed through the description of the embodiments with reference to the accompanying drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2 to 5.

2 illustrates a plasma display panel according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the plasma display panel according to the present invention includes a front case 20, a panel 22, a heat dissipation sheet 24, a frame 26, a PCB 28, and a back cover 30. .

The front case 20 is installed on the front of the panel 22 to protect the panel 22 from external impact and contaminants, and is composed of a glass, front filter. The front filter includes an optical characteristic film, an EMI (Electro Magnetic Interference: EMI) shielding film, an infrared shielding film, and the like. The glass protects the front filter from damage from external impact. The optical characteristic film improves the optical characteristics of the PDP by lowering the luminance of red (R) and green (G) among the light incident from the panel 22 and increasing the luminance of blue (B). The electromagnetic shielding film shields electromagnetic waves and prevents electromagnetic waves incident from the panel 22 from being emitted to the outside. The infrared shielding film shields the infrared rays emitted from the panel 22 to prevent the infrared rays above the reference from being emitted to the outside so that signals transmitted using the infrared rays such as a remote controller can be normally transmitted.

The panel 22 includes an upper substrate 42a having a plurality of scan electrode lines (or scan electrodes Y) and a plurality of sustain electrode lines (or sustain electrodes Z), scan electrodes Y, and sustain electrodes. The lower substrate 42b includes a plurality of address electrode lines (or address electrodes X) formed in a direction intersecting the fields Z, and a phosphor layer formed on the front surface of the substrate. The phosphor generates visible light by the discharge between the scan electrodes Y, the sustain electrodes Z, and the address electrodes, and displays a predetermined image by adjusting the transmittance of the visible light. In addition, pads are connected to the electrodes of the IC chip by FPC. The panel 22 has FPC, COF, and electrode lines X, which supply a driving signal to the display area in which discharge cells are formed to display an image by discharge, and to the electrode lines X, Y, and Z formed in the display area. Y, Z) is divided into a non-display area in which a link and a pad are formed. Here, when some integrated circuits of the driving unit are formed in the COG method, they are formed in the non-display area to supply driving signals to some of the electrode lines X, Y, and Z. To this end, the panel 22 has a shape in which an edge of at least one of at least one of the upper substrate 22a and the lower substrate 22b is chamfered as shown in FIG. 2. The PDP of the present invention secures a space for connecting the panel 22 having the chamfered edge and the electrode lines X, Y, and Z of the panel 22 to the driving unit through the chamfered portion.

The heat dissipation sheet 24 is positioned between the panel 22 and the frame 26, and transfers heat generated from the panel 22 to the frame 26 when the PDP is driven. This heat dissipation sheet 24 prevents the temperature of the panel 22 from rising rapidly due to heat generation during PDP driving.

The frame 26 is installed on the rear surface of the panel 22 and supports the panel 22 and serves to dissipate heat generated when the panel 22 is driven. The heat sink 26 is formed of a metal material having good thermal conductivity, for example, aluminum (Al) or the like so that the heat radiation is good.

Printed Circuit Board (PCB) 28 is a scan driver for driving scan electrode lines formed in the panel 22, a sustain driver for driving sustain electrode lines, and address electrode lines. And a control board for controlling the data driver, the scan driver, the sustain driver, and the data driver. In addition, the scan driver, the sustain driver, and the data driver formed on the PCB 28 are connected to the pads of the electrode lines X, Y, and Z formed on the panel 22 by FPC or FFC. In addition, each driving unit may be connected to the COF method in which the driving integrated circuit is mounted on the cable, and some of the driving units may be mounted to the panel 22 in the COG method.

The back cover 30 is fastened together with the front case 20 at the rear of the PDP to protect the PDP from external shocks, contaminants, and the like.

FIG. 3 is a view illustrating the panel of FIG. 2 in more detail, illustrating an example of forming a data driver and an address electrode.

Referring to FIG. 3, the plasma display panel of the present invention includes a panel that forms a polygon by a chamfered surface. The panel 22 includes a display area 40 for displaying an image by electrode lines and discharge cells, and a non-display area 39 formed around the display area 40.

A plurality of electrode lines X, Y, and Z are formed in the display area 40, and ends of the electrode lines X, Y, and Z are padded by a link 38 formed in the non-display area 39. It is connected with 37.                     

In the non-display area 39, pads 37 are formed to be connected to the driving units 32 and 36, and the pads 37 are connected to the electrode lines X, Y, and Z by the link 38, respectively. do.

The edge of the panel 22 is chamfered unlike the conventional rectangular plasma display panel as shown in FIG. 3. As the edges are chamfered, the number of edges that can be connected to the FPC increases by one or more. When these surfaces are called 1st surface (or side surface part) and 2nd surface (or chamfering part), respectively, the 1st surface 36a, the 2nd surface 36b, and the 3rd surface 36c are formed in FIG.

When the number of data lines formed on the panel 22 is m, the first FPC unit 35 for connecting to the first data line X1 to the i-th line Xi is connected to the first surface 36a. The pad 37 and the link 38 are formed as shown in FIG. 3. In addition, a second FPC 34 is formed on the second surface 36b to connect the i + 1th data line Xi + 1 to the mth data line Xm. Here, the first FPC unit 35 and the links and pads connected to the first FPC unit 35 are lateral connections, the second FPC unit 34 and the links and pads connected to the second FPC unit 34 are chamfered. It is called a connection. In this manner, each line of the data driver 32 is divided to correspond to the number of chamfers, and the line and the driver are connected through the FPC unit corresponding to the divided lines.

Accordingly, the plasma display panel of the present invention can easily connect the lines X, Y, and Z to the driving unit even when a large number of lines X, Y, and Z are formed in the panel 9. . That is, the plasma display panel of the present invention can realize high resolution.                     

4 is a diagram illustrating an example in which a part of a driving unit is formed by a COG method.

Referring to FIG. 4, first to third driving units 52 are formed in each of the first to third surfaces 53 formed by chamfered edges of the non-display area 55 in a COG manner. The driving unit 52 is connected to the data lines X1 to Xm of the display area 54 by the pad 57 and the link 58 to supply driving signals, respectively. As shown in FIG. 3, the first driver 52a supplies a driving signal to the first to i-th data lines X1 to Xi, and the second driver 52b to the i + 1 to j-th data lines Xi + 1. The third driving unit 52c supplies a driving signal to the j + 1 to m-th data lines Xj + 1 to Xm, while supplying a driving signal to the to Xj. Here, the first to third drivers 52 are separated for convenience of description and are shown separately from one data driver.

By the above-described method, the PDP according to the present invention provides a panel having a polygonal shape in which at least one surface is further formed. Such a panel structure provides a space for forming a driving circuit, a link and a pad connected to the driving circuit. Therefore, in order to realize high resolution, even if a large number of electrode lines are formed in the display area, a space for forming a link and a pad for connecting with a driving circuit for driving the same is ensured.

5 is a view showing a discharge cell formed in a panel.

Referring to FIG. 5, the discharge cell of the PDP includes a scan electrode Y and a sustain electrode Z formed on the upper substrate 44a, and an address electrode X formed on the lower substrate 44b. Each of the scan electrode Y and the sustain electrode Z has a line width smaller than the line widths of the transparent electrodes 62Y and 62Z and the transparent electrodes 62Y and 62Z and is formed on one edge of the transparent electrode 63Y. , 63Z).

The transparent electrodes 62Y and 62Z are usually made of metal such as indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). 44a). The metal bus electrodes 63Y and 63Z are formed of metals such as chromium (Cr) on the transparent electrodes 62Y and 62Z, thereby reducing the voltage drop caused by the transparent electrodes 62Y and 62Z having high resistance. The upper dielectric layer 64 and the passivation layer 66 are stacked on the upper substrate 44a on which the scan electrode Y and the sustain electrode Z are arranged side by side.

  The passivation layer 66 prevents damage to the upper dielectric layer 64 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. Magnesium oxide (MgO) is used as the protective film 66.

The lower dielectric layer 72 and the partition wall 74 are formed on the lower substrate 44b on which the address electrode X is formed, and the phosphor layer 76 is coated on the surfaces of the lower dielectric layer 72 and the partition wall 74. The address electrode X is formed in a direction crossing the scan electrode Y and the sustain electrode Z.

Wall charges formed by discharge are accumulated in the upper dielectric layer 64 and the lower dielectric layer 72. The dielectric layers 64 and 72 and the protective film 66 can lower the discharge voltage applied from the outside.

The partition wall 74 provides a discharge space together with the upper and lower substrates 44. The partition wall 74 is formed in parallel with the address electrode X to prevent ultraviolet rays and visible rays generated by the gas discharge from leaking into the adjacent discharge cells. The discharge space provided between the upper / lower substrate 44 and the partition wall 74 includes an inert gas such as He, Ne, Ar, Xe, Kr for discharging the gas, a discharge gas (or a mixed gas) having a combination thereof, or a discharge. Excimer gas that can generate ultraviolet rays is filled.

The phosphor layer 76 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red (R), green (G), and blue (B).

As described above, the plasma display panel according to the present invention provides a polygonal panel having chamfered edges. Since the plasma display panel according to the present invention provides a panel having a plurality of side surfaces by chamfered edges, it is easy to arrange a driving circuit for supplying a driving signal to the lines even if a plurality of lines are formed in a limited panel. Become. In addition, the plasma display panel according to the present invention has a connection space for connecting the driving circuit and the line by the multi-lateral panel, thereby increasing the driving circuit according to the increase of the line.

As a result, the plasma display panel of the present invention can secure high resolution by securing a space for the driving circuit and the connection even if the number of electrode lines formed in the display area is increased.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited by the detailed description of the invention described in the specification, but should be defined by the claims.

Claims (6)

A panel having a plurality of electrodes formed on at least one side of the inclined substrate; And a plurality of driving parts that supply driving signals to the electrodes and are located in an area corresponding to an edge of the substrate. The method of claim 1, And the driving part is connected to the electrodes by a connecting film. The method of claim 2, The connection film includes a flexible printed circuit (FPC), a tape carrier package (Tape Carrier Package) and a chip on film (Chip On Film) characterized in that the plasma display panel. The method of claim 1, The driving unit is mounted on the chip on glass (Chip On Glass) method, characterized in that the plasma display panel. The method of claim 1, And the driving unit is mounted in a chip on glass method in an area corresponding to the inclined surface of the substrate. The method of claim 1, And a second driving part positioned in an area corresponding to at least one surface except the inclined surface of the substrate.

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