KR20060081111A - Internal voltage down converter in semiconductor memory device - Google Patents

Abstract

The present invention relates to an internal power supply voltage generation circuit of a semiconductor memory device. According to the present invention, a PMOS transistor, which is a current source of an IVC drive of an IVC circuit that supplies a constant internal power supply voltage, is driven by receiving a first PMOS transistor to which a Schmitt trigger is applied and an enable signal output from the first PMOS transistor. Two PMOS transistors are implemented. As a result, the current driving capability of the IVC driver is improved compared to the case of implementing a conventional PMOS transistor, so that it is possible to supply a constant internal voltage regardless of the environmental change of the system. It is advantageous to high integration by implementing the separation by two PMOS transistors of size. In addition, by shortening the charging time of the IVC level has a more advantageous advantage in high speed operation.

Semiconductor, Internal power supply voltage generation circuit, Schmitt trigger, Sea morse

Description

Internal Voltage Down Converter in Semiconductor Memory Device             

1 shows an IVC circuit according to the prior art.

2 shows an IVC circuit according to a preferred embodiment of the present invention.

FIG. 3 shows a control scheme for the IVC driver of the IVC circuit shown in FIG.

4 shows a conventional Schmitt trigger applied to the IVC circuit shown in FIG.

5 shows the voltage detection result for the Schmitt trigger applied to the IVC driver according to the present invention.

6 shows an IVC simulation result for an IVC circuit when the IVC driver according to the present invention is applied.

<Description of Symbols for Main Parts of Drawings>

100: IVC circuit 102: bandgap reference

104: reference voltage generator 106: IVC driver

108: first driving PMOS transistor 110: second driving PMOS transistor                 

112: semiconductor memory circuit

The present invention relates to an internal power supply voltage generation circuit of a semiconductor memory device, and more particularly, to an internal power supply voltage generation circuit of a semiconductor memory device having improved current driving capability to supply a stable voltage regardless of an environment change of a system. will be.

Recently, with the rapid development of the information communication field and the rapid popularization of information media such as computers, semiconductor memory devices are also rapidly developing. As a result, it is required to operate at high speed and have a large storage capacity in terms of its functional aspects, and thus the degree of integration of semiconductor devices is gradually increasing.

On the other hand, the internal power supply voltage generation circuit of the semiconductor memory device is a circuit for supplying a stable and constant internal power supply voltage to the inside of the semiconductor memory chip regardless of the change in the external power supply voltage. However, in supplying a stable voltage inside the semiconductor memory chip through the internal power supply voltage generation circuit, the amount of current flowing through the internal power supply voltage generation circuit itself is very large.

FIG. 1 illustrates an IVC (Internal Voltage Down Converter: 1) circuit according to the prior art applied when the internal power of a semiconductor memory chip is used by decreasing an external power supply voltage.

Referring to FIG. 1, the IVC circuit 1 may include a bandgap reference 10 generating a constant reference voltage VREF regardless of an external power source, and a reference voltage VREF generated from the bandgap reference 10. A reference voltage generator 12 and a large driving PMOS transistor 18 for generating a constant reference voltage SREF based on the reference voltage are provided, and the reference voltage SREF generated from the reference voltage generator 12 is converted into a reference voltage generator 12. It consists of an IVC driver 14 for supplying into the circuit. In addition, a semiconductor memory circuit 18 that receives an internal power supply voltage generated from the IVC driver 14 is connected to a rear end of the IVC driver 14.

The operation of the IVC circuit 1 will be described below.

First, a constant reference voltage VREF is generated through the band gap reference 10 regardless of an external power source. Then, the SREF voltage generated through the reference voltage generator 12 is generated based on the reference voltage VREF generated through the bandgap reference 10. The SREF voltage is fed back to the semiconductor memory circuit 18 through the IVC driver 14.

However, the following problems exist in the conventional IVC circuit 1 as described above. First, since the current of the circuit using the IVC as the power supply voltage must be handled, the driving PMOS transistor 16 of the IVC driver 14 must be implemented in a very large size, which is disadvantageous in high integration. In addition, since the gate voltage of the driving PMOS transistor 16 driving the IVC driver 14 is an analog input, when the IVC level drops a lot, the IVC drive 14 may supply a large current at a very low voltage level. When the IVC level is gradually increased, the gate voltage of the driving PMOS transistor 16 is also gradually increased to lower the current driving capability of the driving PMOS transistor 16. Therefore, it takes a long time until the IVC level is charged to an intact level, which is not suitable for a semiconductor memory device operating at a high speed.

SUMMARY OF THE INVENTION An object of the present invention for solving the above-described problems is to use a size of a PMOS transistor, which is a current source of an IVC driver, more efficiently, thereby making it possible to quickly correct an IVC level while being suitable for highly integrated devices. An internal power supply voltage circuit of the device is provided.

Another object of the present invention is to provide an internal power supply voltage circuit of a semiconductor memory device which does not reduce the current driving capability of a PMOS transistor which is an IVC driver even when the IVC level is increased.

Another object of the present invention is to provide an internal power supply voltage circuit of a semiconductor memory device capable of shortening the charging time of the IVC level to enable high speed operation.

In accordance with another aspect of the present invention, there is provided an internal power supply voltage generation circuit of a semiconductor memory device, including: a bandgap reference generating a constant reference voltage VREF regardless of an external power supply; A reference voltage generator configured to generate a constant reference voltage SREF based on the reference voltage VREF generated from the bandgap reference; And a first driving PMOS transistor which detects an output of the amplifier fed back the IVC level and generates an enable signal EN generated by a Schmitt trigger when the output signal of the amplifier falls. And a second driving PMOS transistor that boosts the IVC level by the enabled signal EN, and includes an IVC driver for supplying the reference voltage SREF generated from the reference voltage generator into the semiconductor memory circuit. It features.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention. The present invention is not limited to the embodiments set forth below, but can be embodied in various forms within the scope of the present invention without departing from the scope of the present invention, but only this embodiment to complete the disclosure of the present invention, It is provided to fully inform the knowledge of the scope of the invention.

When the range of the operating power supply voltage of the semiconductor memory chip is wide, an internal power supply voltage generation circuit for supplying a wide range of power supply voltage is typically used in the chip. In FIG. 2, an IVC circuit according to a preferred embodiment of the present invention is used. 100 is shown.

Referring to FIG. 2, the IVC circuit 100 according to the present invention includes a bandgap reference 102 generating a constant reference voltage VREF regardless of an external power supply, and a reference voltage generated from the bandgap reference 102. A reference voltage generator 104 generating a constant reference voltage SREF based on VREF and an IVC driver 106 for supplying a reference voltage SREF generated from the reference voltage generator 104 into a circuit. It consists of. In addition, a semiconductor memory circuit 112 for receiving an internal power supply voltage generated from the IVC driver 106 is connected to a rear end of the IVC driver 106. In this case, it is the core configuration of the present invention that the IVC driver 106 is formed with two driving PMOS transistors 108 and 110 instead of one large driving PMOS transistor as in the related art.

Next, the operation of the IVC circuit 100 having the above configuration will be described.

First, the band gap reference 102 generates a constant reference voltage VREF regardless of an external power source. Thereafter, the SREF voltage level is increased through the reference voltage generator 104 based on the reference voltage VREF generated through the bandgap reference 102. The SREF voltage is fed back to the semiconductor memory circuit 112 through the IVC driver 106.

The PMOS transistor, which is the current source used in the IVC driver 106, is characterized by using a smaller size than the PMOS transistor used in the conventional IVC driver. For example, when the expected load current is 700 mA, conventionally, a large size PMOS transistor having an ability to handle a current of 700 mA or more is formed in the IVC driver. In this case, since the gate voltage of the PMOS transistor, which is the current source of the IVC driver, is an analog voltage, when the IVC level drops a lot, the IVC driver can supply a large current at a very low voltage level. The gate voltage of the MOS transistor is increased, which reduces the driving capability of the IVC driver. As a result, there was a problem that it takes a long time before the IVC level is precharged to the desired level.

Accordingly, the present invention proposes a more efficient IVC driver 106 in which PMOS, which is an IVC driver, is divided into two and each control is changed in order to solve the conventional problems as described above.

The configuration and operation of the IVC driver 106 according to the present invention will be described in detail as follows. The second driving PMOS driver 110 controls the driver with a feedback signal of the amplifier as in the prior art. As shown in FIG. 3, the first driving PMOS driver 108 detects the output of the amplifier fed back the IVC level, and the enable signal generated by the Schmitt trigger when the output signal of the amplifier falls. By transmitting (EN) to the second driving PMOS driver 110 as a driving signal, it is possible to boost the IVC level faster. In this case, a conventional Schmitt trigger applied to the first driving PMOS driver 108 is illustrated in FIG. 4. On the other hand, if the output of the amplifier rises above a certain level, overshooting does not occur because the PMOS transistor is disabled by the Schmitt trigger.

On the other hand, Figure 5 shows the voltage detection result for the Schmitt trigger applied to the IVC driver according to the present invention.

Referring to FIG. 5, when the control signal L1 is detected using the Schmitt trigger to detect the appropriate level of V1 and V2, V2 is made equal to the target IVC level and V1 detects the level of IVC + delta so that the IVC level Overshooting above the level will turn the driver off and drop below the desired IVC level, allowing the IVC driver to be sufficiently on to quickly precharge the IVC level. Most overshoots occur rapidly, with no problem in control speed as the IVC node changes rapidly to the IVC + delta level. On the contrary, since the discharge of the IVC level changes slowly, it is more efficient to set the upper control level of the Schmitt trigger to IVC + delta.

6 shows an IVC simulation result for an IVC circuit when the IVC driver according to the present invention is applied.

Referring to FIG. 6, the X axis represents a current value and the Y axis represents a voltage value. L2 represents the enable signal of the proposed scheme, L3 represents the IVC level of the proposed scheme, and L4 represents the IVC level measured through the simulation. As can be seen from the simulation result of FIG. 6, it can be seen that L3 representing the IVC level of the proposed scheme and L4 representing the IVC level measured through the simulation are almost identical.

As described above, in the present invention, a PMOS transistor functioning as a current source in an IVC driver is driven by receiving a first PMOS transistor to which a Schmitt trigger is applied and an enable signal output from the first PMOS transistor. Implemented separately, it is possible to expect faster level correction speeds for IVC drivers of the same size as in the prior art.

As described above, according to the present invention, in implementing an IVC circuit that supplies a stable and constant internal power supply voltage to a semiconductor memory chip regardless of a change in external power supply voltage, the current source of the IVC drive of the IVC circuit is The MOS transistor is divided into a first PMOS transistor to which a Schmitt trigger is applied and a second PMOS transistor driven by receiving an enable signal output from the first PMOS transistor. As a result, the current driving capability of the IVC driver is improved compared to the case of the conventional PMOS transistor, thereby providing a constant internal voltage regardless of the environmental change of the system.

In addition, the conventional large sized PMOS transistor is separated into two smaller PMOS transistors, which is advantageous in high-integration devices, and high-speed operation can be realized by shortening the charging time of the IVC level. .

Claims (3)

In an internal power supply voltage generation circuit of a semiconductor memory device: A bandgap reference for generating a constant reference voltage VREF regardless of an external power supply; A reference voltage generator configured to generate a constant reference voltage SREF based on the reference voltage VREF generated from the bandgap reference; And A first driving PMOS transistor that detects an output of the amplifier fed back the IVC level and generates an enable signal EN generated when the output signal of the amplifier falls, and an enable signal generated from the first driving PMOS transistor ( And an IVC driver comprising a second driving PMOS transistor for boosting the IVC level by receiving EN) as a drive signal. The internal power supply voltage generation circuit of claim 1, wherein the enable signal is generated by a Schmitt trigger. In an internal power supply voltage generation circuit of a semiconductor memory device: A bandgap reference for generating a constant reference voltage VREF regardless of an external power supply; A reference voltage generator configured to generate a constant reference voltage SREF based on the reference voltage VREF generated from the bandgap reference; And The first driving PMOS transistor and the first driving PMOS transistor configured to detect the output of the amplifier fed back the IVC level and generate the enable signal EN generated by the Schmitt trigger when the output signal of the amplifier falls. And a second driving PMOS transistor that boosts the IVC level by the enable signal EN, and includes an IVC driver for supplying a reference voltage SREF generated from the reference voltage generator into a semiconductor memory circuit. An internal power supply voltage generation circuit of a semiconductor memory device.

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