KR20060076162A - Non-volatile ferroelectric memory device and control method therefor - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile ferroelectric memory device and a method of controlling the same, and discloses a technique for controlling read / write operations of a memory cell array whose channel resistance varies according to a polarization state of the ferroelectric. The present invention senses and amplifies data read from a memory cell through a sense amplifier, stores the amplified data in a register, writes high data to all activated cells, and stores the data in a selected memory cell according to the output of the column decoder. New data applied from the bus unit is written, and data stored in a register is written back to an unselected memory cell.

Description

Non-volatile ferroelectric memory device and control method therefor {Non-volatile ferroelectric memory device and control method therefor}

1A-1C are cell cross-sectional views and symbols of a nonvolatile ferroelectric memory device in accordance with the present invention.

2 is a diagram illustrating a unit memory cell array of a nonvolatile ferroelectric memory device according to the present invention;

3 is a block diagram of a nonvolatile ferroelectric memory device according to the present invention;

4 is a memory cell array of a nonvolatile ferroelectric memory device according to the present invention;

5 is a detailed circuit diagram according to a first embodiment of the sense amplifier of FIG.

6A is a timing diagram at the read operation of the sense amplifier of FIG. 5.

6B is an operation timing diagram relating to low data write operation and high data retention of the sense amplifier of FIG. 5.

7 is a detailed circuit diagram according to a second embodiment of the sense amplifier of FIG.

8A is a timing diagram at the read operation of the sense amplifier of FIG. 7.

8B is an operation timing diagram illustrating a high data write operation, a high data hold operation, and a low data write operation of the sense amplifier of FIG. 7.

9 is a flowchart for explaining a write operation of the method of controlling a nonvolatile ferroelectric memory according to the present invention;

10 is a view for explaining the write and write-back path of the nonvolatile ferroelectric memory device according to the present invention.

11 is a view for explaining a write operation step of a method of controlling a nonvolatile ferroelectric memory according to the present invention;

12 is an operation timing diagram for cell data sensing of a nonvolatile ferroelectric memory control method according to the present invention;

13 is a timing diagram of a high data write operation of the nonvolatile ferroelectric memory control method according to the present invention.

14 is an operation timing diagram relating to low data write operation and high data retention of the nonvolatile ferroelectric memory control method according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile ferroelectric memory device and a method of controlling the same. In a nano scale memory device, a memory cell whose channel resistance varies according to polarization state of a ferroelectric is implemented as an array to read / write a nonvolatile memory cell. It is a technology that controls the operation.

In general, nonvolatile ferroelectric memory, or ferroelectric random access memory (FeRAM), has a data processing speed of about dynamic random access memory (DRAM) and is attracting attention as a next-generation memory device because of its characteristic that data is preserved even when the power is turned off. have.

The FeRAM is a memory device having a structure almost similar to that of a DRAM, and uses a ferroelectric material as a capacitor material to utilize high residual polarization characteristic of the ferroelectric material. Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

Description of the above-described FeRAM has been disclosed in Korean Patent Application No. 2001-57275 filed by the same inventor as the present invention. Therefore, a detailed description of the basic configuration of the FeRAM and its operation will be omitted.

The unit cell of the conventional nonvolatile ferroelectric memory device includes one switching element connecting a sub bit line and a nonvolatile ferroelectric capacitor by switching according to a state of a word line, and one connected between one end of the switching element and a plate line. Of nonvolatile ferroelectric capacitors. Here, the switching element of the conventional nonvolatile ferroelectric memory device mainly uses an NMOS transistor whose switching operation is controlled by a gate control signal.

However, in such a conventional nonvolatile ferroelectric memory device, when the cell size becomes small, data retention characteristics are deteriorated, so that normal cell operation becomes difficult. That is, when a cell read operation, voltage is applied to an adjacent cell, and data is destroyed, thereby causing interface noise between cells. In addition, since a write voltage is applied to an unselected cell during the write operation of the cell, data of the unselected cells is destroyed, thereby making it difficult to perform a random access operation.

The present invention was created to solve the above problems, and improves data retention characteristics by forming a floating channel layer including an N-type drain region, a P-type channel region, and an N-type source region between a word line and a bottom word line. By doing so, it is possible to improve the reliability of the cell.

In addition, an object of the present invention is to improve the read / write operation method in the above-described memory cell array to enable a random access operation.

A nonvolatile ferroelectric memory device of the present invention for achieving the above object, the switching operation is selectively controlled in accordance with the voltage applied to the plurality of word lines and the plurality of bottom word lines, respectively, and comprises a plurality of unit memory cells connected in series A memory cell array in which a plurality of unit cell arrays are provided in row and column directions; A sense amplifier unit for sensing and amplifying data applied from the memory cell array and storing the amplified data; A column decoding unit decoding a column selection signal for selecting a memory cell; And a column switching unit for controlling a switching operation according to an output of the column decoding unit to selectively connect the sense amplifier unit and the data bus, wherein each of the plurality of unit memory cells includes a ferroelectric layer, and according to a polarity state of the ferroelectric layer. Lead / write control of data by inducing different channel resistance in the region.

In addition, the nonvolatile ferroelectric memory control method of the present invention includes the steps of sensing the data stored in the memory cell by inducing different channel resistance in the channel region of the floating channel layer according to the polarity state of the ferroelectric layer; Amplifying data of all activated memory cells through a sense amplifier and storing the amplified data in a register; Storing hidden data in all activated memory cells; And writing the input data applied through the data bus to the selected memory cell according to whether the column selection signal is activated, and writing back data stored in the register to the unselected memory cell.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1A and 1B are unit cell cross-sectional views of a nonvolatile ferroelectric memory device according to the present invention.

1A is a cross-sectional view of a unit cell viewed in a direction parallel to a word line.

First, the bottom word line 10 formed in the lowermost layer and the word line 17 formed in the uppermost layer are arranged in parallel. Here, the bottom word line 10 and the word line 17 are selectively driven by the same row address decoder (not shown). In addition, an insulating layer 11 is formed on the bottom word line 10, and a floating channel layer 15 formed of a P-type channel region 12 is formed on the insulating layer 11. Is formed.

In addition, a ferroelectric layer 16 is formed on the floating channel layer 15, and a word line 17 is formed on the ferroelectric layer 16.

1B is a cross-sectional view of the unit cell viewed in a direction perpendicular to the word line.

First, the insulating layer 11 is formed on the bottom word line 10. In addition, a floating channel layer 15 is formed on the insulating layer 11. Here, the drain region 13 and the source region 14 of the floating channel layer 15 are made of N type, and the channel region 12 is made of P type to be in a floating state.

In addition, as the semiconductor of the floating channel layer 15, a material such as carbon nanotube, silicon, or Ge (germanium) may be used. In addition, a ferroelectric layer 16 is formed on the P-type channel region 12 of the floating channel layer 15, and a word line 17 is formed on the ferroelectric layer 16.

Accordingly, the present invention reads and writes data using the characteristic that the channel resistance of the floating channel layer 15 varies according to the polarization state of the ferroelectric layer 16. That is, when the polarity of the ferroelectric layer 16 induces positive charge in the channel region 12, the memory cell is in a high resistance state and the channel is turned off. On the contrary, when the polarity of the ferroelectric layer 16 induces negative charge in the channel region 12, the memory cell is in a low resistance state and the channel is turned on.

The unit memory cell of the present invention having such a configuration is intended to be represented as a symbol shown in FIG. 1C.

2 is a diagram illustrating a unit memory cell array of a nonvolatile ferroelectric memory device according to the present invention.

The present invention includes switching elements N1 and N2 and a plurality of memory cells Q1 to Qm. Here, the switching element N1 is connected between the bit line BL_1 and the memory cell Q1 to apply the selection signal SEL_1 through the gate terminal. The switching element N2 is connected between the sensing line S / L_1 and the memory cell Qm to receive the selection signal SEL_2 through the gate terminal.

In addition, the plurality of memory cells Q1 to Qm are connected in series between the switching elements N1 and N2 to selectively switch between the word lines WL_1 to WL_m and the bottom word lines BWL_1 to BWL_m. The detailed configuration of each memory cell Q1 to Qm is as shown in FIG. 1B. Accordingly, the source terminal of the memory cell Q1 is connected with the switching element N1, and the drain terminal of the memory cell Qm is connected with the switching element N2.

3 is a configuration diagram of a nonvolatile ferroelectric memory device according to the present invention.

The present invention includes a memory cell array 20, a sense amplifier unit 30, a column switching unit 40, a data bus 50, and a column decoding unit 60.

Here, the memory cell array 20 includes a plurality of unit memory cell arrays shown in FIG. 2 in the column and row directions. The plurality of sense amplifiers S / A0 to S / Am provided in the sense amplifier unit 30 are connected in one-to-one correspondence with the plurality of bit lines BL_0 to BL_m. The plurality of switching elements N3 to Nm included in the column switching unit 40 are connected between the plurality of sense amplifiers S / A0 to S / Am and the data bus 50 to be switched by the output of the column decoding unit 60. The operation is optionally controlled.

In addition, the plurality of column switches C / S_0 to C / S_n included in the column decoding unit 60 are connected to gate terminals of the plurality of switching elements N3 to Nm, thereby selectively switching the switching operations of the plurality of switching elements N3 to Nm. To control.

4 illustrates a memory cell array of a nonvolatile ferroelectric memory device according to the present invention.

In the present invention, a plurality of unit memory cell arrays 20 are provided in an area where a plurality of bit lines BL_1 to BL_n and a plurality of sensing lines S / L_1 to S / L_n cross each other and are arranged in a row and column direction. The configuration of each unit cell array 20 is as shown in FIG. 2.

FIG. 5 is a detailed circuit diagram according to the first embodiment of the sense amplifier in the sense amplifier unit 30 of FIG.

The sense amplifier includes a bit line precharge unit 100, a read control unit 200, and a write control unit 300.

The bit line precharge unit 100 includes an NMOS transistor NM1 to which a ground voltage VSS is connected to a source thereof, a drain thereof is connected to a bitline BL_1, and a bitline precharge control signal BLGND is applied to a gate thereof. That is, the NMOS transistor NM1 precharges the bit line BL_1 to the ground voltage level according to the bit line precharge control signal BLGND.

The read control unit 200 includes a switching unit 210, a precharge unit 220, and an amplifier 230. The switching unit 210 includes an NMOS transistor NM2 controlled by the sense amplifier switching control signal SSW to apply a signal of the bit line BL_1 to the data latch input node SALIN. The precharge unit 220 includes a PMOS transistor PM1 that is controlled by the sense amplifier precharge control signal SAPRE to apply the power supply voltage VDD level to the data latch input node SALIN.

The amplifier 230 includes a data latch control unit 231 and a data latch unit 232 to amplify and output data loaded on the bit line BL_1.

The data latch control unit 231 includes NMOS transistors NM4 and NM5 connected in series between one side of the data latch unit 232 and the ground voltage terminal. The NMOS transistors NM4 and NM5 are respectively controlled by the signal of the data latch input node SALIN and the sense amplifier latch control signal SALAT to apply the ground voltage VSS level to the input terminal of the data latch unit 232. The data latch unit 232 includes inverters IV1 and IV2 having a latch structure in which inputs of each other are connected to output ends of each other.

The light control unit 300 is controlled by the light switching control signal WSW to apply the voltage of the bit line BL_1 to the sense amplifier output node SALOUT in the read mode to precharge the sense amplifier output node SALOUT, and to output the sense amplifier in the write mode. An NMOS transistor NM3 for transferring the data of the node SALOUT to the bit line BL_1 is provided.

6A is a timing diagram of a read operation of the sense amplifier of FIG. 5.

First, it is assumed that data stored in the memory cell Q1 shown in FIG. 2 is read for the read operation. When the cell Q1 connected to WL_1 is selected among the cell arrays connected to any bit line BL_1, the sensing current icell flows from the sense amplifier to the bit line BL_1.

The t0 section is defined as a precharge section of the memory cell. When the selection signal SEL_1 transitions high in the t1 period, the switching element N1 is turned on. Accordingly, the bit line BL_1 and the source terminal of the memory cell Q1 are connected. At this time, the selection signal SEL_2, the plurality of word lines WL_1 to WL_m and the plurality of bottom word lines BWL_1 to BWL_m are kept low. The bit line BL_1 and the sensing line S / L_1 remain low. The above is illustrated in FIG. 9 as a description relating to the memory cell array of FIG.

At this time, in the sense amplifier of FIG. 5, the bit line precharge control signal BLGND is enabled at the high level, and the bit line BL_1 is precharged to the ground voltage level, and the sense amplifier switching control signal SSW is enabled at the high level. NMOS transistor NM2 is turned on. Accordingly, the ground voltage level signal of the bit line BL_1 is applied to the data latch input node SALIN, and the data latch input node SALIN is also precharged to the ground voltage level. In addition, the write switching control signal WSW is enabled to the high level, and the ground voltage level signal of the bit line BL_1 is applied to the sense amplifier output node SALOUT, thereby precharging the sense amplifier output node SALOUT.

Subsequently, the bottom word lines BWL_2 to BWL_m are enabled at a high level in the period t2, and the memory cells Q2 to Qm are connected to the bit line BL_1 through the bottom word lines BWL_2 to BWL_m, and the sense amplifier precharge signal SAPRE goes to the low level. The PMOS transistor PM1 is turned on to apply the power supply voltage VDD level to the data latch input node SALIN. Accordingly, the sensing voltage due to the power supply voltage VDD level is set in the bit line BL_1 through the NMOS transistor NM2. In this case, the sensing voltage is equal to the level of the difference between the sense amplifier switching voltage and the threshold voltage of the NMOS transistor NM2 (SSW-Vt).

Next, when the sense amplifier switching control signal SSW is disabled to the low level in the t3 period, the NMOS transistor NM2 is turned off so that the voltage level of the bit line BL_1 maintains or grounds the voltage level set in the t2 period according to the cell sensing current icell. Lower to the voltage level.

That is, if the cell data is "0", the cell is in the on state and the cell sensing current icell is positive current. If the cell data is "1", the cell is off and the cell sensing current icell becomes zero. The cell with the cell data of "0" lowers the set voltage level of the bit line BL_1 to the ground voltage level, and the cell with the cell data of "1" maintains the voltage of the bit line BL_1 at the set voltage state.

Thereafter, during the period t4 before the sense amplifier switching control signal SSW is enabled to the high level, the sense amplifier precharge control signal SAPRE is disabled to the high level to turn off the PMOS transistor PM1, and then the sense amplifier switching control at the period t5. Enable signal SSW to high level to turn on NMOS transistor NM2.

Accordingly, if the bit line BL_1 is set, the level of the data latch input node SALIN does not change. If the bit line BL_1 is at the ground voltage level, the ground voltage level is applied to the data latch input node SALIN. That is, when the cell data is "1", the bit line BL_1 is set, and when the cell data is "0", the bit line BL_1 is at the ground voltage level, so the data latch input node SALIN is at the ground voltage level.

Meanwhile, in the period t5, the sense amplifier latch control signal SALAT is enabled at a high level, and the NMOS transistor NM5 is turned on. When the cell data is "0", the NMOS transistor NM4 is turned off and the ground voltage level is applied to the sense amplifier output node SALOUT. When the cell data is "1", the NMOS transistor NM4 is turned on to apply a high level signal to the sense amplifier output node SALOUT.

6B is an operation timing diagram relating to low data write operation and high data retention of the sense amplifier of FIG. 5.

First, it is assumed that the memory cell Q1 shown in FIG. 2 is selected during the write operation of data "0". The t0 section is defined as a precharge section of the memory cell.

When the selection signal SEL_1 transitions high in the t1 period, the switching element N1 is turned on. Accordingly, the bit line BL is connected to the source terminal of the memory cell Q1. At this time, the selection signal SEL_2, the plurality of word lines WL_1 to WL_m and the plurality of bottom word lines BWL_1 to BWL_m are kept low. The bit line BL_1 and the sensing line S / L_1 remain low. The above is illustrated in FIG. 9 as a description relating to the memory cell array of FIG.

Meanwhile, the sense amplifier of FIG. 5 always disables the sense amplifier switching control signal SSW to the ground voltage level during the write operation, and disables the sense amplifier latch control signal SALAT to the ground voltage level, and the sense amplifier precharge control signal SAPRE is powered. The NMOS transistors NM2, NM5 and PMOS transistor PM1 are turned off by disabling to the voltage level.

In the t1 period, the bit line precharge control signal BLGND is enabled to the high level, the bit line BL_1 is precharged to the ground voltage level, and all the bottom word lines BWL_1 to BWL_m are enabled to the high level, so that all the memory cells Q1 to Qm are It is connected to the bit line BL_1 through the bottom word lines BWL_1 to BWL_m so that data applied to the bit line BL_1 can be transferred to all the cells Q1 to Qm.

Thereafter, the write switching control signal WSW is enabled to the high level in the period t2, and the NMOS transistor NM3 is turned on. Accordingly, the data of the sense amplifier output node SALOUT is transferred to the bit line BL_1.

In the period t3, the word line WL_1 is enabled at a high level to write the data of the bit line BL_1 to the cell connected to the word line WL_1. That is, if the data transferred to the bit line BL_1 is "0", "0" is written to the selected cell. If the data transferred to the bit line BL_1 is "1", the "1" is maintained in the selected cell.

That is, electrons are accumulated in the P-type channel region 12 of the memory cell Q1 by the word line WL_1. Accordingly, a positive voltage is applied to the word line WL_1 and a threshold voltage difference is generated so that polarity is formed so that channel electrons are induced in the ferroelectric layer 16. Accordingly, data "0" can be written in the memory cell Q1. On the other hand, when the data "1" stored in the memory cell Q1 is to be kept as it is, a high voltage is applied to the bit line BL_1 so that the voltage of the bit line BL_1 is applied to the memory cell Q1. Accordingly, data "1" can be preserved by preventing electrons from being formed in the channel region 12.

Then, in the period t4, the word line WL_1, the write switching control signal WSW, and all the bottom word lines BWL_1 to BWL_m transition to the ground voltage level again, and the bit line BL_1 is freed to the ground voltage level by the bit line precharge control signal BLGND. To complete the write operation. Thereafter, when the selection signal SEL_1 of FIG. 2 transitions to the low level, the switching element N1 is turned off.

FIG. 7 is a detailed circuit diagram according to a second embodiment of the sense amplifier of the sense amplifier unit 30 of FIG.

The sense amplifier includes a precharge unit 400, a read control unit 500, and a light control unit 600.

The precharge unit 400 includes NMOS transistors NM9 and NM10 controlled by the bit line precharge control signal BLGND to precharge the bit line BL_1 and the sense amplifier bar output node / SALOUT to the ground voltage VSS level, respectively. The NMOS transistors NM9 and NM10 are connected in series between the bit line BL_1 and the output terminal of the data latch unit 532.

The read controller 500 includes a switching unit 510, a precharge unit 220, and an amplifier 230. The switching unit 510 includes an NMOS transistor NM6 that is controlled by the sense amplifier switching control signal SSW to apply the signal of the bit line BL_1 to the data latch input node SALIN. The precharge unit 520 includes a PMOS transistor PM2 that is controlled by the sense amplifier precharge control signal SAPRE to apply the power supply voltage VDD level to the data latch input node SALIN.

The amplifier 530 includes a data latch control unit 531 and a data latch unit 532 to amplify and output data carried on the bit line BL_1.

The data latch control unit 531 includes NMOS transistors NM7 and NM8 connected in series between one side of the data latch unit 532 and a ground voltage terminal. The NMOS transistors NM7 and NM8 are respectively controlled by the signal of the data latch input node SALIN and the sense amplifier latch control signal SALAT to apply the ground voltage VSS level to the input terminal of the data latch unit 532. The data latch unit 532 includes inverters IV3 and IV4 having a latch structure in which inputs of each other are connected to output ends of each other.

In the read mode, the write control unit 600 applies the voltage of the bit line BL_1 to the sense amplifier output node SALOUT to precharge the sense amplifier output node SALOUT. In the write mode, the write controller 600 applies the bit line BL_1 according to the data of the sense amplifier output node SALOUT. Apply "0" or "1" to. To this end, the light control unit 600 includes an NMOS transistor NM11 controlled by the light switching control signal WSW and an NMOS transistor NM12 controlled by the voltage of the sense amplifier output node SALOUT.

The operation of the write control unit 600 will be described in detail. First, when data "1" is written, when data "1" is loaded on the sense amplifier output node SALOUT, the NMOS transistor NM12 is turned on by the light switching X signal WSW. The NMOS transistor NM11 is turned on, and the half voltage Half_Vc is applied to the bit line BL_1 to write data "1" to the cell.

On the other hand, when data "0" is written, the NMOS transistor NM11 is turned on by the write control signal WSW, but since the data "0" is loaded on the sense amplifier output node SALOUT, the NMOS transistor NM12 is turned off and the bit line BL_1 is grounded. Data "0" is written because the voltage level is maintained.

8A is a timing diagram of a read operation of the sense amplifier of FIG. 7.

First, it is assumed that data stored in the memory cell Q1 shown in FIG. 2 is read for the read operation.

First, it is assumed that data stored in the memory cell Q1 shown in FIG. 2 is read for the read operation. When the cell Q1 connected to WL_1 is selected among the cell arrays connected to any bit line BL_1, the sensing current icell flows from the sense amplifier to the bit line BL_1. At this time, in the read mode, the write switching control signal WSW is disabled to a low level so that the NMOS transistor NM11 maintains a turn-off state.

The t0 section is defined as a precharge section of the memory cell. When the selection signals SEL_1 and SEL_2 are enabled to the high level in the t1 period, the switching elements N1 and N2 are turned on. Accordingly, the source terminal of the memory cell Q1 is connected to the bit line BL_1, and the drain terminal of the memory cell Qm is connected to the sensing line S / L_1. At this time, the plurality of word lines WL_1 to WL_m and the plurality of bottom word lines BWL_1 to BWL_m are kept low, and current flow between the bit line BL_1 and the sensing line S / L_1 is determined according to the storage polarity of the cell Q1. The above is illustrated in FIG. 9 as a description relating to the memory cell array of FIG.

At this time, the bit line precharge signal BLGND is enabled to a high level in the period t1 so that the NMOS transistors NM9 and NM10 are turned on to precharge the bit line BL_1 and the sense amplifier bar output node / SALOUT to the ground voltage level. In addition, the sense amplifier switching control signal SSW is enabled to the high level in the period t1 so that the NMOS transistor NM6 is turned on to apply the ground voltage level of the bit line BL_1 to the data latch input node SALIN. At this time, the write switching control signal WSW keeps the low level to turn off the NMOS transistor NM11.

Subsequently, the bottom word line BWL_1 of the selected cell is enabled to the high level in the period t2, the precharge control signal SAPRE is enabled to the low level, and the PMOS transistor PM2 is turned on to supply the data latch input node SALIN to the power supply voltage VDD level. Precharge Accordingly, the sensing voltage based on the power supply voltage VDD level is set in the bit line BL_1.

Next, in the period t3, the sense amplifier switching control signal SSW is disabled to the low level so that the NMOS transistor NM6 is turned off, and the voltage level of the bit line NL_1 maintains the voltage level set in the period t2 according to the cell sensing current icell. The developer drops to the ground voltage level.

That is, if the cell data is "0", the cell is in an on state, and the cell sensing current icell is a positive current. If the cell data is "1", the cell is off, and the cell sensing current icell is zero. Therefore, the cell with the cell data of "0" lowers the set voltage level of the bit line BL_1 to the ground voltage level, and the cell of the cell data of "1" maintains the voltage of the bit line BL_1 in the set voltage state. At this time, when the voltage level of the sense amplifier switching control signal SSW is 1.2V and the threshold voltage of the NMOS transistor NM6 is 0.7V, the voltage applied to the bit line BL_1 is 1.2V-0.7V = 0.5V.

After the bit line Bl_1 is sufficiently developed in the period t3, the sense amplifier precharge signal SAPRE is disabled to a high level, the PMOS transistor PM2 is turned off, and the sense amplifier switching control signal SSW is enabled to a high level. The MOS transistor NM6 is turned on. Accordingly, the voltage of the data latch input node SALIN is determined according to the state of the bit line BL_1. That is, the data latch input node SALIN maintains a high level without change when the bit line BL_1 is set to "1", but discharges to the ground voltage level when the bit line BL_1 is at the ground voltage level.

Meanwhile, in the period t5, the sense amplifier latch control signal SALAT is enabled at a high level, and the NMOS transistor NM8 is turned on. When the cell data is "0", the NMOS transistor NM7 is turned off and the ground voltage level is applied to the sense amplifier output node SALOUT. When the cell data is "1", the NMOS transistor NM4 is turned on to apply a high level signal to the sense amplifier output node SALOUT.

Thereafter, in the period t6, the bottom word line BWL_1 is disabled to the low level, the bit line precharge signal BLGND is enabled to the high level, and the bit line BL_1 is precharged to the ground voltage level.

8B is an operation timing diagram illustrating a high data write operation, a high data hold operation, and a low data write operation of the sense amplifier of FIG. 7.

First, it is assumed that the memory cell Q1 shown in FIG. 2 is selected during the write operation of data "1". The t0 section is defined as a precharge section of the memory cell, the t1 and t2 sections are sections for writing data "1" to the cell, and the t3 and t4 sections are sections for maintaining data "1", and t5 and t6. Is a section for writing data "0" to the cell.

In the t1 period, the bit line precharge control signal BLGND is enabled to a high level, thereby turning on the NMOS transistors NM9 and NM10 to precharge the bit line BL_1 and the sense amplifier bar output node / SALOUT to the ground voltage level. At this time, the plurality of word lines WL_2 to WL_m and the plurality of bottom word lines BWL_1 to BWL_m are kept low, and the sense amplifier switching control signal SSW, the sense amplifier precharge control signal SAPRE, and the sense amplifier latch control signal SALAT are always grounded. The read control unit 500 is turned off by disabling to the voltage level and turning off the NMOS transistors NM6, NM8 and PMOS transistor PM2.

In a period t2, a negative voltage VNEG is applied to the word line WL_1, and data "1" is written to the selected cell Q1. That is, a threshold voltage of Vc, which is a ferroelectric polarization switching voltage, is applied to the word line WL_1. If the voltage of the bit line BL_1 is the ground voltage level by the NMOS transistor NM9, the voltage Vc, which is a threshold voltage, is applied between the word line WL_1 and the channel to change the polarization of the ferroelectric to write data "1".

In the t3 period, the data "1" written by applying the ground voltage VSS to the word line WL_1 is maintained.

In the period t4, the bit line precharge control signal BLGND is disabled to the low level, the NMOS transistors NM9 and NM10 are turned off, and the light switching control signal WSW is enabled to the high level, so that the NMOS transistor NM11 is turned on and the sense amplifier output node is turned on. Data of SALOUT is transferred to the bit line BL_1. Since the NMOS transistor NM12 is turned on by the high data of the sense amplifier output node SALOUT, the half voltage Half_Vc is applied to the bit line BL_1 to apply a voltage smaller than the threshold voltage, thereby preserving the data "1" state.

At this time, when the data "1" loaded on the sense amplifier output node SALOUT is loaded, the NMOS transistor NM12 is turned on to apply the half voltage Half_Vc to the bit line BL_1 so that the high data is written to the selected cell, and the data loaded on the sense amplifier output node SALOUT. When " 0 " is loaded, the NMOS transistor NM12 is turned off, and the ground voltage level is applied to the bit line BL_1 to write low data in the cell.

Thereafter, the word line WL_1 is enabled at a high level in the period t5 to write the data of the bit line BL_1 to the cell connected to the word line WL_1. That is, if the data transferred to the bit line BL_1 is "0", "0" is written to the selected cell. If the data transferred to the bit line BL_1 is "1", the "1" is maintained in the selected cell.

In other words, electrons are accumulated in the P-type channel region of the memory cell Q1 by the word line WL_1. Thus, a positive voltage is applied to the word line WL_1 and a threshold voltage difference is generated so that the polarity is formed so that channel electrons are induced in the ferroelectric layer. Accordingly, data "0" can be written in the memory cell Q1. On the other hand, when the data "1" stored in the memory cell Q1 is to be kept as it is, a high voltage is applied to the bit line BL_1 so that the voltage of the bit line BL_1 is applied to the memory cell Q1. As a result, data "1" can be preserved by preventing the formation of electrons in the channel region.

Subsequently, in the period t6, the word line WL_1, the write switching control signal WSW, and all the bottom word lines BWL_1 to BWL_m transition to the ground voltage level again, and in the period t7, the bit line precharge control signal BLGND is enabled again at a high level. The bit line BL_1 is precharged to the ground voltage level to complete the write operation.

As described above, the sense amplifier according to the second embodiment of the present invention applies the threshold voltage of the ferroelectric polarization switching voltage Vc to the word line WL_1.

Accordingly, if the write data is "1", the bit line BL_1 transitions to the half voltage Half_Vc state, which is the threshold voltage intermediate value of the ferroelectric polarization switching voltage Vc, so that the half voltage Half_Vc, which is a voltage smaller than the threshold voltage between the word line WL_1 and the channel, It is applied to prevent the change in polarization of the ferroelectric to maintain high data.

On the other hand, if the write data is "0", the bit line BL_1 is brought to the ground voltage level, and the voltage Vc, which is a threshold voltage, is applied between the word line WL_1 and the channel to change the polarization of the ferroelectric, thereby writing the low data. Done.

9 is a flowchart illustrating a write operation process of the method of controlling the nonvolatile ferroelectric memory of the present invention having such a configuration.

First, data of all activated cells are sensed and amplified by the sense amplifier unit 30 (step S1). The data amplified through the sense amplifier unit 30 is stored in a register in the sense amplifier. S2) That is, before writing the data "1" to all the cells, the original cell data for the write-back operation is previously stored in the sense amplifier unit 30. Here, the write-back operation means writing original cell data back to the memory cell.

Thereafter, the data " 1 " is written to all activated cells. (Step S3)

Next, according to the output of the column decoding unit 60, the cells of the active area and the cells of the inactive area are distinguished and each other data is written (step S4).

That is, it is determined whether the column switches C / S_0 to C / S_n are activated. As shown in the write path of FIG. 10, when the corresponding column switch C / S_0 is activated, the switching elements N3 and N4 are turned on to sense new data applied from the data bus 50 by the sense amplifiers S / A0 and S. Print to / A1. Accordingly, data previously stored in the memory cell 20 is erased, and new data applied from the data bus 50 is written to the memory cell 20 through the bit lines BL_0 and BL_k (step S5).

On the other hand, as shown in the write-back path of FIG. 10, when the corresponding column switches C / S_1 to C / S_n are deactivated, the switching elements N5 to Nm are turned off. Thus, data already stored in the registers of the sense amplifiers S / A2 to S / Am is written back to the memory cell 20 (step S6).

11 illustrates a write operation of the method of controlling a nonvolatile ferroelectric memory according to the present invention.

The write operation cycle of the present invention can be divided into three sub operation regions. That is, in the first sub-operation region, data of all activated cells are amplified by the sense amplifier 30, and the amplified data is stored in a register in the sense amplifier 30.

In the second sub-operation area, data “1” is written to all activated cells. In the third sub-operation area, data "0" is written or data "1" is stored. If the data "1" is to be preserved, a high voltage is applied to the bit line BL in a predetermined period. Accordingly, the value of data " 1 " written in the second sub-operation area can be stored in the memory cell 20. FIG.

12 is a timing diagram of cell data sensing of a nonvolatile ferroelectric memory control method according to the present invention.

First, it is assumed that the memory cell Q1 shown in FIG. 2 is selected in the sensing operation of data. The t0 section is defined as a precharge section of the memory cell.

When the selection signals SEL_1 and SEL_2 transition high in the period t1, the switching elements N1 and N2 are turned on. Accordingly, the bit line BL_1 and the source terminal of the memory cell Q1 are connected, and the sensing line S / L_1 and the drain terminal of the memory cell Qm are connected.

In this case, the plurality of word lines WL_1 to WL_m and the plurality of bottom word lines BWL_1 to BWL_m remain low. The sense amplifier 30, the bit lines BL_1, and the sensing lines S / L_1 remain low.

Thereafter, the plurality of bottom word lines BWL_2 to BWL_m, except for the bottom word line BWL_1 connected to the selected memory cell Q1, transition high in the period t2. Accordingly, the remaining memory cells Q2 to Qm except the selected memory cell Q1 are connected to the sensing line S / L_1.

At this time, all of the plurality of word lines WL_1 to WL_m maintain the ground state. Accordingly, the flow of current between the bit line BL_1 and the sensing line S / L_1 is determined according to the polarity state formed in the memory cell Q1.

Subsequently, when the sense amplifier 30 operates in the period t3 and the sensing voltage is applied to the bit line BL_1, the current flow between the bit line BL_1 and the sensing line S / L_1 is determined according to the state of the memory cell Q1.

That is, when no current is applied to the bit line BL_1 from the sense amplifier 30, it can be seen that data “1” is stored in the memory cell Q1. On the other hand, when a current of a predetermined value or more is applied to the bit line BL_1 from the sense amplifier 30, it can be seen that data "0" is stored in the memory cell Q1.

Next, when the operation of the sense amplifier 30 is stopped in the period t4, the bit line BL_1 goes low to complete the sensing operation. In addition, the plurality of bottom word lines BWL_2 to BWL_m transition to low in a period t5. Thereafter, when the selection signals SEL_1 and SEL_2 transition low in the period t6, the switching elements N1 and N2 are turned off.

13 is a timing diagram of data "1" write operation of the nonvolatile ferroelectric memory control method according to the present invention.

First, it is assumed that the memory cell Q1 shown in FIG. 2 is selected during the write operation of data "1". The t0 section is defined as a precharge section of the memory cell.

When the selection signals SEL_1 and SEL_2 transition high in the period t1, the switching elements N1 and N2 are turned on. Accordingly, the bit line BL and the source terminal of the memory cell Q1 are connected, and the sensing line S / L_1 and the drain terminal of the memory cell Qm are connected.

In this case, the plurality of word lines WL_1 to WL_m and the plurality of bottom word lines BWL_1 to BWL_m remain low. The bit line BL_1 and the sensing line S / L_1 remain low.

Thereafter, the plurality of bottom word lines BWL_2 to BWL_m except for the bottom word line BWL_1 connected to the selected memory cell Q1 in the t2 section transition to high. As a result, the ground voltage <GND> is applied to the drain terminal and the source terminal of the memory cell Q1.

Next, a negative voltage VNEG is applied to the word line WL_1 connected to the selected memory cell Q1 in the period t3. In operation t4, the bottom word line BWL_1 is shifted high. As a result, a high voltage is applied to the ferroelectric layer 16 by voltage division between the word line WL_1 and the bottom word line BWL_1, thereby allowing data "1" to be written.

Subsequently, the word line WL_1 and the bottom word line BWL_1 transition to the ground state again in the period t5. In operation t6, the remaining bottom word lines BWL_2 to BWL_m transition to the ground state to complete the write operation. Thereafter, when the selection signals SEL_1 and SEL_2 transition low in the period t7, the switching elements N1 and N2 are turned off.

14 is an operation timing diagram relating to data "0" write operation and data "1" retention of the nonvolatile ferroelectric memory control method according to the present invention.

First, it is assumed that the memory cell Q1 shown in FIG. 2 is selected during the write operation of data "0". The t0 section is defined as a precharge section of the memory cell.

When the selection signal SEL_1 transitions high in the t1 period, the switching element N1 is turned on. Accordingly, the bit line BL_1 and the source terminal of the memory cell Q1 are connected.

At this time, the selection signal SEL_2, the plurality of word lines WL_1 to WL_m and the plurality of bottom word lines BWL_1 to BWL_m are kept low. The bit line BL_1 and the sensing line S / L_1 remain low.

Thereafter, all of the bottom word lines BWL_1 to BWL_m transition high in the period t2. Accordingly, all of the memory cells Q1 to Qm are connected to the bit line BL_1 through the bottom word lines BWL_1 to BWL_m so that data applied to the bit line BL_1 can be transferred to all the cells Q1 to Qm.

Next, when the data to be written to the memory cell Q1 is "0" in the period t3, the bit line BL_1 continues to maintain the ground voltage. On the other hand, when it is desired to hold data "1" stored in the memory cell Q1, the bit line BL_1 transitions high.

Subsequently, the word line WL_1 transitions high in the period t4. In this case, electrons are accumulated in the P-type channel region 12 of the memory cell Q1 by the word line WL_1. Accordingly, a positive voltage is applied to the word line WL_1 and a threshold voltage difference is generated so that polarity is formed so that channel electrons are induced in the ferroelectric layer 16. Accordingly, data "0" can be written in the memory cell Q1.

If the data "1" stored in the memory cell Q1 is to be kept as it is, a high voltage is applied to the bit line BL_1 so that the voltage of the bit line BL_1 is applied to the memory cell Q1. Accordingly, data "1" can be preserved by preventing electrons from being formed in the channel region 12.

Subsequently, the word line WL_1 transitions to the ground state again in the period t5. In addition, all of the bottom word lines BWL_1 to BWL_m and the bit line BL_1 transition to the ground state in the period t6 to complete the write operation. Thereafter, when the selection signal SEL_1 transitions low in the period t7, the switching element N1 is turned off.

In the present invention, the floating channel layer 15 is composed of an N-type drain region 13, a P-type channel region 12 and an N-type source region 14 in the embodiment, but the present invention is not limited thereto. The floating channel layer 15 may be formed of a P-type drain region, a P-type channel region, and a P-type source region.

In addition, the preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and modifications are the following patents It should be regarded as belonging to the claims.

As described above, the present invention does not destroy data of a cell during a read operation by using a non-destructive read out (NDRO) method. Accordingly, the present invention can improve the reliability of the cell and improve the read / write operation speed during the low voltage operation of the nanoscale ferroelectric cell. In addition, by implementing a plurality of ferroelectric unit cells in an array to improve the read / write operation method to enable a random access operation.

Claims (26)

A memory cell array in which switching operations are selectively controlled according to voltages applied to the plurality of word lines and the plurality of bottom word lines, and a plurality of unit cell arrays including a plurality of unit memory cells connected in series are provided in a row and column direction; A sense amplifier unit for sensing and amplifying data applied from the memory cell array and storing the amplified data; A column decoding unit decoding a column selection signal for selecting a memory cell; And A switching operation controlled according to an output of the column decoding unit, and having a column switching unit selectively connecting the sense amplifier unit and a data bus, Each of the plurality of unit memory cells includes a ferroelectric layer, and induces different channel resistances in a channel region according to the polarity of the ferroelectric layer to read / write data. The nonvolatile ferroelectric memory device of claim 1, wherein the activated unit memory cell of the plurality of unit memory cells is turned on by the column switching unit according to an output of the column decoding unit to write data applied from the data bus. . 3. The method of claim 1, wherein the deactivated unit memory cell of the plurality of unit memory cells is turned off according to an output of the column decoding unit so that data stored in the sense amplifier unit is written back. Nonvolatile ferroelectric memory device. The nonvolatile ferroelectric memory device of claim 1, wherein the column switching unit comprises a plurality of NMOS transistors connected between the sense amplifier and the data bus and whose gate terminals are connected to the column decoding unit. The method of claim 1, wherein each of the plurality of unit memory cells An insulation layer formed on the bottom word line; A floating channel layer formed on the insulating layer to maintain a floating state, and an N-type drain region and an N-type source region connected to both sides of the channel region; A ferroelectric layer formed on the channel region of the floating channel layer; And And a word line formed over the ferroelectric layer. The method of claim 1, wherein each of the plurality of unit memory cells An insulation layer formed on the bottom word line; A floating channel layer formed on the insulating layer and having a P-type channel region maintaining a floating state, and having a P-type drain region and a P-type source region connected to both sides of the channel region; A ferroelectric layer formed on the channel region of the floating channel layer; And And a word line formed over the ferroelectric layer. The method of claim 1, wherein each of the plurality of unit memory cells An insulation layer formed on the bottom word line; A floating channel layer formed on the insulating layer and having an N-type channel region maintaining a floating state, and an N-type drain region and an N-type source region connected to both sides of the channel region; A ferroelectric layer formed on the channel region of the floating channel layer; And And a word line formed over the ferroelectric layer. The method of claim 1, wherein each of the plurality of unit memory cells An insulation layer formed on the bottom word line; A floating channel layer formed on the insulating layer and having an N-type channel region maintaining a floating state, and a P-type drain region and a P-type source region connected to both sides of the channel region; A ferroelectric layer formed on the channel region of the floating channel layer; And And a word line formed over the ferroelectric layer. The method of any one of claims 5 to 8, wherein each of the plurality of unit memory cells A first switching element for selectively connecting a bit line and the plurality of unit memory cells according to a state of a first selection signal; And And a second switching element for selectively connecting the sensing line and the plurality of unit memory cells in accordance with the state of the second selection signal. The nonvolatile ferroelectric memory device of claim 9, wherein when the high data is written to the plurality of unit memory cells, the first switching element and the second switching element maintain a turn-on state. 12. The method of claim 10, wherein the selected unit memory cell of the plurality of unit memory cells, a positive voltage is applied to the bottom word line, a negative voltage is applied to the word line, the bit line and the sensing line Non-volatile ferroelectric memory device, characterized in that the ground voltage is applied. The nonvolatile ferroelectric memory device of claim 9, wherein when the row data is written to the plurality of memory cells, the first switching device is turned on and the second switching device is turned off. The method of claim 12, wherein the selected memory cell of the plurality of memory cells has a positive voltage applied to the bottom word line and the word line, and a ground voltage applied to the bit line and the sensing line. Volatile ferroelectric memory device. 10. The method of claim 9, wherein when the read operation of the plurality of memory cells, the ground voltage is applied to the bottom word line and the word line while the first switching element and the second switching element are turned on. Volatile ferroelectric memory device. The method of claim 1, wherein the memory cell array A plurality of bit lines arranged in a row direction and connected to the sense amplifier unit; A plurality of sensing lines arranged in a vertical direction with the plurality of bit lines; And And a plurality of unit memory cells arranged in a row and column direction in a region where the plurality of bit lines and the plurality of sensing lines intersect each other. The method of claim 1, wherein the sense amplifier unit, A bit line precharge unit for precharging the bit lines; A read controller configured to amplify and output data loaded on the bit line in a read mode after the bit line is precharged; And And a write control unit which transfers data input from the data bus to the bit line in the write mode after the bit line is precharged. The method of claim 16, wherein the bit line precharge unit, And a switching element controlled by a bit line precharge control signal to apply a ground voltage level to the bit line. The method of claim 16, wherein the lead control unit, Switching means controlled by a sense amplifier switching control signal activated in the read mode to apply data contained in the bit line to a data latch input node; Precharge means for applying a power supply voltage level to the data latch input node; And And amplifying means controlled by a signal of the data latch input node to amplify and output data loaded on the bit line. The method of claim 18, wherein the amplifying means, Data latch means for latching and amplifying data carried on the bit line; And And a data latch control means controlled by a signal of the data latch input node and controlled by a latch control signal activated in the read mode to apply a ground voltage level to an input terminal of the data latch means. Volatile ferroelectric memory device. The method of claim 16, wherein the light control unit, And a switching device controlled by a light switching control signal activated in the write mode to transfer data input from the data bus to the bit line. The method of claim 1, wherein the sense amplifier unit, A bit line precharge unit for precharging the bit line and the sense amplifier bar output node; A read control unit configured to amplify the data on the bit line and output the amplified data to the sense amplifier output node after the bit line and the sense amplifier bar output node are precharged; And And a write control unit configured to transfer a data value input from a data bus to the bit line in the write mode after the bit line and the sense amplifier bar output node are precharged. The method of claim 21, wherein the bit line precharge unit, A first switching element controlled by a bit line precharge control signal to apply a ground voltage level to the bit line; And And a second switching element controlled by the bit line precharge control signal to apply the ground voltage level to the sense amplifier bar output node. The method of claim 21, wherein the lead control unit, Switching means controlled by a sense amplifier switching control signal activated in the read mode to apply data contained in the bit line to a data latch input node; Precharge means for applying a power supply voltage level to the data latch input node; And And amplifying means controlled by a signal of the data latch input node to amplify and output data loaded on the bit line. The method of claim 23, wherein the amplifying means, Data latch means connected to an input / output terminal of a pair of sense amplifier output nodes, the latching and amplifying data carried on the bit line; And And a data latch control means controlled by a signal of the data latch input node and controlled by a latch control signal activated in the read mode to apply a ground voltage level to an input terminal of the data latch means. Volatile ferroelectric memory device. The method of claim 21, wherein the light control unit, A first switching element controlled by a light switching control signal activated in the write mode to transfer data input from the data bus to the bit line; And Controlled by the data value of the sense amplifier output node, if the write data applied from the data bus is " 1 " And a second switching device which is turned off when the write data is " 0 ". Sensing data stored in the memory cell by inducing different channel resistances in the channel region of the floating channel layer according to the polarity of the ferroelectric layer; Amplifying data of all activated memory cells through a sense amplifier and storing the amplified data in a register; Storing hidden data in all of the activated memory cells; And And writing the input data applied through the data bus to the selected memory cell according to whether the column selection signal is activated, and writing back the data stored in the register to the unselected memory cell. Ferroelectric memory control method.

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