KR20060075999A - Method for forming capacitor of semiconductor device - Google Patents

Method for forming capacitor of semiconductor device Download PDF

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KR20060075999A
KR20060075999A KR1020040115389A KR20040115389A KR20060075999A KR 20060075999 A KR20060075999 A KR 20060075999A KR 1020040115389 A KR1020040115389 A KR 1020040115389A KR 20040115389 A KR20040115389 A KR 20040115389A KR 20060075999 A KR20060075999 A KR 20060075999A
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dielectric
film
titanium
oxide film
depositing
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심규찬
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주식회사 하이닉스반도체
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal

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Abstract

본 발명은 반도체 소자의 캐패시터 형성방법에 관한 것으로, 특히 종래에 유전체로 사용되던 유전 상수가 20~25 정도의 산화하프늄막(HfO2)을 유전 상수가 70~80 정도의 산화티타늄막(TiO2)으로 대체시키고 누설 전류 특성 저하를 감소시키기 위하여 산화티타늄막의 두께를 60Å 이하로 유지함으로써 유전체의 유전 특성과 누설 전류 특성이 동시에 향상된 캐패시터를 얻을 수 있는 방법에 관한 것이다.The present invention relates to a capacitor formed in a semiconductor device, especially an oxide of a dielectric constant of between 20 and 25 conventionally used as a dielectric hafnium film (HfO 2) the dielectric constant of titanium oxide of about 70-80 layer (TiO 2 In order to reduce the leakage current characteristics and to reduce the leakage current characteristics, the method of the present invention relates to a method for obtaining a capacitor having improved dielectric properties and leakage current characteristics at the same time.

Description

반도체 소자의 캐패시터 형성방법{Method for Forming Capacitor of Semiconductor Device}Capacitor Formation Method of Semiconductor Device {Method for Forming Capacitor of Semiconductor Device}

도 1은 종래 기술에 따른 반도체 소자의 캐패시터 구조를 도시하는 단면도.1 is a cross-sectional view showing a capacitor structure of a semiconductor device according to the prior art.

도 2는 본 발명에 따른 반도체 소자의 캐패시터 구조를 도시하는 단면도.2 is a cross-sectional view showing a capacitor structure of a semiconductor device according to the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

10, 100 : 하부 전극 12 : 산화하프늄막10, 100: lower electrode 12: hafnium oxide film

14 : 산화알루미늄막 30, 130 : 상부 전극14: aluminum oxide film 30, 130: upper electrode

112 : 제1 유전체 114 : 제2 유전체112: first dielectric 114: second dielectric

116 : 제3 유전체 118 : 제4 유전체116: third dielectric 118: fourth dielectric

120 : 제5 유전체120: fifth dielectric

본 발명은 반도체 소자의 캐패시터 형성방법에 관한 것으로, 더욱 상세하게는 유전물질을 적층함으로써 유전 상수(dielectric constant)와 누설 전류(leakage current) 특성을 동시에 향상시킬 수 있는 캐패시터 형성방법에 관한 것이다.The present invention relates to a method of forming a capacitor of a semiconductor device, and more particularly, to a method of forming a capacitor capable of simultaneously improving dielectric constant and leakage current characteristics by stacking a dielectric material.

전하를 저장하는 저장소로 사용되는 캐패시터는 양쪽에 각각 하부 전극 및 상부 전극이라는 금속성 물질과, 상부전극과 하부전극의 사이에 놓여 있는 유전체로 구성되어 있다.The capacitor used as the storage for storing the charge is composed of a metallic material called a lower electrode and an upper electrode on both sides, and a dielectric placed between the upper electrode and the lower electrode, respectively.

일반적으로 캐패시터의 정전용량(capacitance)은 다음의 식으로 표현된다.In general, the capacitance of a capacitor is expressed by the following equation.

Figure 112004062490649-PAT00001
Figure 112004062490649-PAT00001

상기 식에서, C는 캐패시턴스, ε는 유전 상수, A는 전극 면적, d는 하부 전극과 상부 전극간의 거리를 나타낸다.Where C is the capacitance, ε is the dielectric constant, A is the electrode area, and d is the distance between the lower and upper electrodes.

디램(Dynamic Random Access Memory) 소자의 리프레쉬 특성을 향상시키기 위해서는 정전용량 값이 높아야 한다. 이러한 정전 용량을 높이기 위해서는 상기 식으로부터 알 수 있는 바와 같이, 전극 면적이 커야 하고 양 전극 사이의 거리는 작아야 한다. 또한 유전 상수가 높은 물질을 사용함으로써 유전 상수를 향상시킬 수 있다.In order to improve refresh characteristics of DRAM devices, capacitance values must be high. In order to increase this capacitance, as can be seen from the above equation, the electrode area should be large and the distance between both electrodes should be small. In addition, it is possible to improve the dielectric constant by using a material having a high dielectric constant.

도 1을 참조하면, 종래의 캐패시터는 각각 200Å 두께의 티타늄 나이트라이드막(TiN)으로 이루어진 하부 전극(10)과 상부 전극(30)의 사이에 약 100Å 두께의 산화하프늄막(HfO2)(14)과 약 60Å 두께의 산화알루미늄막(Al2O3)(12)의 적층막으로 이루어진 유전체가 놓여 있는 구조를 갖는다.Referring to FIG. 1, a conventional capacitor has a hafnium oxide film (HfO 2 ) 14 having a thickness of about 100 GPa between a lower electrode 10 and an upper electrode 30 each having a titanium nitride film TiN having a thickness of 200 μs. ) And a dielectric film composed of a laminated film of an aluminum oxide film (Al 2 O 3 ) 12 having a thickness of about 60 kHz.

이때, 유전체를 산화하프늄막(14)으로만 구성할 경우 유전 상수는 높지만 누설 전류가 높아서 전하를 캐패시터 내에 오랫동안 유지시킬 수 없고, 유전체를 산화알루미늄막(12)으로만 구성할 경우 누설 전류는 낮아서 캐패시터에서 빠져 나가는 전하는 적지만 유전 상수가 낮아서 많은 전하를 캐패시터 내에 유지시킬 수 없 다는 단점이 있다. 따라서, 이를 보완하기 위해 도입된 것이 산화하프늄막(14)과 산화알루미늄막(12)을 적층하는 것으로서 근래, 양산에 적용되고 있는 유전체는 유전 상수를 높이기 위한 산화하프늄막(14)과 누설 전류를 줄이기 위하여 산화알루미늄막(12)의 적층 구조로 되어 있는 것이다.At this time, when the dielectric is composed of only the hafnium oxide film 14, the dielectric constant is high, but the leakage current is high, so that charge cannot be maintained in the capacitor for a long time. Although the charge leaving the capacitor is small, the low dielectric constant has the disadvantage that many charges cannot be maintained in the capacitor. Therefore, the hafnium oxide film 14 and the aluminum oxide film 12 that are introduced to compensate for this are laminated, and in recent years, dielectrics applied to mass production have been developed to improve the dielectric constant of the hafnium oxide film 14 and the leakage current. In order to reduce, the aluminum oxide film 12 is laminated.

상기 산화하프늄막(14)은 유전 상수가 20~25로서, 그 두께가 50Å 보다 클 경우에 박막이 결정화(crystallization)된다. 결정화가 이루어지면 결정립(grain)과 결정립 사이에 결정립계(grain boundary)가 형성되기 때문에 이를 통해 누설 전류가 흐르게 되어 전하를 저장하는 리프레쉬 특성이 저하하게 되는 문제점이 있다.The hafnium oxide film 14 has a dielectric constant of 20 to 25, and the thin film is crystallized when its thickness is larger than 50 GPa. When crystallization is performed, a grain boundary is formed between the grains and the grains, so that leakage current flows through the grains, thereby degrading the refresh characteristic of storing charge.

본 발명은 상기 종래기술의 문제점을 해결하기 위한 것으로, 캐패시터를 구성하는 유전체의 유전 특성과 누설 전류 특성을 동시에 향상시키기 위하여 유전 상수가 20~25 정도인 산화하프늄막을 유전 상수가 70~80 정도인 산화티타늄막(TiO2)으로 대체시키고 누설 전류 특성 저하를 감소시키기 위하여 산화티타늄막의 두께를 60Å 이하로 유지하여 결정화를 방지할 수 있는 반도체 소자의 캐패시터 형성방법을 제공하는 것을 목적으로 한다.The present invention is to solve the problems of the prior art, in order to improve the dielectric properties and leakage current characteristics of the dielectric constituting the capacitor at the same time, the dielectric constant of about 70 ~ 80 hafnium oxide film An object of the present invention is to provide a method for forming a capacitor of a semiconductor device capable of preventing crystallization by keeping the thickness of the titanium oxide film below 60 kW in order to replace the titanium oxide film (TiO 2 ) and to reduce the leakage current characteristics.

상기 목적을 달성하기 위하여 본 발명에서는 하기의 단계를 포함하는 반도체 소자의 캐패시터 형성방법을 제공한다:In order to achieve the above object, the present invention provides a method of forming a capacitor of a semiconductor device comprising the following steps:

(a) 티타늄 나이트라이드막(TiN)을 증착하여 하부 전극을 형성하는 단계; (a) depositing a titanium nitride film (TiN) to form a lower electrode;                     

(b) 상기 하부 전극 상부에 산화티타늄막(TiO2), BST막(바륨-스트론튬-티타늄) 및 PZT막(납-지르코늄-티타늄)으로 이루어진 군으로부터 선택되는 막을 증착하여 제1 유전체를 형성하는 단계;(b) depositing a film selected from the group consisting of a titanium oxide film (TiO 2 ), a BST film (barium-strontium-titanium), and a PZT film (lead-zirconium-titanium) on the lower electrode to form a first dielectric step;

(c) 상기 제1 유전체 상부에 산화알루미늄막(Al2O3), 질화실리콘막(Si3N 4), 산화니오브막(NbO2) 및 산화실리콘막(SiO2)으로 이루어진 군으로부터 선택되는 막을 증착하여 제2 유전체를 형성하는 단계;(c) an aluminum oxide film (Al 2 O 3 ), a silicon nitride film (Si 3 N 4 ), a niobium oxide film (NbO 2 ), and a silicon oxide film (SiO 2 ) on the first dielectric layer. Depositing a film to form a second dielectric;

(d) 상기 제2 유전체 상부에 산화티타늄막(TiO2), BST막(바륨-스트론튬-티타늄) 및 PZT막(납-지르코늄-티타늄)으로 이루어진 군으로부터 선택되는 막을 증착하여 제3 유전체를 형성하는 단계;(d) depositing a film selected from the group consisting of a titanium oxide film (TiO 2 ), a BST film (barium-strontium-titanium), and a PZT film (lead-zirconium-titanium) on the second dielectric to form a third dielectric Making;

(e) 상기 제3 유전체 상부에 산화알루미늄막(Al2O3), 질화실리콘막(Si3N 4), 산화니오브막(NbO2) 및 산화실리콘막(SiO2)으로 이루어진 군으로부터 선택되는 막을 증착하여 제4 유전체를 형성하는 단계;(e) selected from the group consisting of an aluminum oxide film (Al 2 O 3 ), a silicon nitride film (Si 3 N 4 ), a niobium oxide film (NbO 2 ), and a silicon oxide film (SiO 2 ) over the third dielectric layer; Depositing a film to form a fourth dielectric;

(f) 상기 제4 유전체 상부에 산화티타늄막(TiO2), BST막(바륨-스트론튬-티타늄) 및 PZT막(납-지르코늄-티타늄)으로 이루어진 군으로부터 선택되는 막을 증착하여 제5 유전체를 형성하는 단계; 및(f) depositing a film selected from the group consisting of a titanium oxide film (TiO 2 ), a BST film (barium-strontium-titanium), and a PZT film (lead-zirconium-titanium) on the fourth dielectric to form a fifth dielectric. Making; And

(g) 상기 제5 유전체 상부에 티타늄 나이트라이드막(TiN)을 증착하여 상부 전극을 형성하는 단계.(g) depositing a titanium nitride film (TiN) on the fifth dielectric to form an upper electrode.

또한, 본 발명에서는 상기 방법에 의해 제조되는 것으로 하기의 구조를 포함 하는 반도체 소자의 캐패시터를 제공한다.In addition, the present invention provides a capacitor of a semiconductor device which is manufactured by the above method and includes the following structure.

이하, 첨부된 도면을 참고로 하여 본 발명의 실시예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명에 따른 반도체 소자의 캐패시터 구조를 도시하는 단면도로서, 이를 참조하면 먼저 티타늄 나이트라이드막(TiN)을 190Å∼210Å, 바람직하게는 200Å의 두께로 증착하여 하부 전극(100)을 형성한다.2 is a cross-sectional view showing a capacitor structure of a semiconductor device according to the present invention. Referring to this, first, a titanium nitride film (TiN) is deposited to a thickness of 190 kPa to 210 kPa, preferably 200 kPa to form a lower electrode 100. do.

다음, 하부 전극(100) 상부에 산화티타늄막(TiO2), BST막(바륨-스트론튬-티타늄) 또는 PZT막(납-지르코늄-티타늄)으로 이루어진 군으로부터 선택되는 막을 20Å∼60Å, 바람직하게는 산화티타늄막(TiO2)을 50Å의 두께로 증착하여 제1 유전체 (112)를 형성한다.Next, a film selected from the group consisting of a titanium oxide film (TiO 2 ), a BST film (barium-strontium-titanium), or a PZT film (lead-zirconium-titanium) on the lower electrode 100 is preferably 20 kPa to 60 kPa. A titanium oxide film (TiO 2 ) is deposited to a thickness of 50 GPa to form a first dielectric 112.

다음, 제1 유전체 상부(112)에 산화알루미늄막(Al2O3), 질화실리콘막(Si3N 4), 산화니오브막(NbO2) 또는 산화실리콘막(SiO2)으로 이루어진 군으로부터 선택되는 막을 3Å∼10Å, 바람직하게는 산화알루미늄막(Al2O3)을 5Å의 두께로 증착하여 제2 유전체(114)를 형성한다.Next, an aluminum oxide film (Al 2 O 3 ), a silicon nitride film (Si 3 N 4 ), a niobium oxide film (NbO 2 ), or a silicon oxide film (SiO 2 ) is selected on the first dielectric layer 112. The second dielectric 114 is formed by depositing a 3 to 10 GPa film, preferably an aluminum oxide film (Al 2 O 3 ) to a thickness of 5 GPa.

다음, 제2 유전체(114) 상부에 산화티타늄막(TiO2), BST막(바륨-스트론튬-티타늄) 또는 PZT막(납-지르코늄-티타늄)으로 이루어진 군으로부터 선택되는 막을 20Å∼60Å, 바람직하게는 산화티타늄막(TiO2)을 50Å의 두께로 증착하여 제3 유전체 (116)를 형성한다. Next, a film selected from the group consisting of a titanium oxide film (TiO 2 ), a BST film (barium-strontium-titanium), or a PZT film (lead-zirconium-titanium) over the second dielectric 114 is preferably 20 kPa to 60 kPa. Deposits a titanium oxide film (TiO 2 ) to a thickness of 50 GPa to form a third dielectric 116.

다음, 제3 유전체 상부(116)에 산화알루미늄막(Al2O3), 질화실리콘막(Si3N 4), 산화니오브막(NbO2) 또는 산화실리콘막(SiO2)으로 이루어진 군으로부터 선택되는 막을 3Å∼10Å, 바람직하게는 산화알루미늄막(Al2O3)을 5Å의 두께로 증착하여 제4 유전체(118)를 형성한다.Next, an aluminum oxide film (Al 2 O 3 ), a silicon nitride film (Si 3 N 4 ), a niobium oxide film (NbO 2 ), or a silicon oxide film (SiO 2 ) is selected on the third dielectric upper portion 116. The fourth dielectric 118 is formed by depositing a film of 3 to 10 Å, preferably aluminum oxide (Al 2 O 3 ) to a thickness of 5 Å.

다음, 제4 유전체(118) 상부에 산화티타늄막(TiO2), BST막(바륨-스트론튬-티타늄) 또는 PZT막(납-지르코늄-티타늄)으로 이루어진 군으로부터 선택되는 막을 20Å∼60Å, 바람직하게는 산화티타늄막(TiO2)을 50Å의 두께로 증착하여 제5 유전체 (120)를 형성한다.Next, a film selected from the group consisting of a titanium oxide film (TiO 2 ), a BST film (barium-strontium-titanium), or a PZT film (lead-zirconium-titanium) on the fourth dielectric 118 is preferably 20 kPa to 60 kPa. Deposits a titanium oxide film (TiO 2 ) to a thickness of 50 GPa to form a fifth dielectric (120).

다음, 제5 유전체(120) 상부에 티타늄 나이트라이드막(TiN)을 190Å∼210Å, 바람직하게는 200Å의 두께로 증착하여 상부 전극(130)을 형성한다.Next, a titanium nitride film TiN is deposited on the fifth dielectric 120 to a thickness of 190 kV to 210 kPa, preferably 200 kPa to form the upper electrode 130.

이상의 하부 전극(100), 유전체(112,114,116,118,120) 및 상부 전극(130)은 원자층단위 증착법(Atomic Layer Deposition)에 의해 형성되는 것이 바람직하다. The lower electrode 100, the dielectrics 112, 114, 116, 118, 120, and the upper electrode 130 are preferably formed by atomic layer deposition.

또한, 산화물로 이루어지는 각각의 유전체(112,114,116,118,120)는 산화원 (oxidant)으로 산소(O2), 일산화이질소(N2O) 및 일산화일질소(NO) 가스로부터 선택되는 하나 이상의 가스를 이용하는 것이 바람직하고, 아울러 플라즈마를 이용하여 형성되는 것이 바람직하다.In addition, each of the dielectrics 112, 114, 116, 118, and 120 made of an oxide preferably uses at least one gas selected from oxygen (O 2 ), dinitrogen monoxide (N 2 O), and nitrogen monoxide (NO) gas as an oxidant. In addition, it is preferable to form using a plasma.

또한, 각 하부 전극(100), 유전체(112,114,116,118,120) 및 상부 전극(130)을 증착하는 공정의 중간 또는 증착 공정을 완료한 후에는 수소(H2), 아르곤(Ar) 및 산소(O2) 가스로부터 선택되는 하나 이상의 분위기에서 열처리하는 공정을 더 수행하는 것이 바람직하다.In addition, after completion of the intermediate or deposition process of depositing each of the lower electrode 100, the dielectrics 112, 114, 116, 118, 120 and the upper electrode 130, hydrogen (H 2 ), argon (Ar) and oxygen (O 2 ) gas. It is preferable to carry out the process of heat treatment in at least one atmosphere selected from.

본 발명에서는 또한 상기한 방법에 의해 제조되는 적층 구조의 유전체를 포함함으로써 유전체의 유전 특성과 누설 전류 특성을 동시에 향상된 캐패시터를 제공한다.The present invention also provides a capacitor in which the dielectric and leakage current characteristics of the dielectric are improved at the same time by including the dielectric of the laminated structure produced by the above method.

종래의 유전체 물질로 사용되는 산화하프늄의 경우 유전 상수가 20∼25인데 반해, 본 발명에서 사용하는 제1 유전체(112), 제3 유전체(116) 및 제5 유전체 (120)을 구성하는 산화티타늄은 유전 상수가 70∼80 정도로 산화하프늄의 약 3∼4배가 높은 수치이다. 또한, 산화하프늄막의 경우 박막 두께가 100Å 정도로서 그 두께가 60Å 이상이기 때문에 박막이 결정화되고 그 결과, 결정립과 결정립 사이에 결정립계가 형성되기 때문에 이를 통해 누설 전류가 흐르게 되어 전하를 저장하는 리프레쉬 특성이 저하하게 된다.In the case of hafnium oxide used as a conventional dielectric material, the dielectric constant is 20 to 25, whereas titanium oxide constituting the first dielectric 112, the third dielectric 116 and the fifth dielectric 120 used in the present invention. The dielectric constant is 70 to 80, about 3 to 4 times higher than hafnium oxide. In the case of the hafnium oxide film, since the thin film is about 100 GPa and the thickness is 60 GPa or more, the thin film is crystallized, and as a result, a grain boundary is formed between the grains and the grains, so that a leakage current flows through it, thereby reducing the refresh characteristics of storing charge. Done.

그러나 본 발명에서는 제1 유전체(112), 제3 유전체(116) 및 제5 유전체 (120)을 구성하는 산화티타늄막의 두께가 제2 유전체(114) 및 제4 유전체(118)를 구성하는 산화알루미늄 박막에 의해 50Å 정도로 제한된다. 따라서 결정화가 일어나지 않고 비정질(amorphous) 상태로 유지되기 때문에 결정립계가 형성되지 않아 결정립계를 통한 누설전류 특성 저하는 일어나지 않는다. 본 발명에서 제2 유전체 (114)및 제4 유전체(118)의 두께를 종래의 60Å 정도에서 5Å 정도로 감소시킨 이유는 5Å의 두께만으로도 누설 전류를 막을 수 있기 때문이다. However, in the present invention, the thickness of the titanium oxide film constituting the first dielectric 112, the third dielectric 116, and the fifth dielectric 120 is the aluminum oxide constituting the second dielectric 114 and the fourth dielectric 118. The film thickness is limited to about 50 microseconds. Therefore, since crystallization does not occur and remains in an amorphous state, grain boundaries are not formed and thus leakage current characteristics through the grain boundaries do not occur. In the present invention, the reason why the thickness of the second dielectric 114 and the fourth dielectric 118 is reduced from about 60 mA to about 5 mA is because a leakage current can be prevented even with a thickness of 5 mA.                     

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

이상에서 설명한 바와 같이, 본 발명에서는 유전 상수가 20~25 정도인 산화하프늄막을 유전 상수가 70~80 정도인 산화티타늄막(TiO2)으로 대체시키고 누설 전류 특성 저하를 감소시키기 위하여 산화티타늄막의 두께를 60Å 이하로 유지함으로써 결정화를 방지할 수 있어 유전체의 유전 특성과 누설 전류 특성을 동시에 향상된 캐패시터를 얻을 수 있다.As described above, in the present invention, the thickness of the titanium oxide film in order to replace the hafnium oxide film having a dielectric constant of about 20 to 25 with the titanium oxide film (TiO 2 ) having a dielectric constant of about 70 to 80 and to reduce leakage current characteristics The crystallization can be prevented by maintaining ≤ 60 mA, so that a capacitor having improved dielectric and leakage current characteristics of the dielectric can be obtained at the same time.

Claims (9)

(a) 티타늄 나이트라이드막(TiN)을 증착하여 하부 전극을 형성하는 단계;(a) depositing a titanium nitride film (TiN) to form a lower electrode; (b) 상기 하부 전극 상부에 산화티타늄막(TiO2), BST막(바륨-스트론튬-티타늄) 및 PZT막(납-지르코늄-티타늄)으로 이루어진 군으로부터 선택되는 막을 증착하여 제1 유전체를 형성하는 단계;(b) depositing a film selected from the group consisting of a titanium oxide film (TiO 2 ), a BST film (barium-strontium-titanium), and a PZT film (lead-zirconium-titanium) on the lower electrode to form a first dielectric step; (c) 상기 제1 유전체 상부에 산화알루미늄막(Al2O3), 질화실리콘막(Si3N 4), 산화니오브막(NbO2) 및 산화실리콘막(SiO2)으로 이루어진 군으로부터 선택되는 막을 증착하여 제2 유전체를 형성하는 단계;(c) an aluminum oxide film (Al 2 O 3 ), a silicon nitride film (Si 3 N 4 ), a niobium oxide film (NbO 2 ), and a silicon oxide film (SiO 2 ) on the first dielectric layer. Depositing a film to form a second dielectric; (d) 상기 제2 유전체 상부에 산화티타늄막(TiO2), BST막(바륨-스트론튬-티타늄) 및 PZT막(납-지르코늄-티타늄)으로 이루어진 군으로부터 선택되는 막을 증착하여 제3 유전체를 형성하는 단계;(d) depositing a film selected from the group consisting of a titanium oxide film (TiO 2 ), a BST film (barium-strontium-titanium), and a PZT film (lead-zirconium-titanium) on the second dielectric to form a third dielectric Making; (e) 상기 제3 유전체 상부에 산화알루미늄막(Al2O3), 질화실리콘막(Si3N 4), 산화니오브막(NbO2) 및 산화실리콘막(SiO2)으로 이루어진 군으로부터 선택되는 막을 증착하여 제4 유전체를 형성하는 단계;(e) selected from the group consisting of an aluminum oxide film (Al 2 O 3 ), a silicon nitride film (Si 3 N 4 ), a niobium oxide film (NbO 2 ), and a silicon oxide film (SiO 2 ) over the third dielectric layer; Depositing a film to form a fourth dielectric; (f) 상기 제4 유전체 상부에 산화티타늄막(TiO2), BST막(바륨-스트론튬-티타늄) 및 PZT막(납-지르코늄-티타늄)으로 이루어진 군으로부터 선택되는 막을 증착하여 제5 유전체를 형성하는 단계; 및(f) depositing a film selected from the group consisting of a titanium oxide film (TiO 2 ), a BST film (barium-strontium-titanium), and a PZT film (lead-zirconium-titanium) on the fourth dielectric to form a fifth dielectric. Making; And (g) 상기 제5 유전체 상부에 티타늄 나이트라이드막(TiN)을 증착하여 상부 전극을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법.and (g) depositing a titanium nitride film (TiN) on the fifth dielectric to form an upper electrode. 제 1 항에 있어서,The method of claim 1, 상기 하부 전극 및 상부 전극의 두께는 190Å∼210Å인 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법.And the thickness of the lower electrode and the upper electrode is 190 kPa to 210 kPa. 제 1 항에 있어서,The method of claim 1, 상기 제1 유전체, 제3 유전체 및 제5 유전체의 두께는 20Å∼60Å인 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법.And the thicknesses of the first dielectric, the third dielectric, and the fifth dielectric are 20 k? To 60 k ?. 제 1 항에 있어서,The method of claim 1, 상기 제2 유전체 및 제4 유전체의 두께는 3Å∼10Å인 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법.And a thickness of said second dielectric material and said fourth dielectric material is 3 k? To 10 k ?. 제 1 항에 있어서,The method of claim 1, 상기 하부 전극, 유전체 및 상부 전극은 원자층단위 증착법(Atomic Layer Deposition)에 의해 형성되는 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법.The lower electrode, the dielectric and the upper electrode is a capacitor forming method of the semiconductor device, characterized in that formed by atomic layer deposition (Atomic Layer Deposition) method. 제 1 항에 있어서,The method of claim 1, 상기 유전체는 산화원(oxidant)으로 산소(O2), 일산화이질소(N2O) 및 일산화일질소(NO) 가스로부터 선택되는 하나 이상의 가스를 이용하여 형성되는 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법.The dielectric is formed using at least one gas selected from oxygen (O 2 ), dinitrogen monoxide (N 2 O) and nitrogen monoxide (NO) gas as an oxidant. Way. 제 1 항에 있어서,The method of claim 1, 상기 유전체는 플라즈마를 이용하여 형성되는 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법.And the dielectric material is formed using plasma. 제 1 항에 있어서,The method of claim 1, 상기 방법은 각 단계의 중간 또는 완료 후에, 수소(H2), 아르곤(Ar) 및 산소(O2) 가스로부터 선택되는 하나 이상의 분위기에서 열처리하는 공정을 더 수행하는 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법.The method further comprises performing a heat treatment in one or more atmospheres selected from hydrogen (H 2 ), argon (Ar), and oxygen (O 2 ) gas after each step is completed or completed. Formation method. 제 1 항에 기재된 방법에 의해 제조되는 것을 특징으로 하는 반도체 소자의 캐패시터.It is manufactured by the method of Claim 1, The capacitor of the semiconductor element characterized by the above-mentioned.
KR1020040115389A 2004-12-29 2004-12-29 Method for forming capacitor of semiconductor device KR20060075999A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7763953B2 (en) * 2007-03-14 2010-07-27 Elpida Memory, Inc. Semiconductor device and method of manufacturing the same
KR100984075B1 (en) * 2009-10-09 2010-09-28 삼성탈레스 주식회사 Variable band pass filter and configuring method therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7763953B2 (en) * 2007-03-14 2010-07-27 Elpida Memory, Inc. Semiconductor device and method of manufacturing the same
KR100984075B1 (en) * 2009-10-09 2010-09-28 삼성탈레스 주식회사 Variable band pass filter and configuring method therefor

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