KR20060075691A - Method for inspecting a defect - Google Patents

Abstract

According to a defect inspection method capable of effectively inspecting defects, the microstructures formed on the semiconductor substrate are partitioned by region, and then the semiconductor substrate is scanned to obtain image data about the microstructures. Defects on the semiconductor substrate are detected from the image data, and the detected defects are classified by regions. In this case, the detected defects are given area identification codes containing area information in which each defect exists. The defects are classified based on the area identifiers assigned to each defect. Therefore, the defects on the semiconductor substrate can be classified and inspected for each region. As a result, the efficiency of the inspection process can be maximized, and finally, a precise semiconductor device can be manufactured.

Description

How to check for defects {METHOD FOR INSPECTING A DEFECT}

1 is a flowchart illustrating a defect inspection method according to an embodiment of the present invention.

2 is a conceptual diagram illustrating a region partitioning method for a non-memory chip.

3 is a conceptual diagram illustrating a region partitioning method for a non-memory chip.

4 is a diagram illustrating an example of a defect detection result of the non-memory chip of FIG. 1.

FIG. 5 is a schematic diagram illustrating a first map in which the defect classification result of FIG. 1 is not filtered for each region.

FIG. 6 is a schematic diagram illustrating a second map in which only defects existing in a specific area of the first map of FIG. 5 are filtered.

FIG. 7 illustrates a trend graph for explaining a defect classification result of FIG. 1.

<Explanation of symbols for the main parts of the drawings>

111: first SRAM area 112: second SRAM area

113: LOGIC area 114: F-MEMORY area

122: cell area 124: other area

122: cell area 124: other area                 

230, 341, 342, 343, 344: defective

231 ： Coordinate information 233 ： Size information

235 ： Area information 237 ： Grade information

239: Area information 300: The first map

400: Second map D1, D2: Die

The present invention relates to a defect inspection method. More specifically, the present invention relates to a method of detecting defects from the results of scanning microstructures formed on a semiconductor substrate and inspecting the detected defects.

Current research on semiconductor devices is progressing toward high integration and high performance in order to process more data in a short time. In order to achieve high integration and high performance of the semiconductor device, it is very important to accurately form microstructures such as circuit patterns on the semiconductor substrate. In addition, an inspection process for determining whether the microstructures are accurately formed on the semiconductor substrate is essential.

On the semiconductor substrate, there are repeat regions where the microstructures are repeatedly formed and non-repeat regions where the microstructures are formed repeatedly. For example, in the case of a memory chip, a ferry in which 60 to 70% of cells are repeatedly formed in one die and 30 to 40% of non-repetitively formed ferries are formed. (peri), sense amplifier (S / A), sub-word divider (SWD), and the like. In the case of a non-memory chip or a system on chip (hereinafter referred to as 'SOC'), an SRAM, a DRAM, a logic, a flash memory, and the like are non-repetitively formed. . Among them, cells are repeatedly formed in each of an SRAM area, a DRAM area, and a flash memory area. That is, both the memory chip and the non-memory chip have regions in which microstructures are repeatedly formed and regions in which they are not repeatedly formed.

However, conventionally, many problems have been caused by performing a defect inspection process without dividing a semiconductor substrate into a repeating region and a non-repeating region. Even the same defects may be ignored depending on the area where they exist, or may cause serious problems. In more detail, even the same defect is not a serious problem in a memory chip in which cells are repeatedly formed, but in a logic of a non-memory chip, it may cause a serious problem of discarding the chip. Therefore, it is necessary to classify the detected defects by area and take action on them, but the current defect inspection method does not satisfy this.

Therefore, in light of the current research on semiconductor devices, this is a problem that must be solved.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to provide a method for effectively inspecting defects present on a semiconductor substrate.

According to an embodiment of the present invention to achieve the above object of the present invention, after dividing the microstructures formed on the semiconductor substrate for each region, to obtain the image data for the microstructures by scanning the semiconductor substrate . Defects on the semiconductor substrate are detected from the image data, and the detected defects are classified by regions. In this case, the semiconductor substrate is divided into a repeating region in which microstructures are repeatedly formed for each die and a non-repeatment region in which the microstructures are non-repetitively formed. The repeating region is one of an SRAM (SRAM) region, a DRAM (DRAM) region, and a flash memory (FASHION region). The non-repeatable area is a logic (LOGIC) area. The detected defects include area data in which the defects are located, and classify the defects based on the area data.

According to the present invention, defects on a semiconductor substrate may be classified and inspected for each region. Therefore, the efficiency of the inspection process can be maximized, and finally, a precise semiconductor device can be manufactured.

Hereinafter, a defect inspection method according to a preferred embodiment of the present invention with reference to the accompanying drawings in detail, but the present invention is not limited or limited by the following examples.                     

FIG. 1 is a flowchart illustrating a defect inspection method according to an exemplary embodiment of the present invention, FIG. 2 is a conceptual diagram illustrating a region partitioning method for a non-memory chip, and FIG. A conceptual diagram for explaining a region partitioning method for a chip is shown.

1 and 3, a semiconductor substrate on which microstructures are formed is prepared (S110). In this case, microstructures for memory or non-memory may be repeatedly or non-repetitively formed on the semiconductor substrate.

Subsequently, the semiconductor substrate is loaded into the defect detection apparatus (S120). An inspection range for the loaded semiconductor substrate is set (S130). The inspection range is set by dividing the microstructures formed on the semiconductor substrate for each region (S132). In this case, the microstructures are divided into regions in which the microstructures are repeatedly formed and regions that are not repeatedly formed.

As shown in FIG. 2, in the case of a non-memory chip or an SOC, SRAM, LOGIC, F-MEMORY, etc. are non-repetitively formed in one die D1 on a semiconductor substrate. In this case, the microstructures are repeatedly formed in the SRAM regions 111 and 112 and the F-MEMORY region 114, but the microstructures are non-repetitively formed in the LOGIC region 113. Even in the SRAM region 111 and the F-MEMORY region 114, the microstructures are repeatedly formed in different trends. Therefore, it is preferable to divide the microstructures on the semiconductor substrate into the first SRAM region 111, the second SRAM region 112, the LOGIC region 113, and the F-MEMORY region 114.                     

As shown in FIG. 3, in the case of the memory chip, cells are repeatedly formed in about 60 to 70% of one die D2 on the semiconductor substrate, and the remaining 30 to 40% are peri, A sense amplifier (S / A), a sub-word divider (SWD), and the like are formed non-repetitively. Therefore, it is desirable to partition the microstructures on the semiconductor substrate into the cell region 122 and the other region 124.

As described above, when the area partition for the microstructures is completed (S132), a recipe of the defect detection apparatus is set corresponding to the partitioned area (S134). The recipe setting S134 is for setting an inspection range for the semiconductor substrate and is performed based on the partitioned region.

When the recipe is set, an area identifier is assigned to the corresponding area (S136). In more detail, as shown in FIG. 2, in the case of a non-memory chip or an SOC, a first region identification code is assigned to the first SRAM region 111 when a recipe is set for the first SRAM region 111. The second region identification code is assigned to the second SRAM region 112 when the recipe is set for the second SRAM region 112, and the third region identification code is assigned to the LOGIC region 113 when the recipe is set for the LOGIC region 113. And a fourth region identification code to the F-MEMORY region 114 when the recipe is set for the F-MEMORY region 114.

When the recipe setting is completed by assigning an area identification code (S136), image data of the semiconductor substrate is acquired by scanning (S140). In this case, the acquired image data includes an area identification code. That is, it may be known which area of the semiconductor substrate is image data obtained by scanning.                     

When scanning is completed (S140), defects existing on the semiconductor substrate are detected from the scanning result (S150). As a detection method of the defects, the reflected light for each unit range on the semiconductor substrate can be compared relative. Methods for detecting defects from scanning results are disclosed in many publications and will be readily understood by those skilled in the art. The defect detection result is shown in FIG. 4 as an example.

4 is a diagram illustrating an example of a defect detection result of the non-memory chip of FIG. 1.

Referring to FIG. 4, the defect detection result data may include coordinate information 231, size information 233, area information 235, and grade information 237 for each defect 230. Here, according to the defect inspection method according to the present embodiment, the region information 239 for each defect 230 can also be found in the defect detection result data. This is because a recipe is created so that the region identification code is included in the image data obtained by scanning the semiconductor substrate. That is, it is possible to find out which defect is in the first SRAM region 111, the second SRAM region 112, the LOGIC region 113, or the F-MEMORY region 114. In more detail, the defect in which the region information 239 is 1 is a defect existing in the first SRAM region 111, and the defect in which the region information 239 is 4 is a F-MEMORY region 114 defect.

After obtaining a defect detection result including region information of the defects (S150), the detected defects are classified by regions (S160). The classification method is relatively simple. This is because the area identification code corresponding to each defect can be performed. The classification result of the detected defects may be displayed as shown in FIGS. 5, 6, and 7 as an example.

FIG. 5 is a schematic diagram illustrating a first map without filtering the defect classification result of FIG. 1 by region, and FIG. 6 is a second map filtering only defects existing in a specific region in the first map of FIG. 5. It is a schematic diagram showing.

5 and 6, in the first map 300, the first to fourth defects 341, 342, 343, and 344 are displayed on the display apparatus without being filtered for each region. However, the first to fourth defects 341, 342, 343, and 344 may be displayed in color, shape, or hatched.

Among the first to fourth defects 341, 342, 343, and 344 of the first map 301, when only the defects existing in the F-MEMORY region 114 are filtered, the second map 400 of FIG. 6 is filtered. ) Is displayed. This can be achieved relatively simply by selecting only the defects having the region identification code '4' of the F-MEMORY region 114 from the defect detection result and displaying them on the display device.

As described above, the defects may be displayed on a map-by-region basis. Alternatively, the defects may be classified and displayed according to trends as shown in FIG. 7.

 FIG. 7 illustrates a trend graph for explaining a result of defect classification in FIG. 1.

Referring to FIG. 7, the defect result data may be displayed as the number of defects generated in each region by date. Defects generated in each area can be marked by color, shape or hatched.

In addition to the defect display method described above, the detected defects are classified and displayed by defect density per unit area, good chip rate, defect image, defect size, and the like. You may.

According to the defect inspection method according to an embodiment as described above, it is possible to quickly and easily determine which defects exist in which regions. In addition, it is possible to quickly and easily check what trends are caused by defects by region. That is, the defect inspection result required for the improvement of the yield of a semiconductor substrate processing process can be acquired quickly, correctly, and easily.

According to the present invention, a defect inspection result including area information in which a defect exists can be obtained. Therefore, defects can be accurately analyzed and countermeasures can be prepared quickly and effectively. Therefore, not only can the efficiency of the defect process be maximized, but also the semiconductor device can be manufactured precisely.

As described above, the present invention has been described with reference to the preferred embodiments, but those skilled in the art can variously modify the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be appreciated that it can be changed.

Claims (5)

Partitioning the microstructures formed on the semiconductor substrate for each region; Scanning the semiconductor substrate to obtain image data of the microstructures; Detecting a defect on the semiconductor substrate from the image data; And And classifying the detected defects by the regions. The defect inspection method according to claim 1, wherein the detected defect includes region data in which the defect is located, and wherein the classifying classifies the defect based on the region data. The method of claim 1, wherein the partitioning step, Partitioning the semiconductor substrate by die; And And dividing the repetition region into which the microstructures are repeatedly formed for each die and the non-repetition region where the microstructures are formed repeatedly. The logic circuit of claim 3, wherein the repeating region is at least one selected from a group consisting of an SRAM region, a DRAM region, and a flash memory region, and the non-repeatable region is a logic region. The defect inspection method characterized by the above-mentioned. The method of claim 1, wherein the microstructure is a semiconductor device formed on the semiconductor substrate.

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