KR20060075509A - Output enable signal generating apparatus, output enable signal outputting apparatus and memory using the generating apparatus - Google Patents

Abstract

The present invention discloses an output enable signal generating device for selectively outputting an output enable signal, an output enable signal output device and a memory element using the device.

The output enable signal generating device of the present invention is a first output enable for outputting a second output enable signal by delaying the first output enable signal for a predetermined time according to the first control signal when the output enable reset signal is activated. Delay unit; And selectively outputting a plurality of output enable signals by delaying the second output enable signal according to a cascade latency (CL) signal, the first control signal, and the second control signal when the output enable reset signal is activated. And a second output enable delay unit to selectively generate only the required output enable signal according to a preset cascade latency value and to block unnecessary output enable signals from being generated, thereby reducing unnecessary current consumption. There is a big advantage in the application to the memory device.

Memory, Output Enable, Cascading

Description

Output enable signal generating apparatus, output enable signal output apparatus and memory device using the same {output enable signal generating apparatus, output enable signal outputting apparatus and memory using the generating apparatus}             

1 is a block diagram showing a configuration of a circuit for generating signals related to data output in a conventional memory device.

2 is a timing diagram for output enable signals generated during a read operation in DDR SDRAM.

FIG. 3 is a diagram illustrating in more detail the configuration of the output enable signal output unit in FIG. 1; FIG.

FIG. 4 is a circuit diagram illustrating in detail the configuration of the third output enable signal generator in FIG. 3. FIG.

5 is a block diagram showing a configuration of a circuit for generating signals related to data output in a memory device according to the present invention.

FIG. 6 is a diagram illustrating the configuration of an output enable signal output unit in FIG. 5 in more detail. FIG.

FIG. 7 is a circuit diagram illustrating in more detail a configuration of an optional output enable signal generator in FIG. 6. FIG.

The present invention relates to an apparatus for generating an output enable signal for a data read. More specifically, the present invention selectively generates only an output enable signal required according to a pre-set cas latency signal (CL). The present invention relates to an output enable signal generating device capable of reducing unnecessary current consumption by blocking an output enable signal from being generated, and an output enable signal output device and a memory device using the device.

Generally, in order to read data stored in a memory cell in a memory device operating at a high speed, a read enable signal is input because an external read enable signal is input and the operation is not processed within one clock. Then, the output enable signal is applied and the data is output according to the CL signal that determines how many clocks to output the data.

FIG. 1 is a configuration diagram illustrating a circuit for generating signals related to data output in a conventional memory device, and FIG. 2 is a timing diagram of output enable signals generated during a read operation in a DDR SDRAM.

When the read command signal READ is applied from the outside in synchronization with the clock signal, the output enable signal output unit d_oe_gen is output enable signals oe0, oe05, oe1, and oe15 that are delayed differently according to the rising timings of the control signals rclk_dll and fclk_dll. Create and print oe2, oe25, oe3, oe35, and oe4. Here, the control signal rclk_dll is a rising clock delay locked loop signal having a pulse at the rising edge of the main clock CLK, and the control signal fclk_dll is a falling clock delay locked loop signal having a pulse at the falling edge of the main clock CLK. . The delay of each output enable signal is determined according to a predetermined CL value. That is, as shown in FIG. 2, the output enable signal oe05 is generated by delaying the output enable signal oe0 in accordance with the rising timing of the control signals rclk_dll and fclk_dll, and the output enable signal oe1 is generated by delaying the output enable signal oe05. do. The other output enable signals oe15, oe2, oe25 and oe3 are generated by delaying the output enable signals oe1, oe15, oe2 and oe25, respectively.

The output enable signals output from the output enable signal output unit d_oe_gen are respectively applied to the data output control unit d_dout_ctrl and the data strobe control unit d_qs_ctrl, and according to the CL set in the mode register set MRS, the first filtering signal fouten, A second filtering signal routen, a data output reset signal rst_doutz, a data strobe preamble control signal qsen_pre, and a data strobe enable signal qsen are generated. In this case, the first and second filtering signals fouten and routen are signals for filtering clock signals used for data output among clock signals of the phase delay loop circuit DLL and are generated in synchronization with rising edges of the control signals fclk_dll and rclk_dll, respectively. do.

CL output signal routen fouten qsen_pre qsen Blocking signal CL = 1.5 oe1 oe05 oe15 oe05 oe2 CL = 2 oe1 oe15 oe15 oe1 oe2 CL = 2.5 oe2 oe15 oe2 oe15 oe25 CL = 3 oe2 oe25 oe25 oe25 oe3

FIG. 3 is a diagram illustrating in detail the configuration of the output enable signal output unit d_oe_gen in FIG. 1.

The output enable signal output unit d_oe_gen is the reset unit d_oe_rstz for generating the output enable reset signal oe_rstz, the first output enable signal generator d_oe0_gen for generating the output enable signal oe0, and the output enable signal oe0 with the output enable signal oe05. A second output enable signal generator d_oe05_gen for generating a third output enable signal generator d_oe1_gen for generating an output enable signal oe1 with an output enable signal oe05, and an output enable signal oe15 with an output enable signal oe1. and a third output enable signal generator d_oex_gen for generating oe2, oe25, oe3, oe35, and oe4.

FIG. 4 is a circuit diagram illustrating in detail the configuration of the third output enable signal generator d_oex_gen in FIG. 3.

The output enable signal generator d_oex_gen delays the output enable signals oe1, oe15, oe2, oe25, and oe3 by 0.5 tck, respectively, in response to the output enable reset signal oe_rstz and the control signal fclk_dllz or rclk_dllz. Output enable delay units 1 to 5 for generating oe25, oe3, and oe35 are sequentially connected in series.

However, the generation of the signals fouten, routen, qsen_pre, and qsen for the data output do not require all the output enable signals generated by the output enable signal generator d_oex_gen according to the CL value as shown in Table 1, but do not require a specific output. Only enable signal is required. For example, when CL = 2, only one output enable signal oe15 of one of the output enable signals generated by the output enable signal generator d_oex_gen is required. However, when the control signals fclk_dllz and rclk_dllz are both at the low level, the transmission gate is turned on to output all of the output enable signals oe2, oe25, oe3, and oe35, thereby causing unnecessary current consumption.

Accordingly, an object of the present invention for solving the above-mentioned problem is to improve the structure of a circuit for generating an output enable signal, thereby preventing unnecessary current consumption by blocking the generation of unnecessary output enable signals.

The output enable signal generating apparatus of the present invention for achieving the above object is to delay the first output enable signal for a predetermined time according to the first control signal when the output enable reset signal is activated to generate a second output enable signal. A first output enable delay unit for outputting; And selectively outputting a plurality of output enable signals by delaying the second output enable signal according to a cascade latency (CL) signal, the first control signal, and the second control signal when the output enable reset signal is activated. And a second output enable delay unit.

 The output enable signal output device of the present invention comprises: a reset unit for generating and outputting an output enable reset signal; A first output enable signal generator configured to generate and output a first output enable signal according to the output enable reset signal and the first control signal; A second output enable signal generator configured to delay the first output enable signal to generate and output a second output enable signal; A third output enable signal generator configured to delay the second output enable signal to generate and output a third output enable signal; And outputting a plurality of fourth output enable signals by delaying the third output enable signal to correspond to rising edges of the second control signal and the third control signal, and when the specific cascade latency (CL) signals are activated. And an optional output enable signal generator for selectively blocking outputs of the plurality of fourth output enable signals irrespective of the second control signal and the third control signal.

The memory device of the present invention includes an output enable signal output unit for selectively blocking the output of the output enable signals in accordance with the cascade latency signal; A data output control unit for generating and outputting a filtering signal for filtering a clock signal used for data output among clock signals of a phase delay loop circuit (DLL) according to the output enable signal; And a data strobe control unit configured to generate and output a data strobe preamble control signal and a data strobe enable signal according to the output enable signal.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

FIG. 5 is a configuration diagram illustrating a configuration of a circuit for generating signals related to data output in a memory device according to the present invention.

The memory device of the present invention includes an output enable signal output unit 100, a data output control unit 200, and a data strobe control unit 300.

The output enable signal output unit 100 selectively blocks the output of the output enable signals according to the CL signal. That is, the output enable signal output unit 100 outputs the output signals fouten, routen, and the output signal of the data output control unit 200 and the data strobe control unit 300 as shown in Table 1 according to the CL value set in the mode register set MRS (not shown). It selectively blocks the output of the output enable signals that do not affect the occurrence of qsen and qsen_pre. More specifically, the output enable signal output unit 100 outputs the enable signals oe2, oe25, oe3, oe35, and oe4 regardless of the states of the control signals rclk_dll and fclk_dll when the CL signals cl15, cl2, cl25, and cl3 are activated. Selectively block the output of

Since the data output controller 200 and the data strobe controller 300 have the same configuration and operation as the data output controller d_dout_ctrl and the data strobe controller d_qs_ctrl of FIG. 1, description thereof will be omitted.

FIG. 6 is a diagram illustrating in detail the configuration of the output enable signal output unit 100 in FIG. 5.

The output enable signal output unit 100 of the present invention includes a reset unit 110, a plurality of output enable signal generators 120 to 140, and an optional output enable signal generator 150.

Since the reset unit 110 and the output enable signal generators 120 to 140 have the same configuration and function as those of FIG. 3, description thereof will be omitted.

The optional output enable signal generator 150 selectively blocks the output of the output enable signals oe2, oe25, oe3, oe35, and oe4 according to the CL signals cl15, cl2, cl25, and cl3. That is, unlike the third output enable signal generator d_oxe_gen in FIG. The enable signal generator 150 selectively blocks the output of the output enable signals oe2, oe25, oe3, oe35, and oe4 regardless of the control signals rclk_dllz and fclk_dllz according to whether the CL signals cl15, cl2, cl25, and cl3 are activated. Let's do it.

FIG. 7 is a circuit diagram illustrating in detail the configuration of the optional output enable signal generator 150 in FIG. 6.

The selective output enable signal generator 150 of the present invention includes a plurality of output enable delay units 10 to 50 connected in series.

The output enable delay unit 10 generates and outputs an output enable signal oe15 by delaying the output enable oe1 for a predetermined time according to the control signal fclk_dllz when the output enable reset signal oe_rstz is activated.

The output enable delay unit 10 sets the output signal of the switching unit 12 when the switching unit 12 selectively switches the output enable signal oe1 and the output enable reset signal oe_rstz is activated according to the control signal fclk_dllz. And a delay unit 14 for generating and outputting the output enable signal oe15 with a time delay. Here, the switching unit 12 includes an inverter IV1 for inverting and outputting the control signal fclk_dllz and a transfer gate TG1 for selectively switching the output enable signal oe1 according to the output signal of the control signal fclk_dllz and the inverter IV1. The delay unit 14 inverts the output of the enable enable signal oe_rstz and the output signal of the switching unit 12 to the NAND gate ND1 and the output of the NAND gate ND1 to the output terminal of the switching unit 12, and feeds back the inverter. IV2 and inverter inverters IV3 to IV5 which invert the output of the NAND gate ND1 to output the output enable signal oe15.

The output enable delay unit 20 delays the output signal oe15 of the output enable delay unit 10 by a predetermined time according to the control signals rclk_dllz and CL signals cl15 and cl2 when the output enable reset signal oe_rstz is activated. Create and print oe2.

The output enable delay unit 20 includes a switching unit 22 and an output enable reset signal oe_rstz for selectively switching the output signal oe15 of the output enable delay unit 10 according to the control signals rclk_dllz and the CL signals cl15 and cl2. Has a delay section 24 for delaying the output signal of the switching section 22 for a predetermined time to generate and output the output enable signal oe2. Here, the switching unit 22 outputs the output signals of the NOA gate NOR1 and the inverter IV6 and the output signal of the NOA gate NOR1 and the inverter IV6 which inverts the output of the NOA gate NOR1, the NOA gate NOR1, and the control signals rclk_dllz and the CL signals cl15 and cl2. And a transmission gate TG2 for selectively switching the output enable signal oe15 in accordance with the output signal. The delay unit 24 inverts the output of the enable enable reset signal oe_rstz and the output signal of the switching unit 22 to NAND gate ND2 and the output of the NAND gate ND2 to the output terminal of the switching unit 22 to feed back. IV7 and inverter inverters IV8 to IV10 which invert the output of the NAND gate ND2 and output the output enable signal oe2.

The output enable delay unit 30 delays the output signal oe2 of the output enable delay unit 20 by a predetermined time according to the control signals fclk_dllz and the CL signal cl25 when the output enable reset signal oe_rstz is activated, thereby outputting the output enable signal oe25. Create and print

The output enable delay unit 30 activates the switching unit 32 and the output enable reset signal oe_rstz which selectively switch the output signal oe2 of the output enable delay unit 20 according to the control signals fclk_dllz and the CL signal cl25. And a delay unit 34 for delaying the output signal of the time switching unit 32 for a predetermined time to generate and output the output enable signal oe25. Here, the switching unit 32 outputs the output signal of the NOA gate NOR2, which inverts the output of the control signal fclk_dllz and the CL signal cl25, the inverter IV11 which inverts the output of the NOA gate NOR2, and the output signal of the NOA gate NOR2 and the output signal of the inverter IV11. And a transmission gate TG3 for selectively switching the output enable signal oe2. The delay unit 34 inverts the output of the enable enable reset signal oe_rstz and the output signal of the switching unit 32 and the output of the NAND gate ND3 and the NAND gate ND3 to the output terminal of the switching unit 32 to feed back. IV12 and inverter inverters IV13 to IV15 for outputting the output enable signal oe25 by inverting the output of the NAND gate ND3.

The output enable delay unit 40 delays the output signal oe25 of the output enable delay unit 30 for a predetermined time according to the control signals rclk_dllz and the CL signal cl3 when the output enable reset signal oe_rstz is activated, thereby outputting the output enable signal oe3. Create and print

The output enable delay unit 40 includes a switching unit 42 and an output enable reset signal oe_rstz for selectively switching the output signal oe25 of the output enable delay unit 30 according to the control signals rclk_dllz and the CL signal cl3. A delay unit 44 is provided to delay and output the output signal of the switching unit 42 for a predetermined time to generate and output the output enable signal oe3. Here, the switching section 42 outputs the output signal of the NOA gate NOR3, which inverts the output of the NOA gate NOR3, and the output signal of the NOA gate NOR3 and the output signal of the inverter IV16. And a transmission gate TG4 for selectively switching the output enable signal oe25. The delay unit 44 inverts the output of the enable enable reset signal oe_rstz and the output signal of the switching unit 42 and the output of the NAND gate ND4 and the NAND gate ND4 to the output terminal of the switching unit 42. IV17 and inverter inverters IV18 to IV20 which invert the output of the NAND gate ND4 to output the output enable signal oe3.

The output enable delay unit 50 generates the output enable signal oe35 by delaying the output signal oe3 of the output enable delay unit 40 for a predetermined time according to the control signal fclk_dllz when the output enable reset signal oe_rstz is activated. .

The output enable delay unit 50 includes a switching unit 52 for selectively switching the output signal oe3 of the output enable delay unit 40 according to the control signal fclk_dllz and a switching unit when the output enable reset signal oe_rstz is activated. And a delay unit 54 for delaying the output signal of 52 for a predetermined time to generate and output the output enable signal oe35. Here, the switching unit 52 selectively switches the output signal oe3 of the output enable delay unit 40 according to the inverter IV21 and the control signal fclk_dllz and the output signal of the inverter IV21 which inverts and outputs the control signal fclk_dllz. TG5. The delay unit 54 inverts the output of the enable enable reset signal oe_rstz and the output signal of the switching unit 52 and the output of the NAND gate ND5 and the NAND gate ND5 to the output terminal of the switching unit 52 to feed back. IV22 and inverters IV23 to IV25 which invert the output of the NAND gate ND5 to output the output enable signal oe35.

The operation of the selective output enable signal generator 150 according to the present invention having the above-described configuration will be briefly described according to the value of the CL signal.

When CL = 1.5, only the output enable signals oe05, oe1, and oe15 need to be generated to output the signals fouten, routen, qsen_pre, and qsen for data output as shown in Table 1 above. That is, since the output enable signal oe2 and the delayed output enable signals oe25 and oe3 having the delayed output enable signal oe15 are not generated, unnecessary current consumption can be prevented, thereby preventing the generation of the output enable signal oe2. (See blocking signal in Table 1).

In the case of CL = 2, only output enable signals oe1 and oe15 need to be generated to output the signals fouten, routen, qsen_pre, and qsen for data output. Neither signals oe25 nor oe3 are generated.

Accordingly, the selective output enable signal generator 150 of the present invention is connected to the input terminal of the switching unit 22 in the output enable delay unit 20 that outputs the output enable signal oe2 as in the circuit of FIG. 7. The output signal of the output enable delay unit 10 is provided with the NOA gate NOR1 and the inverter IV6, and the switching unit 22 outputs the switching unit 22 when any one of the CL signals cl15 and cl2 indicating that the cascade latency is set to 1.5 or 2 is activated. It is configured to block oe15 from being applied to the delay unit 24. That is, when any one of the CL signals cl15 and cl2 is activated, the output of the NOA gate NOR1 transitions low regardless of the state of the control signal rclk_dllz, so that the output signal oe15 of the enable delay unit 10 outputs the transmission gate TG2. By blocking the enable delay unit 20 from being applied, the output enable signals oe2 and the output enable signals oe25, oe3, and oe35 below are not all activated.

In the same principle, in the case of CL = 2, since the generation of the output enable signal oe25 is cut off as shown in Table 1, the switching unit 32 in the output enable delay unit 30 outputting the output enable signal oe25. When the CL signal cl25 is activated at the input terminal of the NOA gate NOR2 and the inverter IV11, indicating that the cascade latency is set to 2.5, the switching unit 32 of the output enable delay unit 20 is independent of the control signal fclk_dllz. The output signal oe2 is blocked from being applied to the delay unit 34. Thus, when the CL signal cl25 is activated, the output enable signals oe15 and oe2 are activated, but not all the output enable signals oe25, oe3 and oe35 are activated.

In the case of CL = 3, in order to prevent the output enable signal oe3 and the output enable signal oe35 below, the output enable delay unit 40 is connected to the nominal gate NOR3 and the input terminal of the switching unit 42. When the CL signal cl3 indicating that the cascade latency is set to 3 is activated and the inverter IV16 is activated, the switching unit 42 outputs the output signal oe25 of the output enable delay unit 30 to the delay unit (regardless of the control signal rclk_dllz). Block access to Thus, when the CL signal cl3 is activated, the output enable signals oe15, oe2, oe2, and oe25 are activated, but not all the output enable signals oe3 and oe35 are activated.

As described above, the selective output enable signal generation device of the present invention selectively generates only the required output enable signal according to a preset Cas Latency (CL) value and unnecessary output enable signal is not generated. Blocking them can reduce unnecessary current consumption, which is a major advantage in memory devices that require low power.

Claims (13)

A first output enable delay unit for outputting a second output enable signal by delaying the first output enable signal for a predetermined time according to the first control signal when the output enable reset signal is activated; And And selectively outputting a plurality of output enable signals by delaying the second output enable signal according to a cascade latency (CL) signal, the first control signal and the second control signal when the output enable reset signal is activated. And an output enable signal generator having a second output enable delay unit. The method of claim 1, wherein the second output enable delay unit Blocking the application of the second output enable signal upon activation of any one of the first CL signal indicating that the cascade latency is set to 1.5 and the second CL signal indicating that the cascade latency is set to 2. A third output enable delay unit configured to receive and delay the second output enable signal according to the second control signal when the first and second CL signals are inactivated to output a third output enable signal; When the third CL signal informing that the cascade latency is set to 2.5 blocks the application of the third output enable signal when activated, and when the third CL signal is inactive, the third output signal is the third output according to the first control signal. A fourth output enable delay unit configured to receive the delay signal and delay the output signal to output a fourth output enable signal; And A fourth CL signal indicating that the cascade latency is set to 3 blocks the application of the fourth output enable signal upon activation, and when the fourth CL signal is inactive, the fourth output signal according to the second control signal. And a fifth output enable delay unit configured to receive and delay the enable signal to output a fifth output enable signal. The method of claim 1 or 2, wherein the first control signal is An output enable signal generator, characterized in that the falling clock locked loop signal having a pulse at the falling edge of the main clock (CLK). The method of claim 1 or 2, wherein the second control signal is And an output enable signal generation device comprising a rising clock delay locked loop signal having a pulse at the rising edge of the main clock CLK. The method of claim 1, wherein the first output enable delay unit A first switching unit selectively transmitting the first output enable signal according to the first control signal; And And a first delay unit for outputting the second output enable signal by delaying the output of the first switching unit for a predetermined time when an output enable reset signal is activated. The method of claim 5, wherein the third output enable delay unit A second switching unit for selectively transmitting the output of the first delay unit according to the first and second CL signals and the second control signal; And And a second delay unit for outputting the third output enable signal by delaying the output of the second switching unit for a predetermined time when an output enable reset signal is activated. The method of claim 6, wherein the fourth output enable delay unit A third switching unit selectively transmitting the output of the second delay unit according to the third CL signal and the first control signal; And And a third delay unit for outputting the fourth output enable signal by delaying the output of the third switching unit for a predetermined time when an output enable reset signal is activated. The method of claim 7, wherein the fifth output enable delay unit A fourth switching unit for selectively transmitting the output of the third delay unit according to the fourth CL signal and the second control signal; And And a fourth delay unit for outputting the fifth output enable signal by delaying the output of the fourth switching unit for a predetermined time when an output enable reset signal is activated. A reset unit generating and outputting an output enable reset signal; A first output enable signal generator configured to generate and output a first output enable signal according to the output enable reset signal and the first control signal; A second output enable signal generator configured to delay the first output enable signal to generate and output a second output enable signal; A third output enable signal generator configured to delay the second output enable signal to generate and output a third output enable signal; And Delaying the third output enable signal to output a plurality of fourth output enable signals corresponding to the rising edges of the second control signal and the third control signal, and when specific cascade latency (CL) signals are activated And an output enable signal generator for selectively blocking outputs of a plurality of fourth output enable signals irrespective of a control signal and the third control signal. The method of claim 9, wherein the selective output enable signal generation unit A first output enable delay unit for outputting a fifth output enable signal by delaying the third output enable signal for a predetermined time according to the second control signal when the output enable reset signal is activated; And A second delaying of the fifth output enable signal according to the specific CL signal, the second control signal, and the third control signal when the output enable reset signal is activated to selectively output a plurality of output enable signals; And an output enable delay unit. 11. The method of claim 10, wherein the second output enable delay unit Blocking the application of the fifth output enable signal upon activation of any one of the first CL signal indicating that the cascade latency is set to 1.5 and the second CL signal indicating that the cascade latency is set to 2, A third output enable delay unit configured to output a sixth output enable signal by receiving and delaying the fifth output enable signal according to the third control signal when the first and second CL signals are inactive; The third CL signal informing that the cascade latency is set to 2.5 blocks the application of the sixth output enable signal upon activation, and the sixth output according to the second control signal when the third CL signal is inactive. A fourth output enable delay unit configured to receive the enable signal and delay the output signal to output a seventh output enable signal; And The fourth CL signal indicating that the cascade latency is set to 3 blocks the application of the seventh output enable signal upon activation, and the fourth output signal according to the third control signal when the fourth CL signal is inactive. And a fifth output enable delay unit configured to receive and delay the enable signal to output the eighth output enable signal. An output enable signal output unit for selectively blocking output of the output enable signals according to the cascade latency signal; A data output control unit for generating and outputting a filtering signal for filtering a clock signal used for data output among clock signals of a phase delay loop circuit (DLL) according to the output enable signal; And And a data strobe control unit configured to generate and output a data strobe preamble control signal and a data strobe enable signal according to the output enable signal. The method of claim 12, wherein the output enable signal output unit And selectively outputting output enable signals that do not affect generation of the filtering signal, the data strobe preamble control signal, and the data strobe enable signal according to the cascade latency signal.

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