KR20060071076A - A coding method of convolutional turbo code for high-speed personal internet system and apparatus thereof - Google Patents

Abstract

The present invention relates to a method and apparatus for encoding a convolutional turbo code (CTC) for a personal mobile Internet system (HPi). In the implementation of a convolutional turbo code (CTC) coder, the input is encoded in units of two bits. Serial convolutional encoder to perform; A parallel convolutional encoder which receives the input in units of 8 bits and performs encoding; An interleaver for mixing the positions of the input bits; And a circular state finding block for determining initial state values of the serial convolutional encoder and the parallel convolutional encoder. According to the present invention, it is possible to implement a Very Large Scale Integration (VLSI) of a convolutional turbo code encoder adopted in the personal portable Internet system standard, and also to implement an 8-bit parallel processing convolutional encoder to minimize processing speed delay. And serial convolutional encoder and interleaver can be efficiently arranged to improve the processing speed of the entire CTC encoder.

CTC Encoder, Weaving Encoder, Interleaver, Mobile Internet, Tail Biting

Description

{A Coding Method of Convolutional Turbo Code for High-speed Personal Internet System and Apparatus}

1 is a diagram illustrating a convolutional turbo code (CTC) coder having a code rate of 1/3.

2 is a structural diagram of an 8-bit parallel convolutional encoder according to an embodiment of the present invention.

3 is an interleaver structure diagram according to an embodiment of the present invention.

4 is a structural diagram of a CTC encoder according to an embodiment of the present invention.

The present invention relates to a method and apparatus for encoding a convolutional turbo code (CTC) for a personal mobile Internet system (HPi), and more particularly, to improve the convolutional turbo code code rate and to minimize the area consumption in hardware implementation. The present invention relates to a convolutional turbo code encoding method and an apparatus thereof.

In general, in a wired / wireless digital communication system, an additional bit is added to an information bit at a transmitting end to correct an error on a transmission path, and a receiving end is corrected using an error correction algorithm. One of such error correction algorithms uses turbo code. In a typical turbo code, the encoder receives and processes one bit input every clock, while in a convolutional turbo code (CTC), two bits are input and processed every clock.

Convolutional Turbo Code (CTC) has been adopted as a channel codec of 802.16e, which is being studied recently, and has also been adopted in a high speed personal Internet (HPi) wireless communication system.

The convolutional turbo code (CTC) is mainly applied to a packet transmission system, so the coding unit is very small compared to the turbo code. Therefore, when a tail bit is added for termination, there is a problem in that the transmission efficiency is relatively low. To compensate for this, the tail biting technique is applied to the HPi system. By applying the tail biting technique, termination can be performed without additional bits, thereby improving transmission efficiency, while adding a coding process for finding an initial state value of the convolutional encoder, which causes a delay in processing speed.

Assuming that the convolutional turbo code (CTC) encoder input bit size is 2 × N, the convolutional turbo code (CTC) encoder with the general structure is used for N clock, convolutional encoder 2 to find the initial state value for convolutional encoder 1. A total of 3 x N is required, such as N clock to find the initial state value and N clock to perform the actual encoding.

On the other hand, as a prior art, Korean Patent Application No. 2002-7003287 discloses an invention named "implementation of a parallel turbo encoder", and proposes a method for designing a 2-bit input convolutional encoder for a serial turbo encoder. Basically, a turbo encoder that receives only one bit and encodes in serial form receives n bits per clock and supplies them in parallel to a delay element to perform encoding. One method for parallelizing convolutional encoders in a turbo encoder is presented. The patent proposes an n-bit input parallel encoding structure of a convolutional encoder in a turbo encoder.

An object of the present invention for solving the above problems is to solve the problem of delayed processing speed, and to provide an efficient hardware structure and design method of a convolutional turbo code (CTC) coder of a personal portable Internet (HPi) system.

Another object of the present invention is to implement an internal convolutional encoder and an n-bit input serial convolutional encoder and an 8-bit input parallel convolutional encoder for a convolutional turbo code (CTC) encoder characterized by having n-bit input, It is to provide an efficient structure for speeding up the entire convolutional turbo code (CTC) encoder using an internal interleaver and memory.

As a means for achieving the above object, the convolutional turbo code encoding method for a personal portable Internet system according to the present invention,

a) obtaining an interleaving address in operation of the interleaver;

b) encoding the interleaved data using a serial convolutional encoder having an initial register state value of all zeros to the obtained interleaving address;

c) determining an initial register value using a final register value obtained by the performed encoding;

d) storing the next interleaving data in 8 bit units while performing the encoding;

e) encoding an sequential data sequence using a parallel convolutional encoder 2 to determine an initial register value to be applied when performing actual encoding; And

f) initializing two parallel convolutional encoders 1 and 2 with the obtained initial register value, and then simultaneously performing encoding on the sequential data sequence and the interleaved data sequence

Characterized in that it comprises a.

In addition, the convolutional turbo code encoding apparatus for a personal portable Internet system according to the present invention,

A serial convolutional encoder which receives the input in units of two bits and performs encoding;

A parallel convolutional encoder which receives the input in units of 8 bits and performs encoding;

An interleaver for mixing the positions of the input bits; And

A cyclic state search block for determining initial state values of the serial convolutional encoder and the parallel convolutional encoder

Characterized in that it comprises a.

According to the present invention, it is possible to implement a Very Large Scale Integration (VLSI) of a convolutional turbo code encoder adopted in the personal portable Internet system standard, and also to implement an 8-bit parallel processing convolutional code to minimize processing speed delay. By effectively arranging the serial convolutional encoder and the interleaver, the processing speed of the entire CTC encoder can be improved.

Hereinafter, with reference to the accompanying drawings, a convolutional turbo code encoding method and apparatus for a personal portable Internet system according to an embodiment of the present invention will be described in detail.

1 is a diagram illustrating a convolutional turbo code (CTC) coder having a code rate 1/3, and FIG. 2 is a structural diagram of an 8-bit parallel convolutional coder according to an embodiment of the present invention.

In the embodiment of the present invention, the parallel convolutional coder receives an input in 8-bit units and performs encoding, unlike the serial convolutional coder receiving a 2-bit input and processing the same. In order to design an 8-bit parallel convolutional encoder, the convolutional turbo code (CTC) encoder state of FIG. 1 should be observed for 4 clock periods.

Furthermore, according to an embodiment of the present invention, the serial convolutional encoder consists of three registers and an exclusive-OR operator.

First, in FIG. 1, it is assumed that the A and B delay element values are S1, S2, and S3, respectively, and the delay and parity output bit values are examined for a total of four cycles of data from M0 to M3. Here, the + operator means Exclusive-OR.

Y1  A1 + B1 + S1 + S2 W1  A1 + B1 + S1 S1  A1 + B1 + S1 + S3 S2  S1 + B1 S3  S2 + B1

Y2  A2 + B2 + A1 + S3 W2  A2 + B2 + A1 + B1 + S1 + S3 S1  A2 + B2 + A1 + S1 + S3 + S2 S2  B2 + A1 + B1 + S1 + S3 S3  B2 + S1 + B1

Y3  A3 + B3 + A2 + S2 + B1 W3  A3 + B3 + A2 + A1 + S3 + S2 + B2 + S1 S1  A3 + B3 + A2 + A1 + S3 + S2 + B1 S2  B3 + A2 + B2 + A1 + S1 + S3 + S2 S3  B3 + B2 + A1 + B1 + S1 + S3

Y4  A4 + B4 + A3 + B1 + B2 + S1 W4  A4 + B4 + A3 + A2 + B1 + B3 + A1 + S3 + S2 S1  A4 + B4 + A3 + A2 + S2 + B2 + S1 S2  B4 + A3 + B3 + A2 + A1 + S3 + S2 + B1 S3  B4 + B3 + A2 + B2 + A1 + S1 + S3 + S2

Table 1 is the M0 input cycle, Table 2 is the M1 input cycle, Table 3 is the M2 input cycle, and Table 4 is the M3 input cycle.

When 8 bits are input using the table, encoding bits Y1, W1, Y2, W2, Y3, W3, Y4, and W4 for four periods can be obtained. The state value of the delay element is S1, S2, S3 of the last period M3. The hardware structure thereof is shown in FIG. 2.

In addition, the interleaver block proposes a convolutional turbo code (CTC) internal interleaving algorithm as shown in Equation 1 in a personal portable Internet (HPi) system.

Step 1: for j = 0 ... N-1

If (jmod2 == 0) let (B, A) = (A, B)

Step 2: Pi (j)

for j = 0 ... N-1

switch j mod 4:

case 0: I = (P0 * j + 1) mod N

case 1: I = (P0 * j + 1 + N / 2 + P1) mod N

case 2: I = (P0 * j + 1 + P2) mod N

case 3: I = (P0 * j + 1 + N / 2 + P3) mod N.

Step 1: for j = 0: N-1

if (j (0) == '0') let (B, A) = (A, B)

Step 2: D (-1) = 0

for j = 0: N-1

 if D (j-1) + P0 N> = 0,

D (j) = D (j-1) + P0 N;

else, D (j) = D (j-1) + P0;

switch j (1: 0)

case "00": const = 1;

case "01": const = N / 2 + 1 + P1 (= P4);

case "10": const = P2 + 1 (= P5);

case '11 ": const = N / 2 + 1 + P3 (P6);

if Pi (j) + D (j) N> = 0, Y = Pi (j) + D (j) N;

else, Y = Pi (j) + D (j);

 if Y N> = 0, out (j-1) = Y N;

 else, out (j-1) = Y;

While Equation 1 is described by modulo operation and multiplication, Equation 2 shows that all processes are performed by addition operation only. Therefore, hardware implementation according to the interleaving algorithm is easy. The structure of the interleaver is shown in FIG. 3.

The convolutional turbo code encoder is configured as shown in FIG. 4 by integrating the above element blocks. The operation of the CTC encoder can be largely divided into two steps. The first step is to determine the register initial value when performing the actual encoding, and the second step is to perform the actual encoding.

Referring to FIG. 4, an encoding process is performed on an interleaved data using a serial convolutional encoder having an interleaving address obtained from the interleaver while operating the interleaver and having initial register state values of all zeros. . The final register value obtained here is used to determine the initial register value. While performing encoding, the next interleaving data is stored in memory in units of 8 bits. This series of steps takes about N (1/2 of the input bit sequence length) clock.

Next, by performing the encoding on the sequential data sequence using the parallel convolutional encoder 2 to determine the initial register value to be applied when performing the actual encoding as above. In this case, because the parallel encoder is used, it takes about N / 4 clock.

Next, after the two parallel convolutional encoders 1 and 2 are initialized with the initial register values obtained above, encoding for the sequential data sequence and the data sequence in which the interleaving is performed is performed simultaneously.

As described above, the n-bit input parallel encoding structure of the convolutional encoder in the turbo encoder has been proposed. However, the embodiment of the present invention has proposed not only the parallelization of the convolutional encoder in the convolutional turbo code (CTC) encoder but also the entire structure for the higher speed.

While the invention has been shown and described in connection with specific embodiments thereof, it will be appreciated that various modifications and changes can be made without departing from the spirit and scope of the invention as indicated by the claims. Anyone who owns it can easily find out.

According to the present invention, an internal convolutional encoder for an convolutional turbo code (CTC) encoder with n-bit input is implemented by implementing an n-bit input serial convolutional encoder and an 8-bit input parallel convolutional encoder. An efficient structure for speeding up a convolutional turbo code (CTC) encoder can be presented.

In addition, according to the present invention, by providing not only the parallelization of the internal convolutional encoder of the convolutional turbo code (CTC) coder adopted in the personal mobile Internet (HPi) system, but also by providing an interleaver structure and a high speed structure of the entire CTC coder, In addition to providing a control method, a convolutional turbo code (CTC) interleaver can be implemented simply by an adder and a multiplexer, and the convolutional turbo code code speed can be improved and the area consumption of hardware can be minimized. .

Claims (7)

In the convolutional turbo code encoding method for a personal portable internet system, a) obtaining an interleaving address in operation of the interleaver; b) encoding the interleaved data using a serial convolutional encoder having an initial register state value of all zeros to the obtained interleaving address; c) determining an initial register value using the last register value obtained by the performed encoding; d) storing the next interleaving data in 8 bit units while performing the encoding; e) encoding an sequential data sequence using a parallel convolutional encoder 2 to determine an initial register value to be applied when performing actual encoding; And f) initializing two parallel convolutional encoders 1 and 2 with the obtained initial register value, and then simultaneously performing encoding on sequential data sequences and interleaved data sequences; A convolutional turbo code encoding method for a personal mobile internet system comprising a. The method of claim 1, The convolutional turbo code encoding method of the personal portable Internet system, characterized in that N (1/2 of the input bit sequence length) clock is required in the series of steps d). The method of claim 1, Convolutional turbo code encoding method for a personal portable Internet system, characterized in that N / 4 clock is required by the use of a parallel encoder in step e). In a convolutional turbo code (CTC) encoding apparatus, A serial convolutional encoder which receives the input in units of two bits and performs encoding; A parallel convolutional encoder which receives the input in units of 8 bits and performs encoding; An interleaver for mixing the positions of the input bits; And A cyclic state search block for determining initial state values of the serial convolutional encoder and the parallel convolutional encoder Convolutional turbo code encoding device for a personal mobile Internet system comprising a. The method of claim 4, wherein And a serial convolutional encoder comprises a plurality of registers and an Exclusive-OR operator. The method of claim 4, wherein The parallel convolutional encoder is a convolutional turbo code encoding apparatus for a personal portable Internet system, characterized in that for monitoring the state of the convolutional turbo code encoding apparatus for 4 clock periods to receive and encode in 8-bit units. The method according to claim 4 or 6, In order to design the 8-bit parallel convolutional encoder, 8-bit parallel data (A1-A4, B1-B4) and delay element values (S1, S2, S3) as input bits are used for a total of 4 cycles of data from M0 to M3. When 8 bits are input as the delay element and the parity output bit value, the personalized portable device is configured to obtain encoding bits (Y1, W1, Y2, W2, Y3, W3, Y4, W4) for 4 cycles. Convolutional Turbo Code Encoding Device for Internet Systems.

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