KR20060070837A - Thin film transistor array panel - Google Patents

Abstract

The thin film transistor array panel according to the exemplary embodiment of the present invention includes an insulating substrate, a first signal line formed on the insulating substrate, a second signal line insulated from and intersecting the first signal line, and an area defined by the crossing of the first signal line and the second signal line. And a thin film transistor electrically connected to the pixel electrode, the first signal line, the second signal line, and the pixel electrode formed each time, and having a semiconductor in which a channel is formed. In this case, the semiconductor in which the channel is formed is disposed within the boundary of the gate electrode or the data line, and is separated from other semiconductors under the drain electrode.

Semiconductor, Leakage Current, Thin Film Transistor, Liquid Crystal Display

Description

Thin film transistor array panel

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 1 taken along the line II-II ′.

3 is a layout view of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment of the present invention.

4 is a layout view illustrating a structure of a common electrode display panel for a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 5 is a layout view illustrating a structure of a liquid crystal display including the display panels of FIGS. 3 and 4.

FIG. 6 is a cross-sectional view of the liquid crystal display of FIG. 5 taken along the line VI-VI '. FIG.

<Description of the symbols for the main parts of the drawings>

110, 210: substrate 121, 129: gate line

124: gate electrode 140; Gate insulating film

151, 154, and 155 semiconductors 161, 163 and 165 resistive contact members                 

171, 179: data line 173: source electrode

175: drain electrode 180: protective film

181, 182, 185: contact hole 190: pixel electrode

81, 82: contact auxiliary member 270: common electrode

The present invention relates to a thin film transistor array panel, and more particularly, to a thin film transistor array panel using amorphous silicon as a semiconductor.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which field generating electrodes such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. Is applied to generate an electric field in the liquid crystal layer, thereby determining the orientation of liquid crystal molecules in the liquid crystal layer and controlling the polarization of incident light to display an image.

Among the liquid crystal display devices, a field generating electrode is provided on each of two display panels. Among them, a liquid crystal display device having a structure in which a plurality of pixel electrodes are arranged in a matrix form on one display panel and one common electrode covering the entire display panel on the other display panel is mainstream. The display of an image in this liquid crystal display device is performed by applying a separate voltage to each pixel electrode. To this end, a thin film transistor, which is a three-terminal device for switching a voltage applied to a pixel electrode, is connected to each pixel electrode, and a gate line transferring a signal for controlling the thin film transistor and data transferring a voltage to be applied to the pixel electrode. Install the wire on the display panel.

In such a liquid crystal display, a semiconductor layer is interposed between the gate line and the data line, thereby minimizing parasitic capacitance generated therebetween or preventing short or disconnection of the gate line or data line.

However, the portion not covered by the signal line is exposed to the light source, so that leakage current due to light is generated, which causes an afterimage in the image.

An object of the present invention is to provide a thin film transistor array panel capable of minimizing afterimages.

In order to solve this problem, the semiconductor in which the thin film transistor channel is formed in the thin film transistor array panel according to the present invention is disposed in the boundary line of the signal line.

More specifically, the thin film transistor array panel according to the exemplary embodiment of the present invention may include an insulating substrate, a first signal line formed on the insulating substrate, a second signal line insulated from and intersecting the first signal line, and a first signal line and a second signal line intersecting each other. And a thin film transistor having a first semiconductor, which is electrically connected to a pixel electrode, a first signal line, a second signal line, and a pixel electrode formed in each of the regions defined by the channel, and has a channel formed thereon. In this case, the first semiconductor is disposed within the boundary between the gate electrode and the data line.

The semiconductor device may further include a second semiconductor including the same layer as the first semiconductor and separated from the first semiconductor and disposed under the drain electrode of the thin film transistor.

The first semiconductor may be linearly formed along the data line, and the pixel electrode may have a cutout.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Hereinafter, a thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, the structure of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 2.                     

FIG. 1 is a layout view illustrating a structure of a thin film transistor array panel according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along line II-II ′.

A plurality of gate lines 121 are formed on the insulating substrate 110 to transfer gate signals.

The gate lines 121 are separated from each other and mainly extend in the horizontal direction, and a part of each gate line 121 forms a plurality of gate electrodes 124. In addition, the other part of each gate line protrudes downward to form a plurality of expansions 127, and has a wide end portion 129 for connecting another layer or an external device.

The gate line 121 includes two layers having different physical properties, that is, a lower layer 121p and an upper layer 121q thereon. The top layer 121q is a material having excellent physical, chemical and electrical contact properties with other materials, particularly indium zinc oxide (IZO) or indium tin oxide (ITO), such as molybdenum (Mo) and molybdenum alloys (eg, molybdenum-tungsten) MoW) alloy], and chromium (Cr). In contrast, the lower layer 121p is made of a metal having a low resistivity, such as aluminum (Al) or an aluminum alloy, so as to reduce the delay or voltage drop of the gate signal. An example of the combination of the lower layer 121p and the upper layer 121q may be aluminum-neodymium (Nd) alloy / chromium, and the positions may be interchanged. In FIG. 2, the lower and upper layers of the gate electrode 124 are denoted by reference numerals 124p and 124q, and the lower and upper layers of the end portion 129 of the gate line 121 are denoted by reference numerals 129p and 129q, respectively.

Side surfaces of the lower layer 121p and the upper layer 121q are inclined, respectively, and the inclination angle thereof is about 30 to 80 ° with respect to the surface of the substrate 110.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121.

A plurality of linear semiconductors 151 and island semiconductors 156 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. The linear semiconductor 151 extends mainly in the longitudinal direction, from which a plurality of protrusions 154 extend up to the gate electrode 124. The island semiconductor 156 is separated from the linear semiconductor 151. In this case, the protrusion 154 of the linear semiconductor 151 is located within the boundary of the gate electrode 124.

On top of the semiconductors 151 and 156 a plurality of linear and island ohmic contacts 161 made of a material such as n + hydrogenated amorphous silicon doped with a high concentration of n-type impurities such as silicide or phosphorus. 165 and 166 are formed, respectively. The linear ohmic contact 161 has a plurality of protrusions 163 extending toward the gate electrode 124, and the protrusions 163 and the island-type ohmic contact 165 are paired and disposed on the semiconductor 154. In this case, the gate electrodes 124 face each other. The islanding ohmic contact 166 is positioned on the island semiconductor 156.

Side surfaces of the semiconductor layer of the thin film transistor including the semiconductors 151 and 156 and the ohmic contacts 161, 165 and 166 are also inclined and have an inclination angle of 30-80 °.                     

The plurality of data lines 171, the plurality of drain electrodes 175, and the plurality of storage capacitor conductors may be formed on the resistance contact members 161, 165, 166, and the gate insulating layer 140, respectively. storage capacitor conductor 177 is formed.

The data line 171 mainly extends in the vertical direction to cross the gate line 121 and transmit a data voltage. A plurality of branches extending from the data line 171 toward the drain electrode 175 forms a source electrode 173. The pair of source electrode 173 and the drain electrode 175 are separated from each other and positioned opposite to the gate electrode 124. The gate electrode 124, the source electrode 173, and the drain electrode 175 together with the protrusion 154 of the linear semiconductor 151 form a thin film transistor (TFT), and the channel of the thin film transistor The protrusion 154 of the linear semiconductor 151 is formed between the source electrode 173 and the drain electrode 175. At this time, the semiconductor 154 is disposed inside the boundary line of the gate electrode 124, which is an opaque film, and is not exposed to the light source. In addition, the semiconductor device may be disposed below the drain electrode 175 and separated from the island-like semiconductor 156 exposed outside the boundary line of the drain electrode 175. Therefore, it is possible to minimize the occurrence of leakage current due to light in the protrusion 154 of the semiconductor 151, thereby minimizing the afterimage caused by the leakage current when displaying an image.

The storage capacitor conductor 177 overlaps the extension portion 127 of the gate line 121.

In this case, the data line 171 and the drain electrode 175 are materials having excellent physical, chemical, and electrical contact properties with other materials, particularly indium zinc oxide (IZO) or indium tin oxide (ITO), such as molybdenum (Mo) and molybdenum. A conductive film made of an alloy, chromium, or the like, and a conductive film made of a metal having a low resistivity, such as aluminum (Al) or an aluminum alloy, so as to reduce a delay or voltage drop of a data signal. It may be a single film or a multilayer film.

The data line 171, the drain electrode 175, and the conductor 177 for the storage capacitor are also inclined at an angle of about 30 to 80 °, similarly to the gate line 121.

The ohmic contacts 161, 165, and 166 exist only between the semiconductors 151 and 155 thereunder and the data line 171 and the drain electrode 175 thereon, and serve to lower the contact resistance. Although the width of the linear semiconductor 151 is smaller than the width of the data line 171 in most places, the width of the linear semiconductor 151 may be increased at a portion where the linear semiconductor 151 meets the gate line 121. Insulation between the data lines 171 is strengthened and the data lines 171 are prevented from being disconnected.

On the data line 171, the drain electrode 175, the conductive capacitor 177 for the storage capacitor, and the exposed portion of the semiconductor 154, an organic material or plasma chemical vapor deposition having excellent planarization characteristics and photosensitivity. A passivation layer 180 made of a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or the like formed by enhanced chemical vapor deposition (PECVD) is formed.

In an embodiment made of an organic material, which is the passivation layer 180, the passivation layer 180 is formed to prevent the organic material of the passivation layer 180 from coming into contact with the portion where the semiconductor 154 is exposed between the data line 171 and the drain electrode 175. ) Preferably includes an insulating film made of silicon nitride or silicon oxide covering the semiconductor 154.

The passivation layer 180 includes a plurality of contact holes 185, 187, and 182 that respectively expose the drain electrode 175, the storage capacitor conductor 177, and the end portion 179 of the data line 171. A contact hole 181 is formed along with the gate insulating layer 140 to expose the end portion 129 of the gate line 121.

The contact holes 185, 187, 182, and 181 expose the drain electrodes 175, the conductor 177 for the storage capacitor, the data lines 171, and the ends 129, 179 of the gate line 121. In the contact holes 185, 187, 182, and 181, the aluminum-based conductive film is preferably not exposed to secure contact characteristics with the conductive film of ITO or IZO formed later.

A plurality of pixel electrodes 190 and a plurality of contact assistants 82 and 81 formed of IZO or ITO are formed on the passivation layer 180.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 and the storage capacitor conductor 177 through the contact holes 185 and 187, respectively, to receive a data voltage from the drain electrode 175, and to connect the conductor. Transfer data voltage to 177.

The pixel electrode 190 to which the data voltage is applied rearranges the liquid crystal molecules of the liquid crystal layer by generating an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied. .

In addition, as described above, the pixel electrode 190 and the common electrode form a capacitor (hereinafter referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off. For the sake of reinforcement there are other capacitors connected in parallel with the liquid crystal capacitor which are referred to as "storage electrodes". The storage capacitor is made by overlapping the pixel electrode 190 and the neighboring gate line 121 (which is referred to as a "previous gate line"), and the like, to increase the capacitance of the storage capacitor, that is, the storage capacitance. In order to increase the overlapped area by providing an extension part 127 extending the gate line 121, a protective film conductor 177 connected to the pixel electrode 190 and overlapping the extension part 127 is provided as a protective film. 180) Place it underneath to bring the distance between the two closer.

The pixel electrode 190 also overlaps the neighboring gate line 121 and the data line 171 to increase the aperture ratio, but may not overlap.

The contact auxiliary members 81 and 82 are connected to the end portions 129 and 179 of the data lines through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 serve to protect and protect the adhesion between the end portions 129 and 179 of the gate line 121 and the data line 171 and an external device such as a driving integrated circuit. It is not essential that the application is optional.

According to another embodiment of the present invention, a transparent conductive polymer may be used as the material of the pixel electrode 190, and in the case of a reflective liquid crystal display, an opaque reflective metal may be used. In this case, the contact assistants 81 and 82 may be made of a material different from the pixel electrode 190, in particular, IZO or ITO.                     

In another embodiment of the present invention, the pixel electrode may have domain dividing means for dividing the pixel into a plurality of domains to orient the liquid crystal molecules, which will be described in detail with reference to the accompanying drawings.

3 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment. FIG. 4 is a layout view illustrating a structure of an opposing display panel for a liquid crystal display according to another exemplary embodiment. 5 is a layout view illustrating a structure of a liquid crystal display according to an exemplary embodiment in which the display panels of FIGS. 3 and 4 are aligned, and FIG. 6 is a line VI-VI ′ of the liquid crystal display of FIG. 5. It is a cross-sectional view cut along.

The liquid crystal display according to the present exemplary embodiment includes a thin film transistor array panel 100, a common electrode display panel 200, and a liquid crystal layer 3 interposed between the two display panels 100 and 200.

First, the thin film transistor array panel 100 will be described in detail with reference to FIGS. 3, 5, and 6. Here, the detailed description of the same structure as in the above embodiment will be omitted, and only other features will be described in detail.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on the insulating substrate 110 to transmit the gate signals.

Each gate electrode 124 forms a protrusion of the gate line 121.

Each storage electrode line 131 mainly includes a plurality of sets of branches that extend in the horizontal direction and constitute the first to fourth storage electrodes 133a, 133b, 133c, and 133d. The first storage electrode 133a and the second storage electrode 133b extend in the vertical direction, and the third and fourth storage electrodes 133c and 133d extend in an oblique direction and are disposed at both ends of the second storage electrode 133b. The first sustain electrode 133a is connected to and adjacent to each other. The third and fourth sustain electrodes 133c and 133d have inverted symmetry with respect to the center line between two adjacent gate lines 121. A predetermined voltage such as a common voltage applied to the common electrode 270 of the common electrode display panel 200 of the liquid crystal display device is applied to the sustain electrode line 131.

The protrusion 154 in which the channel of the thin film transistor is formed extends toward the gate electrode 124. Also at this time, the linear semiconductor 151 is disposed within the boundary of the data line 171 and is separated from the island-like semiconductor 156 exposed outside the boundary of the drain electrode 175. Leakage current caused by light can be minimized, and afterimage can be minimized.

In addition, a plurality of under-bridge metal pieces 178 positioned on the gate line 121 are formed on the same layer as the data line 171. 121 and overlapped with each other.

The passivation layer 180 has a plurality of contact holes 183a and 183b exposing a part of the storage electrode line 131 together with the gate insulating layer 140.

A plurality of pixel electrodes 190, sustain electrode line connecting legs 83, and a plurality of contact assistants 81 and 82 made of ITO or IZO are formed on the passivation layer 180.                     

The storage electrode line connecting leg 83 crosses the gate line 121 and the source electrode 173, and is disposed on the opposite side of the first storage electrode with the gate line 121 interposed therebetween through the contact holes 183a and 183b. It is connected to the exposed end of 133a and the exposed part of sustain electrode line 131. The storage electrode line 131 can be used to repair a defect of the storage electrode line connection leg 83, the metal piece 178, the gate line 121, the data line 171, or the thin film transistor.

Each pixel electrode 190 is chamfered at the left corner, and the chamfered hypotenuse forms an angle of about 45 degrees with respect to the gate line 121.

The pixel electrode 190 has a central cutout 91, a lower cutout 92a, and an upper cutout 92b, and the pixel electrode 190 includes a plurality of regions by these cutouts 91, 92a, and 92b. Divided into. The cutouts 91, 92a, and 92b have almost inverted symmetry with respect to a horizontal center line that bisects the pixel electrode 190 in parallel with the gate line 121.

The lower and upper cutouts 92a and 92b extend obliquely from the right side to the left side of the pixel electrode 190 and are positioned on the lower half and the upper half of the horizontal center line of the pixel electrode 190, respectively. The lower and upper cutouts 92a and 92b extend perpendicular to each other at an angle of about 45 degrees with respect to the gate line 121.

The center cutout 91 is disposed at the center of the pixel electrode 190 and has an inlet at the right side. The inlet of the central incision 91 has a pair of hypotenuses substantially parallel to the lower incision 92a and the upper incision 92b, respectively.

Accordingly, the lower half of the pixel electrode is divided into two regions by the lower cutout 92a, and the upper half is also divided into two regions by the upper cutout 92b. In this case, the number of regions or the number of cutouts may vary depending on the size of the pixel, the ratio of the length of the horizontal side and the vertical side of the pixel electrode, the type and characteristics of the liquid crystal layer 3, and the inclination direction may also vary.

Next, the common electrode display panel 200 will be described with reference to FIGS. 3 to 6.

The light blocking member 220 is formed on the insulating substrate 210 made of transparent glass or the like. The light blocking member 220 has a plurality of openings facing the pixel electrode 190 and having substantially the same shape as the pixel electrode 190, and corresponding to the gate line 121 and the data line 171 and the thin film transistor. It is preferable that it consists of the part corresponding to.

A plurality of color filters 230 are also formed on the substrate 210 and are mostly located in an area surrounded by the light blocking member 230. The color filter 230 may extend in the vertical direction along the pixel electrode 190. The color filter 230 may display one of primary colors such as red, green, and blue.

An overcoat 250 is formed on the color filter 230.

The common electrode 270 formed of a transparent conductor such as ITO or IZO is formed on the overcoat 250.

The common electrode 270 has a plurality of sets of cutouts 71, 72a, and 72b.

The pair of cutouts 71, 72a, and 72b includes a center cutout 71, a lower cutout 72a, and an upper cutout 72b facing the pixel electrodes 190a and 190b. Each of the cutouts 71, 72a and 72b is disposed between adjacent cutouts 91, 92a and 92b of the pixel electrodes 190a and 190b or chamfered hypotenuses of the cutouts 92a and 92b and the first pixel electrode 190a. It is arranged in between. In addition, each of the cutouts 71, 72a, and 72b includes at least one diagonal line extending in parallel with the lower cutout 92a or the upper cutout 92b of the pixel electrode.

Each of the lower and upper cutouts 72a and 2b extends from the left side of the pixel electrode toward the upper or lower side and overlaps the side along the side of the pixel electrode from each end of the diagonal line. It includes a horizontal portion and a vertical portion forming an obtuse angle.

The central cutout 71 is a central horizontal portion extending from the left side of the pixel electrode in the horizontal direction, a pair of diagonal portions extending toward the right side of the pixel electrode at an oblique angle with the central horizontal portion at the end of the central horizontal portion, and From each end of the oblique portion, it extends overlapping with the right side along the right side of the pixel electrode and includes a vertical longitudinal portion forming an obtuse angle with the oblique portion.

The number and direction of the cutouts 71, 72a, and 72b may also vary depending on the design element, and the light blocking member 220 overlaps the cutouts 71, 72a, and 72b and is located near the cutouts 71, 72a, and 72b. Can block light leaks.

Vertical alignment layers 11 and 21 are coated on the inner surfaces of the two display panels 100 and 200, respectively, and polarizers 12 and 22 are provided on the outer surfaces thereof. The transmission axes of the two polarizing plates 12 and 22 are orthogonal, and one transmission axis is parallel to the gate line 121. In the case of a reflective liquid crystal display, one of the two polarizing plates 12 and 22 may be omitted.

A phase retardation film may be interposed between the display panels 100 and 200 and the polarizers 12 and 22 to compensate for the delay value of the liquid crystal layer 3, respectively. The phase retardation film has birefringence and serves to reversely compensate for the birefringence of the liquid crystal layer 3. As the retardation film, a uniaxial or biaxial optical film can be used, and in particular, a negative uniaxial optical film can be used.

The liquid crystal display may also include a polarizer 12 and 22, a phase retardation film, display panels 100 and 200, and a backlight unit for supplying light to the liquid crystal layer 3.

The liquid crystal layer 3 has negative dielectric anisotropy, and the liquid crystal molecules 310 of the liquid crystal layer 3 are aligned such that their major axes are perpendicular to the surfaces of the two display panels in the absence of an electric field. Therefore, incident light does not pass through the quadrature polarizers 12 and 22 and is blocked.

When a common voltage is applied to the common electrode 270 and a data voltage is applied to the pixel electrode 190, an electric field almost perpendicular to the surface of the display panel is generated. The liquid crystal molecules 310 try to change the direction of the long axis perpendicular to the direction of the electric field in response to the electric field. Meanwhile, the hypotenuses of the cutouts 71, 72a, 72b, 91, 92a, and 92b of the common electrode 270 and the pixel electrode 190 and the pixel electrode 190 parallel to the distorted electric field incline the liquid crystal molecules. Create a horizontal component that determines the direction. The horizontal component of the electric field is perpendicular to the sides of the cutouts 71, 72a, 72b, 91, 92a, 92b and the hypotenuse of the pixel electrode 190. In addition, the horizontal components of the main electric field at two opposite sides of the cutouts 71, 72a, 72b, 91, 92a, and 92b are opposite to each other.                     

Through these electric fields, the cutouts 71, 72a, 72b, 91, 92a, and 92b control the direction in which the liquid crystal molecules of the liquid crystal layer 3 are inclined. Liquid crystal molecules in each domain defined by adjacent cutouts 71, 72a, 76b, 91, 92a, and 92b or defined by the left hypotenuse of the cutouts 72a and 72b and the pixel electrode 190 may be cut out. Inclined in the direction perpendicular to the longitudinal direction of (71, 72a, 72b, 91, 92a, 92b). The two longest sides of each domain are substantially parallel to each other, and form approximately ± 45 degrees with the gate line 121, and most of the liquid crystal molecules in the domain are inclined in four directions.

The width of the cutouts 91, 92a, 92b, 71, 72a, 72b is preferably about 9 μm to about 12 μm.

At least one cutout 91, 92a, 92b, 71, 72a, 72b may be replaced with a protrusion (not shown) or a depression (not shown). The protrusions may be made of organic or inorganic materials and may be disposed above or below the field generating electrodes 190 and 270, and the width thereof is preferably about 5 μm to about 10 μm.

The shape and arrangement of the incisions 91, 92a, 92b, 71, 72a, 72b can be modified.

Meanwhile, when the inclination direction of the liquid crystal molecules 310 and the transmission axis of the polarizers 12 and 22 are 45 degrees, the highest luminance can be obtained. In the present embodiment, the inclination direction of the liquid crystal molecules 310 in all domains is the gate line. The gate line 121 is perpendicular or horizontal to the edges of the display panels 100 and 200 at an angle of 45 ° with the 121. Therefore, in the present exemplary embodiment, when the transmission axes of the polarizers 12 and 22 are attached to be perpendicular or parallel to the edges of the display panels 100 and 200, the highest luminance can be obtained and the polarizers 12 and 22 can be manufactured at low cost. Can be.

As described above, in the thin film transistor array panel according to the exemplary embodiment of the present invention, since the semiconductor in which the channel is formed is disposed in the boundary of the opaque gate line or data line, leakage current generated in the semiconductor due to external light can be minimized. Through this, the afterimage can be minimized.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (4)

Insulation board, A first signal line formed on the insulating substrate, A second signal line insulated from and intersecting the first signal line, A pixel electrode formed in each region defined by the crossing of the first signal line and the second signal line; A thin film transistor electrically connected to the first signal line, the second signal line, and the pixel electrode, the first semiconductor having a channel formed thereon; And the first semiconductor is disposed within a boundary between the gate electrode and the data line. In claim 1, The thin film transistor array panel further comprising a second semiconductor layer formed on the same layer as the first semiconductor layer and separated from the first semiconductor layer and disposed under the drain electrode of the thin film transistor. In claim 2, And the first semiconductor is linearly formed along the data line. In claim 1, The pixel electrode has a cutout.

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