KR20060070351A - Method of manufacturing thin film transistor array panel - Google Patents

Abstract

Forming a semiconductor film over the substrate, annealing the substrate, crystallizing the semiconductor film, forming a gate insulating film over the semiconductor film, forming a gate electrode and a sustain electrode over the gate insulating film, masking the gate electrode and the sustain electrode Implanting impurity ions into the semiconductor film to form a source region and a drain region and a channel region therebetween; and forming a source electrode connected to the source region and a drain electrode connected to the drain region. Method for manufacturing a transistor display panel.

Dehydrogenation, Polycrystalline Silicon, ANNEAL

Description

Method of manufacturing thin film transistor array panel {METHOD OF MANUFACTURING THIN FILM TRANSISTOR ARRAY PANEL}

1 is a layout view of a thin film transistor substrate according to an embodiment of the present invention,

FIG. 2 is a cross-sectional view of the thin film transistor of FIG. 1 taken along the line II-II ′,

3 is a cross-sectional view at a first stage of a method of manufacturing the thin film transistor array panel shown in FIGS. 1 and 2 according to one embodiment of the present invention;

4A is a layout view of a thin film transistor array panel in the next step of FIG. 3;

4B is a cross-sectional view of the thin film transistor of FIG. 4A taken along line IVb-IVb.

5 is a cross-sectional view showing the next step of FIG. 4B;

6 is a sectional view showing the next step of FIG. 5;

FIG. 7A is a layout view of a thin film transistor array panel in the next step of FIG. 6;

FIG. 7B is a cross-sectional view of the thin film transistor array panel of FIG. 7A taken along the line VIIb-VIIb,

8A is a layout view of a thin film transistor array panel in the next step of FIG. 7A.

FIG. 8B is a cross-sectional view of the thin film transistor array panel of FIG. 8A taken along a line VIIb-VIIb,

9A is a layout view of a thin film transistor array panel in the next step of FIG. 8A,                 

FIG. 9B is a cross-sectional view of the thin film transistor array panel of FIG. 9A taken along the line 'b-'b.

※ Explanation of symbols on main parts of drawing ※

110: insulating substrate 121: gate line

124: gate electrode 131: sustain electrode line

137: sustain electrode 140: gate insulating film

153: source region 154a: channel region

155: drain region 171: data line

173: source electrode 175: drain electrode

190: pixel electrode 150: semiconductor film

152 lightly doped drain region

The present invention relates to a method of manufacturing a thin film transistor array panel, and more particularly, to a method of manufacturing a polycrystalline silicon thin film transistor array panel.

In general, a thin film transistor (TFT) is used as a switching element for driving each pixel independently in a flat panel display such as a liquid crystal display or an organic light emitting display. The thin film transistor array panel including the thin film transistor includes a scan signal line (or gate line) for transmitting a scan signal to the thin film transistor and a data line for transmitting a data signal, in addition to the thin film transistor and the pixel electrode connected thereto.

The thin film transistor includes a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode connected to the pixel electrode, and a semiconductor layer positioned on the gate electrode between the source electrode and the drain electrode. The data signal from the data line is transferred to the pixel electrode in accordance with the scan signal from the. In this case, the semiconductor layer of the thin film transistor is made of polycrystalline silicon (polysilicon) or amorphous silicon (amorphous silicon).

Since polycrystalline silicon has a large electron mobility used for amorphous silicon, the use of a polycrystalline silicon thin film transistor enables high-speed driving. In addition, the driving circuit for driving the thin film transistor array panel may be formed on the substrate in the form of a thin film transistor without attaching a separate integrated circuit chip.

On the other hand, a semiconductor layer made of polycrystalline silicon is laminated with amorphous silicon on an insulating substrate and crystallized by a method such as laser annealing, furnace annealing, or sequential lateral solidification (SLS). Form.

In order to do this, first, an annealing process is applied to heat the transparent insulating substrate, and the substrate is cleaned using ozone (O3). Next, a blocking film is formed on the substrate and a hydrogenated amorphous silicon is deposited thereon to form a semiconductor film. At this time, since the deposited semiconductor film contains a large amount of about 3 to 20% of hydrogen, an explosion of hydrogen gas occurs during the crystallization process, which may cause defects in the semiconductor film.

Therefore, the dehydrogenation process of a semiconductor film advances before a crystallization work process progresses.

In addition, an oxide film (SiO 2) is formed on the semiconductor film before the crystallization process to prevent the heat supplied to crystallize the semiconductor film using oxygen (O 2) plasma.

When this operation is completed, ozone (O3) cleaning is performed, and the semiconductor film is crystallized to form a semiconductor layer.

As described above, a process is complicated because a dehydrogenation process and a separate process of forming an oxide film are required to form a semiconductor layer. In addition, even when the dehydrogenation process is carried out, a small amount of hydrogen still remains, which may degrade the performance of the thin film transistor.

Accordingly, the technical problem of the present invention is to provide a method of manufacturing a thin film transistor array panel which can increase the productivity of the thin film transistor by reducing the process steps for forming the semiconductor layer.

A method of manufacturing a thin film transistor array panel according to the present invention includes forming a semiconductor film on a substrate, annealing the substrate, crystallizing the semiconductor film, forming a gate insulating film on the semiconductor film, and a gate electrode on the gate insulating film. And forming a sustain electrode, implanting impurity ions using the gate electrode and the sustain electrode as a mask to form a source region and a drain region and a channel region therebetween in the semiconductor film, and connecting the source region. Forming a source electrode and a drain electrode connected to the drain region.

In the annealing step, hydrogen of the semiconductor film may be removed.

An oxide layer may be formed on the semiconductor layer in the annealing process.

The method may further include forming a passivation layer on the sustain electrode and the gate electrode, and forming a pixel electrode connected to the drain electrode on the passivation layer.

The method may further include forming a low concentration doped region by implanting ions between the channel region and the source and drain regions at a concentration lower than the ion implantation concentration when the source and drain regions are formed.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

A method of manufacturing a polysilicon thin film transistor array panel according to an exemplary embodiment of the present invention will now be described in detail with reference to FIGS. 1 and 2.

FIG. 1 is a layout view of a thin film transistor array panel manufactured by a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment, and FIG. 2 is a cross-sectional view taken along line II-II of the thin film transistor of FIG.

A blocking film 111 made of silicon oxide (SiO 2) or silicon nitride (SiN x) is formed on the transparent insulating substrate 110. The blocking film 111 may have a multilayer structure.

An island type semiconductor 151 made of polycrystalline silicon is formed on the blocking layer 111. The island-type semiconductor 151 includes an intrinsic region containing conductive impurities and an intrinsic region containing almost no conductive impurities. The impurity region includes a heavily doped region having a high impurity concentration; There is a lightly doped region with low impurity concentrations. The intrinsic region includes a channel region 154 and a storage region 157, and the high concentration impurity region is separated from each other around the channel region 154. ) And drain regions 155 and the like, and the low concentration impurity regions 152 and 156 are located between the intrinsic regions 154 and 157 and the high concentration impurity regions 153 and 155 and have a narrow width. In particular, the low concentration impurity region 152 located between the source region 153 and the channel region 154 and between the drain region 155 and the channel region 154 is referred to as a lightly doped drain region (LDD region). do.

Examples of the conductive impurity include P-type impurities such as boron (B) and gallium (Ga) and N-type impurities such as phosphorus (P) and arsenic (As). The lightly doped drain regions 152 and 156 may prevent a leakage current or a punch through phenomenon of the thin film transistor from occurring and may be replaced with an offset region containing no impurities.

A gate insulating layer 140 made of silicon nitride or silicon oxide is formed on the island semiconductor 151.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 extending in the horizontal direction are formed on the gate insulating layer 140.

The gate line 121 transmits a gate signal and includes a gate electrode 124 protruding downward and overlapping the channel region 154a of the semiconductor 151. The gate electrode 124 may also overlap the lightly doped drain region 152. One end portion of the gate line 121 may have a large area in order to connect to another layer or an external driving circuit, and when a gate driving circuit (not shown) generating a gate signal is integrated on the substrate 110. The gate line 121 may be directly connected to the gate driving circuit.

The storage electrode line 131 receives a predetermined voltage such as a common voltage applied to a common electrode (not shown), and extends up and down to overlap the storage region 157a of the semiconductor 151. 137).

The gate line 121 and the storage electrode line 131 may be formed of aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, copper-based metal such as copper (Cu) or copper alloy, Molybdenum-based metals such as molybdenum (Mo) and molybdenum alloy, chromium (Cr), tantalum (Ta), titanium (Ti), tungsten (W) and the like. However, the gate line 121 and the storage electrode line 131 may have a multilayer film structure including two conductive films (not shown) having different physical properties. One of these conductive films is a low resistivity metal such as an aluminum-based metal, a silver-based metal, or a copper-based metal so as to reduce signal delay or voltage drop of the gate line 121 and the storage electrode line 131. It may be made of a metal. The other conductive layer may be made of a material having excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metal, chromium, tantalum, or titanium. A good example of such a combination is a chromium bottom film and an aluminum top film, and an aluminum bottom film and a molybdenum top film.

Side surfaces of the gate line 121 and the storage electrode line 131 are inclined with respect to the surface of the substrate 110 so that the upper thin film can be smoothly connected.

An interlayer insulating film 160 is formed on the gate line 121, the storage electrode line 131, and the gate insulating layer 140. The interlayer insulating layer 160 is an organic material having excellent planarization characteristics and photosensitivity, a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or the like formed by plasma chemical vapor deposition, or It may be formed of an inorganic material such as silicon nitride. A plurality of contact holes 163 and 165 exposing the source region 153 and the drain region 155 are formed in the interlayer insulating layer 160 and the gate insulating layer 140, respectively.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the interlayer insulating layer 160.

The data line 171 transmitting the data signal mainly includes a plurality of source electrodes 173 extending in the vertical direction to intersect the gate line 121 and connected to the source region 153 through the contact hole 163. . One end of the data line 171 may have a large area in order to connect to another layer or an external driving circuit. Line 171 may be directly connected to the data driving circuit.

The drain electrode 171 is separated from the source electrode 173 and is connected to the drain region 155 through the contact hole 165.

The data line 171 and the drain electrode 175 may be made of a refractory metal such as molybdenum, chromium, tantalum, titanium, or an alloy thereof. However, these may also have a multilayer film structure including a conductive film having a low resistance and a conductive film having good contact characteristics. Examples of the multilayer film structure include a triple film of molybdenum film, aluminum film, and molybdenum film in addition to the above-described double film of chromium lower film and aluminum upper film or aluminum lower film and molybdenum upper film.

Side surfaces of the data line 171 and the drain electrode 175 may also be inclined with respect to the substrate 110 surface.

A passivation layer 180 is formed on the data line 171, the drain electrode 175, and the interlayer insulating layer 160. The passivation layer 180 may be made of the same material as the interlayer insulating layer 160 and has a plurality of contact holes 185 exposing the drain electrode 175.

A pixel electrode 190 made of a transparent conductive material such as IZO or ITO or an opaque reflective conductive material such as aluminum or silver is formed on the passivation layer 180.

The pixel electrode 190 is connected to the drain electrode 175 connected to the drain region 155 through a contact hole to receive a data voltage from the drain region 155 and the drain electrode 175.

The pixel electrode 190 to which the data voltage is applied generates an electric field together with the common electrode to which the common voltage is applied, thereby determining the direction of the liquid crystal molecules of the liquid crystal layer (not shown) between the two electrodes or the light emitting layer between the two electrodes. Current) to emit light.

In the case of the liquid crystal display, the pixel electrode 190 and the common electrode form a capacitor (hereinafter referred to as a liquid crystal capacitor) to maintain the applied voltage even after the thin film transistor is turned off. For this purpose, another capacitor connected in parallel with the liquid crystal capacitor is provided, which is called a storage capacitor. The storage capacitor is made by overlapping the storage electrode line 131 including the pixel electrode 190 and the storage region and the storage electrode.

When the passivation layer 180 is formed of an organic material having a low dielectric constant, the pixel electrode 190 may be overlapped with the data line 171 and the gate line 121 to improve the aperture ratio.

Next, a method of manufacturing the thin film transistor array panel illustrated in FIGS. 1 and 2 will be described in detail with reference to FIGS. 1 and 2, together with FIGS. 3 to 9B.

 3 is a cross-sectional view at a first stage of the method of manufacturing the thin film transistor array panel shown in FIGS. 1 and 2 according to one embodiment of the present invention, and FIG. 4A is a layout view of the thin film transistor array panel at the next stage of FIG. 4B is a cross-sectional view of the thin film transistor of FIG. 4A taken along line IVb-IVb, FIG. 5 is a cross-sectional view showing the next step of FIG. 4B, FIG. 6 is a cross-sectional view showing the next step of FIG. 5, and FIG. 7A 6 is a layout view of a thin film transistor array panel in the next step of FIG. 6, and FIG. 7B is a cross-sectional view of the thin film transistor array panel of FIG. 7A taken along the line VII-b of FIG. 7A, and FIG. 8B is a cross-sectional view of the thin film transistor array panel of FIG. 8A taken along the line Bb-Vb, FIG. 9A is a layout view of the thin film transistor array panel in the next step of FIG. 8A, and FIG. A cross-sectional view cut film transistor panel according to Ⅸb-Ⅸb line.

First, as shown in FIG. 3, the transparent insulating substrate 110 is cleaned initially and the ozone (O3) is cleaned, and then the blocking film 111 is formed thereon. Then, the semiconductor film 150 made of amorphous silicon is formed by a method such as plasma chemical vapor deposition (PECVD). At this time, the semiconductor film 150 may contain about 3 to 20% hydrogen.

Next, the insulating substrate 110 is annealed at a temperature of about 550 ° C. Annealing processes include furnace annealing and rapid thermal annealing (RTA), and UV lamp annealing.

At this time, hydrogen contained in the semiconductor film 150 is almost released, and at the same time, a thin oxide film SiO2 (not shown) is formed on the semiconductor film 150.

When this operation is completed, the ozone (O3) cleaning operation is performed again.

Next, as shown in FIGS. 4A to 4B, the semiconductor film 150 is subjected to laser annealing or furnace annealing using an excimer laser, a continuous wave laser, or a furnace annealing. The semiconductor film 150 is crystallized by a sequential lateral solidification (SLS) method and then patterned to form a plurality of island-like semiconductors 151. At this time, the oxide film serves to shorten the time of the crystallization operation by preventing the heat supplied to crystallize the semiconductor film 150.

Next, as shown in FIG. 5, an insulating material such as silicon nitride or silicon oxide is deposited to a thickness of 500 to 3,000 Å by a chemical vapor deposition method to form a gate insulating layer 140, and a gate is formed on the gate insulating layer 140. The conductive layer 120 is formed. A mask layer made of chromium is deposited on the gate conductive layer 120, and a photoresist pattern is formed on the mask layer. Then, patterns 58 and 59 are formed using the photosensitive film pattern as a mask. At this time, the mask pattern 59 is coincident with or slightly wider than the holding region 157.

6, the gate conductive layer 120 is patterned using the mask patterns 58 and 59 as masks to form the plurality of gate lines 121 and the sustain electrodes 137 including the gate electrodes 124. A plurality of sustain electrode lines 131 including () are formed. At this time, the etching time of the gate conductive layer 120 is lengthened so that the width of the gate line 121 and the storage electrode line 131 is smaller than the width of the mask patterns 58 and 59.

Here, the mask patterns 58 and 59 are used as ion implantation masks to inject a high concentration of n-type or p-type impurity ions into the island-type semiconductor 151 to include a plurality of high-concentration impurities including the source region 153 and the drain region 155. Form an area. At this time, portions under the mask patterns 58 and 59 become intrinsic regions 154 and 157 into which impurities are not injected.

Then, as shown in Figs. 7A to 7B, after removing the mask patterns 58 and 59, the gate line 121 and the storage electrode line 131 are used as masks to form n-type or p-type impurities at low concentration. Inject. In this way, the region under the gate electrode 124 positioned between the source region 153 and the drain region 155 is the channel region 154 and the peripheral regions 152 and 156 of the storage region 157 are lightly doped regions. Becomes

Subsequently, as shown in FIGS. 8A to 8B, the plurality of contact holes 163 exposing the source region and the drain region 153 and 155 by stacking the photo interlayer insulating layer 160 on the entire surface of the substrate 110 and etching the photo, respectively. , 165).

Next, as shown in FIGS. 9A to 9B, the source electrode 173 is connected to the source region 153 and the drain region 155 through the contact holes 163 and 165 on the interlayer insulating layer 160. A plurality of data lines 171 and a plurality of drain electrodes 175 are formed.

Thereafter, the passivation layer 180 is stacked and photo-etched to form a plurality of contact holes 185 exposing the drain electrode 175.                     

1 and 2, the plurality of pixel electrodes 190 connected to the drain electrode 175 through the contact hole 185 with a transparent conductive material such as IZO, ITO, or the like on the passivation layer 180. Form.

In the method of manufacturing a thin film transistor according to the present invention, dehydrogenation and an oxide film may be formed through an annealing process of an insulating substrate, thereby reducing process work.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the invention.

Claims (5)

Forming a semiconductor film on the substrate, Annealing the substrate, Crystallizing the semiconductor film, Forming a gate insulating film on the semiconductor film; Forming a gate electrode and a sustain electrode on the gate insulating layer; Implanting impurity ions using the gate electrode and the sustain electrode as a mask to form a source region and a drain region and a channel region therebetween in the semiconductor film; and Forming a source electrode connected to the source region and a drain electrode connected to the drain region. In claim 1, A method of manufacturing a thin film transistor array panel in which hydrogen of the semiconductor film is removed in the annealing step. The method of claim 1 or 2, And an oxide film is formed on the semiconductor film in the annealing process. In claim 1, Forming a passivation layer on the sustain electrode and the gate electrode, and forming a pixel electrode connected to the drain electrode on the passivation layer. In claim 1, And forming a low concentration doped region between the channel region and the source and drain regions by implanting ions at a concentration lower than the ion implantation concentration at the time of forming the source and drain regions.

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