KR20060069026A - Command input device of semiconductor memory device - Google Patents

Abstract

The present invention relates to a command input device of a semiconductor memory device. The command input device of the semiconductor memory device according to the present invention includes a plurality of flip-flops and a command decoder. The plurality of flip-flops receive a plurality of external command signals, respectively. Each of the plurality of flip-flops generates a first signal in synchronization with a first transition of an internal clock and generates a second signal in synchronization with a second transition later than the first transition. The command decoder outputs an internal command signal in response to the first and second signals generated in the plurality of flip-flops. Herein, the combination of the first signals may prevent an invalid internal command signal from being generated. According to the present invention, since the internal clock does not have to be delayed to prevent the generation of an invalid internal command signal, the operation speed of the semiconductor memory device can be increased.

Description

Command input device of semiconductor memory device {COMMAND INPUT DEVICE OF SEMICONDUCTOR MEMORY DEVICE}

1 is a block diagram showing a command input device according to the prior art.

FIG. 2 is a timing diagram illustrating the operation of the command input device shown in FIG. 1.

FIG. 3 is a timing diagram illustrating an operation of delaying an internal clock in the command input device shown in FIG. 1.

4 is a block diagram showing a command input device according to a preferred embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating an internal configuration of the flip flop illustrated in FIG. 4.

FIG. 6 is a timing diagram illustrating an operation of the command input device shown in FIG. 4.

7 is a timing diagram illustrating an operation of generating a normal valid internal command signal.

* Description of the symbols for the main parts of the drawings *

1, 4: Command input device 100, 400: Command decoder

110, 410: clock buffer 120, 130, 420, 430: command buffer

140, 440: delay circuit 150, 160, 450, 460: flip-flop

The present invention relates to a semiconductor memory device, and more particularly, to a command input device of a semiconductor memory device.

A semiconductor memory device is a memory device that stores data and can be read out when needed. Command input devices can be largely divided into random access memory (RAM) and read only memory (ROM). RAM is volatile memory that loses its stored data when power is lost. ROM is a nonvolatile memory in which stored data is not destroyed even when a power supply is cut off. RAM includes Dynamic RAM (DRAM), Static RAM (SRAM), and the like. The ROM includes a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EPROM), a flash memory, and the like.

In a semiconductor memory device such as a DRAM, a command decoder that receives various external command signals and generates corresponding internal command signals is required. In particular, in SDRAM (Synchronous DRAM), all external command signals are input in synchronization with an external clock. If the delay time is short from the time when the external command signal is input to the time when the internal command signal is input, the operation of the SDRAM will be faster. That is, since the delay time affects the DRAM AC parameters (e.g., tAA; access time from the read command signal to the first valid data output), it is necessary to reduce the delay time for the high speed operation DRAM. The conventional command input device has a problem in that a delay time from an external command signal to an internal command signal is increased because the command decoder is configured with static combination logic.

Generally, the DRAM includes four external commands: a chip select signal (CS), a write enable signal (WE), a low address strobe (RAS), and a column address strobe (CAS). Has a signal. Various internal command signals are generated by the combination of the external command signals. For example, the active command signal is a case where CS is high (hereinafter, H), WE is low (hereafter, L), RAS is H, and CAS is L. The read command signal is H for CS, L for WE, L for RAS, and H for CAS.

1 is a block diagram showing a command input device according to the prior art. Referring to FIG. 1, the command input device 1 includes a clock buffer 110 that receives an external clock ECLK, buffers it, and generates an internal clock ICLK. The internal clock ICLK generated by the clock buffer 110 is delayed for a predetermined time while passing through the delay circuit 140. The first command buffer 120 receives and buffers the first external command signal ECMD1 and provides the buffered signal to the first flip-flop 150. The second command buffer 130 receives and buffers the second external command signal ECMD2 and provides the buffered signal to the second flip-flop 160. The first and second flip-flops 150 and 160 receive signals provided from the first and second command buffers 120 and 130 in synchronization with an internal clock ICLK generated by the clock buffer 110. . The command decoder 100 receives an internal command signal ICMD in response to an internal clock ICLK provided by the delay circuit 140 and signals A and B provided by the first and second flip-flops 150 and 160. Occurs.

The command decoder 100 includes a PMOS transistor MP1, NMOS transistors MN1, MN2, and MN3, a NOR gate 101, and an inverter 102. The PMOS transistor MP1 and the NMOS transistors MN1, MN2, and MN3 are connected in series. The internal clock ICLK is simultaneously input to the gates of the PMOS transistor MP1 and the first NMOS transistor MN1. The drains of the PMOS transistor MP1 and the first NMOS transistor MN1 are connected to the inverter 102. The inverter 102 outputs an internal command signal ICMD. The gate of the second NMOS transistor MN2 receives an A signal provided from the first flip-flop 150. The NOR gate 101 has a first input terminal receiving a B signal provided from the second flip-flop 160 and a second input terminal connected to a ground voltage. The gate of the third NMOS transistor MN3 receives the C signal provided from the NOR gate 101.

FIG. 2 is a timing diagram illustrating the operation of the command input device shown in FIG. 1. Referring to FIG. 2, an external clock ECLK and external command signals ECMD1 and ECMD2 are input. For example, it is assumed that the combination of the external command signals ECMD1 and ECMD2 means a write operation. In addition, it is assumed that the external clock ECLK is not delayed in the delay circuit 140.

The first and second flip-flops 150 and 160 receive the first and second external command signals ECMD1 and ECMD2, respectively, and generate A and B signals in synchronization with the external clock ECLK. The B signal is delayed by t1 by the NOR gate 101 and inverted to become a C signal.

Referring to FIG. 2, when the internal clock ICLK transitions from L to H, since both the A signal and the C signal are in the H state, the NMOS transistors MN1, MN2, and MN3 are all turned on. Therefore, as shown in FIG. 2, an internal command signal that causes a malfunction, that is, an invalid internal command signal Invalid ICMD is generated.

FIG. 3 is a timing diagram illustrating a delay of an internal clock to eliminate an invalid internal command signal generated in FIG. 2. The delay circuit 140 delays the internal clock ICLK for a predetermined time. The delayed internal clock is input after being delayed by a predetermined time t2 from the input point of time of the C signal which is input to the NMOS transistors MN2 and MN3 at the latest. Therefore, since the internal clock ICLK is in the L state when the A and C signals are in the H state, an invalid internal command signal is not generated as shown in FIG. 3.

However, since the input of the internal clock ICLK is delayed, the generation of the internal command signal is delayed, and thus, the overall operation speed of the semiconductor memory device such as tAA is slowed.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a command input device capable of speeding up the operation speed of a semiconductor memory device without generating an invalid internal command signal.

The command input device of the semiconductor memory device according to the present invention includes a plurality of flip-flops and a command decoder. The plurality of flip-flops receive a plurality of external command signals, respectively. Each of the plurality of flip-flops generates a first signal in synchronization with a first transition of an internal clock and generates a second signal in synchronization with a second transition later than the first transition. The command decoder outputs an internal command signal in response to the first and second signals generated in the plurality of flip-flops. Herein, the combination of the first signals may prevent an invalid internal command signal from being generated.

In example embodiments, each of the plurality of flip-flops may include: a first latch configured to latch a first signal in synchronization with the first transition; And a second latch connected in series with the first latch and latching a second signal in synchronization with the second transition.

In an embodiment, the command decoder may include: a driving circuit configured to output an internal command signal in response to an internal clock; A switch circuit turned on or off in response to the second signal; And a determination circuit for preventing generation of an invalid internal command signal in response to the first signal. Here, the driving circuit includes a PMOS transistor for supplying charge in response to the internal clock; An NMOS transistor connected in series with the PMOS transistor and discharged in response to the internal clock; And an inverter connected between the connection point and the output terminal of the PMOS and NMOS transistors. The decision circuit may include a NAND gate configured to receive the first signal; And a switch circuit turned on or off in response to the output of the NAND gate.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

4 is a block diagram showing a command input device according to a preferred embodiment of the present invention. Referring to FIG. 4, the command input device 4 includes a clock buffer 410 for receiving an external clock ECLK, a first command buffer 420 for receiving a first external command signal, and a second external command signal. It includes a second command buffer 430 that receives the input.

The clock buffer 410 buffers the external clock ECLK and generates an internal clock ICLK. The internal clock ICLK may be delayed in the delay circuit 440 for a predetermined time. The first and second command buffers 420 and 430 buffer the first and second external command signals ECMD1 and ECMD2.

The command input device 4 further includes first and second flip-flops 450 and 460 for receiving buffered first and second external command signals, respectively. The first flip-flop 450 generates the A signal and the A 'signal in synchronization with the internal clock ICLK, and the second flip-flop 460 is the B signal and B' signal in synchronization with the internal clock ICLK. Occurs. The A 'and B' signals are output from a latch which is an intermediate node of the first and second flip-flops 450 and 460, and are output before the A and B signals. The A 'and B' signals are for preventing generation of an invalid internal command signal without delaying the internal clock ICLK. Meanwhile, the first and second flip-flops 450 and 460 perform the same function. An internal configuration and an operation principle of the first flip-flop 450 are described in detail with reference to FIG. 5 described later.                     

 Referring back to FIG. 4, the command input device 4 further includes a command decoder 400. The command decoder 400 receives an internal clock ICLK and A, A ', B, and B' signals and generates an internal command signal ICMD. The command decoder 400 includes a driving circuit 401, a NOR gate 401, and a decision circuit 403.

The driving circuit 401 includes a PMOS transistor P1, a first NMOS transistor N1, and an inverter INV1. The PMOS transistor P1 and the first NMOS transistor N1 are connected in series. The internal clock ICLK is simultaneously input to the gates of the PMOS transistor P1 and the first NMOS transistor N1. The source of the PMOS transistor P1 receives a power supply voltage. The drain of the PMOS transistor P1 and the first NMOS transistor N1 is connected to the inverter INV1. The inverter INV1 outputs an internal command signal ICMD. The driving circuit 401 generates an internal command signal ICMD in response to the internal clock ICLK.

The second NMOS transistor N2 has a gate that receives an A signal and a drain connected to a source of the first NMOS transistor N1.

The NOR gate 402 has a first input terminal for receiving a B signal and a second input terminal connected to a ground voltage. The gate of the third NMOS transistor N3 receives the C signal provided from the NOR gate 402. The source of the third NMOS transistor N3 is connected to ground.

The decision circuit 403 is connected between the second and third NMOS transistors N2 and N3, and the second and third NMOS transistors N2 and N3 are connected in response to signals A 'and B'. To be electrically connected or disconnected. The determination circuit 403 is a circuit for preventing the generation of an invalid internal command signal in advance. For example, the decision circuit 403 may be implemented with a NAND gate G1 and a fourth NMOS transistor N4 as shown in FIG. 4. The NAND gate G1 generates the L signal of the L level only when the A 'and B' signals are both at the H level. The gate of the fourth NMOS transistor N4 receives the D signal provided from the NAND gate G1. The drain of the fourth NMOS transistor N4 is connected to the source of the second NMOS transistor N2, and the source of the fourth NMOS transistor N4 is connected to the drain of the third NMOS transistor N3.

FIG. 5 is a circuit diagram illustrating an internal configuration of the first flip-flop illustrated in FIG. 4. Referring to FIG. 5, the first flip-flop 450 includes pass transistors 451 and 453 and latches 452 and 454.

The first pass transistor 451 transfers the input signal IN to the first latch 452 in response to the clock signal CLK. The output terminal L of the first latch 452 outputs an A 'signal. Meanwhile, the second pass transistor 453 transfers the output of the first latch 452 to the second latch 454 in response to the clock signal CLK. The output terminal OUT of the second latch 454 outputs an A signal.

The first flip-flop 450 first generates the A 'signal before the A signal is output. Similarly, the second flip-flop 460 first generates the B 'signal before the B signal is output.                     

FIG. 6 is a timing diagram illustrating an operation of the command input device shown in FIG. 4. Referring to FIG. 6, an external clock ECLK and external command signals ECMD1 and ECMD2 are input. For example, it is assumed that the combination of the external command signals ECMD1 and ECMD2 means a write operation. It is assumed that the internal clock ICLK is not delayed by the delay circuit 440.

The first and second flip-flops 450 and 460 receive the first and second external command signals ECMD1 and ECMD2, respectively, and generate A and B signals in synchronization with the external clock ECLK. The B signal is delayed by t3 by the NOR gate 402 and inverted to become a C signal.

Referring to FIG. 6, it can be seen that A 'and B' signals are generated before the A and B signals are generated. This is because the A 'and B' signals are output from the first latch 452 of the flip-flop. The D signal is in the L level state while the signals A 'and B' are both in the H level state. The fourth NMOS transistor N4 is turned off in the period where the D signal is in the L level. Therefore, there is no need to delay the internal clock ICLK. That is, an invalid internal command signal as shown in FIG. 2 is not generated without a delay of the internal clock ICLK.

7 is a timing diagram illustrating an operation of generating a normal valid internal command signal. It is assumed that the combination of the external command signals ECMD1 and ECMD2 means a read operation. It is assumed that the internal clock ICLK is not delayed by the delay circuit 440.                     

Referring to FIG. 7, the A 'and B' signals generated before the A and B signals are output can be seen. In the period where A 'is at the H level, the B' signal is at the L level. At this time, the D signal is in the H level state. That is, when the combination of the external command signals ECMD1 and ECMD2 is shown in FIG. 7, the D signal is always in the H level state, and thus the fourth NMOS transistor N4 is always turned on. Therefore, the command decoder 400 outputs an internal command signal for a read operation in response to the C signal input most recently.

According to the command input device of the semiconductor memory device according to the present invention, it is possible to prevent the generation of an invalid internal command signal without delaying the internal clock. Therefore, the operation speed of the semiconductor memory device can be increased by improving characteristics such as tAA.

On the other hand, in the detailed description of the present invention has been described with respect to specific embodiments, various modifications are of course possible without departing from the scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

As described above, since the command input device of the semiconductor memory device according to the present invention does not have to delay the internal clock to prevent generation of an invalid internal command signal, the operation speed of the semiconductor memory device can be increased.

Claims (6)

A plurality of flip-flops each receiving a plurality of external command signals; Each of the plurality of flip-flops generates a first signal in synchronization with a first transition of an internal clock and generates a second signal in synchronization with a second transition later than the first transition; And a command decoder configured to output an internal command signal in response to first and second signals generated in the plurality of flip-flops. The method of claim 1, And the combination of the first signals prevents an invalid internal command signal from being generated. The method of claim 1, Each of the plurality of flip-flops, A first latch for latching a first signal in synchronization with the first transition; And And a second latch connected in series with the first latch and latching a second signal in synchronization with the second transition. The method of claim 1, The command decoder, A driving circuit outputting an internal command signal in response to an internal clock; A switch circuit turned on or off in response to the second signal; And And a decision circuit for preventing generation of an invalid internal command signal in response to the first signal. The method of claim 4, wherein The drive circuit, A PMOS transistor supplying charge in response to the internal clock; An NMOS transistor connected in series with the PMOS transistor and discharged in response to the internal clock; And And an inverter connected between an output point and a connection point of the PMOS and NMOS transistors. The method of claim 4, wherein The decision circuit may include a NAND gate configured to receive the first signal; And And a switch circuit turned on or off in response to an output of the NAND gate.

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