KR20060067050A - Fabricating method of organic electroluminenscence device - Google Patents

Abstract

The present invention relates to a method for manufacturing an organic light emitting display device, by applying a lift-off method to reduce the number of existing 7 to 8 mask (5) mask process to 5 to 6 mask on a CMOS basis, The present invention relates to a method of manufacturing an organic light emitting display device capable of realizing material cost and manufacturing cost reduction due to reduced tact time and process mask number.

Organic light emitting device, lift-off, back exposure, mask reduction

Description

Fabrication Method of Organic Electroluminescent Device {Fabricating Method of Organic Electroluminenscence Device}

1 is a cross-sectional view of an organic light emitting display device having a bottom gate type thin film transistor according to the related art.

2A to 2H are cross-sectional views illustrating an organic light emitting display device having a bottom gate type thin film transistor and a method of manufacturing the same.

<Description of the symbols for the main parts of the drawings>

200 substrate 210 gate electrode

220: gate insulating film 230: semiconductor layer

250: first electrode 280: source / drain electrode

285 passivation film 290 pixel definition film (PDL)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an organic light emitting display device, and more specifically, to a conventional organic light emitting device employing a lift-off method to a organic light emitting device employing a bottom gate type thin film transistor. The present invention relates to a method of manufacturing an organic light emitting display device, which can reduce the number of mask processes of 7 to 8 to 5 to 6 masks.

Among flat panel display devices, organic electroluminescence devices (OLEDs) are self-luminous and have a wide viewing angle and a fast response time of 1 ms or less, thin thickness, low manufacturing cost, and high contrast. And other properties.

The organic light emitting device includes an organic light emitting layer between an anode electrode and a cathode electrode, so that holes supplied from the anode electrode and electrons received from the cathode electrode combine in the organic light emitting layer to form an exciton which is a hole-electron pair, and the exciton is bottomed. The light emitted by the energy generated when returning to the state.

In general, organic light emitting diodes are equipped with a thin film transistor for each pixel to provide a stable luminance regardless of the number of pixels of the organic light emitting diode, and thus exhibit stable luminance and low power consumption. It has the advantage of being advantageous.

1 is a cross-sectional view of an organic light emitting display device having a conventional bottom gate type thin film transistor.

Referring to FIG. 1, a conventional organic light emitting diode having a bottom gate type thin film transistor includes a gate electrode 110 on a substrate 100 having a first thin film transistor region a and a second thin film transistor region b. After the lamination, the photoresist (PR) pattern is patterned using a first mask.

A gate insulating layer 120 is formed on the gate electrode 110, and source / drain regions 130a and 130c, a channel region 130b, and an LDD source / drain region 130d and 130e are disposed on the gate insulating layer. The semiconductor layer 130 is formed by laminating and patterning the semiconductor layer 130 simultaneously with the gate insulating film using a second mask.

Subsequently, phosphorus (P) and arsenic (As) are applied to the semiconductor layer 130 using a third mask in a region corresponding to the channel region 130b on the semiconductor layer 130 of the first thin film transistor region a. ), N-type impurities such as antimony (Sb) and bismuth (Bi) are implanted to form an NMOS.

Subsequently, N-LDD (Lightly Doped Drain) impurities are implanted into the channel region 130b of the semiconductor layer 130 of the first thin film transistor regions a and b using a fourth mask. The source / drain regions of the first thin film transistor region (a) through the N-LDD impurity implantation are the source / drain regions 130a and 130c implanted with n-type impurities and the source / drain regions implanted with N-LDD impurities ( 130d, 130e).

Subsequently, p-type impurities such as boron (B), aluminum (Al), gallium (Ga), and indium (In) are implanted into the semiconductor layer 130 of the second thin film transistor region (b) using a fifth mask. Thus, source / drain regions 130f and 130g are defined to form a PMOS.

As a result, the NMOS source / drain regions 130a, 130c, 130d and 130e, the PMOS source / drain regions 130f and 130g, and the channel region 130b of the semiconductor layer 130 are defined, and the organic light emitting diode is It is formed of a CMOS (Complementaty Metal Oxide Semiconductor) having both NMOS and PMOS.

Subsequently, the source / drain electrodes 145a and 145b are stacked on the semiconductor layers 130 of the first and second thin film transistor regions a and b and then etched using the sixth mask to form the semiconductor layer 130. Source / drain electrodes 145a and 145b contacting the source / drain regions 130a, 130c, 130d, 130e, 130f, and 130g are patterned and formed.

The gate electrode 110, the semiconductor layer 130, and the source / drain electrodes 145a and 145b form a thin film transistor. The thin film transistor is a CMOS thin film transistor including an NMOS thin film transistor and a PMOS thin film transistor.

Subsequently, the first electrode 150 is stacked and patterned using a seventh mask to contact one of the source / drain electrodes 145a and 145b. The first electrode is formed of a transparent electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO).

The passivation layer 160 is formed over the entire surface of the source / drain electrodes 145a and 145b and the first electrode 150. After the pixel definition layer 170 is stacked on the passivation layer 160, the pixel definition layer is formed to have an opening that exposes the first electrode through the back exposure. At this time, the passivation film 160 is patterned by etching.

An organic layer (not shown) including at least an organic light emitting layer is formed on the first electrode 150 exposed in the opening. The organic layer may include a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL) in addition to an organic emission layer (EML). Electron Injection Layer) may further include one or more of the layers consisting of.

Subsequently, a second electrode (not shown) including the organic layer is formed over the entire surface of the substrate. The bottom gate type organic light emitting display device is completed by encapsulating the substrate formed up to the second electrode with the upper substrate in a conventional manner.

In the conventional CMOS organic light emitting display device having a bottom gate type thin film transistor, seven masks are applied in a manufacturing process, which causes a long process tack time, a material cost, and a manufacturing cost. .

The technical problem to be achieved by the present invention is to solve the above-described problems of the prior art, by applying a lift-off method to the bottom gate organic light emitting device, the conventional 7 ~ 8 mask (based on CMOS) By reducing the number of mask process to 5 to 6 mask, it is to provide a method of manufacturing an organic light emitting device that can realize a material cost and a manufacturing cost due to the reduction of the process tact time and the number of process masks.

In order to achieve the above technical problem, the present invention

Providing a substrate having first and second thin film transistor regions, patterning a gate electrode on the substrate, patterning a semiconductor layer on the gate electrode, and forming a semiconductor layer on the first thin film transistor region. After implanting the n-type impurity, the first electrode is stacked on the semiconductor layer, and then patterned by using a lift-off method, and then the p-type impurity is injected into the semiconductor layer of the second thin film transistor region. The first electrode is stacked on the semiconductor layer and then patterned by a lift-off method. The source / drain electrodes contacting the first electrodes of the first and second thin film transistor regions are patterned to form the source / drain electrodes. A pixel defining layer is formed by backside exposure so as to have an opening on the drain electrode, and is disposed on the first electrode exposed through the opening. Forming an organic layer including the organic light-emitting layer and, and provides a method for producing an organic electroluminescent device comprising: forming a second electrode on top of the organic layer.

Hereinafter, with reference to the accompanying drawings of the present invention will be described in more detail.

2A to 2H are cross-sectional views illustrating an organic light emitting display device having a bottom gate type thin film transistor according to the present invention and a method of manufacturing the same.

2A to 2H, an organic light emitting diode employing a bottom gate type thin film transistor according to the present invention includes a substrate 200 having a first thin film transistor region a and a second thin film transistor region b. To provide. The substrate 200 is a transparent substrate such as glass, plastic, or quartz. The gate electrode 210 is stacked on the substrate 200 of the first thin film transistor region a and the second thin film transistor region b, and then patterned using a first mask. The gate electrode 210 is formed of one selected from tungsten molybdenum (MoW), molybdenum (Mo), tungsten (W), tungsten silicide (WSi ₂ ), molybdenum silicide (MoSi ₂ ), and aluminum (Al). Lamination is carried out by sputtering or vacuum deposition.

Subsequently, a gate insulating layer 220 is formed over the entire gate electrode 210. The gate insulating layer 220 may be formed of a silicon oxide film, a silicon nitride film, or a double layer thereof, and may be stacked by performing a method such as plasma chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD).

The semiconductor layer 230 is stacked on the gate insulating layer 220. The semiconductor layer 230 may be formed of amorphous silicon or polycrystalline silicon, and preferably of polycrystalline silicon. The semiconductor layer 230 is formed by depositing amorphous silicon using a chemical vapor deposition (CVD) method, crystallizing the polysilicon film using a crystallization method, and then forming a gate insulating film 220 using a second mask. And patterning at the same time. The CVD method may use a chemical vapor deposition method such as PECVD, LPCVD. At this time, when the amorphous silicon is carried out by PECVD, a process of lowering the concentration of hydrogen by dehydrogenation by heat treatment after deposition of a silicon film is performed. In addition, the crystallization method of the amorphous silicon film may be RTA (Rapid Thermal Annealing) process, SPC (Solid Phase Crystallization), ELA (Excimer Laser Crystallization), MIC (Metal Induced Crystallization), MILC (Metal Induced Lateral Crystallization) or Any one or more of the SLS method (Sequential Lateral Solidification) can be used.

Next, n-type impurities are implanted into the semiconductor layer 230 of the first thin film transistor region a using the third mask 240 to form an NMOS. The n-type impurity is formed of one selected from the group consisting of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). In this case, the second thin film transistor region b is formed such that n-type impurities are not implanted by stacking the third masks 240.

Subsequently, the first electrode 250 is disposed on the third mask 240 of the first and second thin film transistor regions a and b and the source / drain regions 230a and 230c of the semiconductor layer into which the n-type impurities are implanted. Laminated. The first electrode 250 is formed of a transparent electrode such as ITO or IZO, and preferably formed of ITO.

The first electrode 250 is typically deposited by sputtering, and in the present invention, the first electrode 250 is formed of ITO, and is deposited on the semiconductor layer and the substrate implanted with n-type impurities. When the thickness of the ITO is defined as t1, the thickness of the ITO deposited in the direction perpendicular to the mask which is the photoresist (PR) is t2, and the thickness of the ITO deposited on the mask is t3, It satisfies the deposition characteristic of t1 = t3 >> t2. The first electrode 250 may be patterned without an additional mask by using a lift-off method using the characteristics of the ITO deposition thickness, thereby reducing the number of masks by one.

The lift-off method is applicable when the thickness of the deposited ITO satisfies the condition of t1 = t3 >> t2, and the photoresist PR on the channel region 230b through the photoresist strip PR STRIP. Photo Resist 240 and the first electrode 250 may be removed.

The reaction order of the lift-off method is that the semiconductor layer 230 is etched by the photoresist etching solution by etching both the portion of t2 where the thickness of ITO is relatively thin compared to the portion t1 and t3 and etching the photoresist under the portion t2. As the photoresist on the channel region 230b is separated, the ITO on the photoresist is removed at the same time to form an ITO pattern as shown in FIG. 2D.

As a PR stripper applied to the lift-off method, a mixture of H ₂ S0 ₄ : H ₂ 0 ₂ , a mixture of NH ₄ OH: H ₂ 0 ₂ : H ₂ 0, and a mixture of NH ₄ F: HF (BOE) or HF can be used, but is not limited thereto.

Subsequently, lightly doped drain (N-LDD) impurities may be further implanted using the fourth mask 260 on the channel region 230b of the semiconductor layer 230 of the first thin film transistor regions a and b. have. The N-LDD impurity implantation may use a conventional n-type impurity, and is generally referred to as PH ₃ , and is preferably implanted to improve characteristics of the thin film transistor. As a result, the N-LDD regions 230d and 230e of the semiconductor layer 230 are defined.

After implanting the N-LDD impurity, source / drain regions 230f and 230g are defined by implanting p-type impurities into the semiconductor layer 230 of the second thin film transistor region b using the fourth or fifth mask. . The p-type impurity is formed of one selected from the group consisting of boron (B), aluminum (Al), gallium (Ga), and indium (In).

Accordingly, the semiconductor layer 230 of the first thin film transistor region a includes n-type impurity source / drain regions 230a and 230c, N-LDD impurity source / drain regions 230d and 230e, and a channel region 230b. The p-type impurity source / drain regions 230f and 230g and the channel region 230b are defined in the semiconductor layer 230 of the second thin film transistor region b.

 Subsequently, the fifth mask 270 stacked on the first and second thin film transistor regions a and b is used to form an upper portion of the semiconductor layer 230 on the fifth mask and the second thin film transistor region b. 1 electrode 250 is deposited. The first electrode 250 is made of the same material as the material of the first electrode 250 and is formed of a transparent electrode such as ITO or IZO.

The formation method and the patterning method of the first electrode 250 of the second thin film transistor region (b) are the same as the formation method and the patterning method of the first electrode 250, and lift-off during patterning. The law proceeds on the same principle.

After the lift-off method, the PR strip is processed, and a metal film contacting the first electrode is stacked on the first electrode 250 of the first and second thin film transistor regions (a and b), and the fifth or fifth film is deposited. The source / drain electrodes 280a and 280b are formed by patterning through etching using six masks. The source / drain electrodes 280a and 280b are formed of one selected from the group consisting of molybdenum (Mo), tungsten (W), tungsten molybdenum (MoW), tungsten silicide (WSix), and the like. It deposits by a vapor deposition method.

In this case, the gate electrode 210, the semiconductor layer 230, and the source / drain electrodes 280a and 280b form a thin film transistor. The organic light emitting device is formed of a CMOS having both a first thin film transistor of an NMOS and a second thin film transistor of a PMOS.

A passivation film 285 is formed on the source / drain electrodes 280a and 280b to protect the thin film transistor from contamination of a subsequent process over the entire surface of the substrate. The passivation film 285 may be formed of a silicon oxide film, a silicon nitride film, or a double layer thereof. The passivation film 285 may be stacked in a manner such as PECVD or LPCVD.

A pixel defining layer (PDL) 290 is formed of a photosensitive organic insulating material to define a pixel region on the passivation layer 285 and to insulate the organic light emitting layer. The photosensitive organic insulating layer is a positive type and has a property of changing into a material that is dissolved in a developer when exposed to light. In addition, the photosensitive organic insulating layer has excellent planarization characteristics, so that the topography of the passivation insulating layer 285 may be alleviated to form a flat surface. The pixel definition layer 290 formed of the photosensitive organic insulating layer may be formed of acrylic resin or polyimide (PI). In addition, it is preferable to form the pixel definition layer 290 on the substrate by using spin coating.

Subsequently, the pixel definition layer 290 is etched through back exposure, and the passivation layer is patterned by wet etching using a selectivity to form the first electrode 250 of the first thin film transistor region a. A via hole 295 is formed to expose.

The back exposure irradiates light from the bottom surface of the substrate 200 on which the pixel definition layer 290 is formed to etch the pixel definition layer 290 on the first electrode 250 of the first thin film transistor region a. It is. The first electrode 250 may transmit light incident from the bottom surface of the substrate 200. Therefore, the pixel defining layer 290 formed on the first electrode 250 of the opening 295 is exposed to the light. The portion of the pixel defining layer 290, which is the photosensitive organic insulating layer, is exposed to the light, that is, the opening 295 is changed and etched into a material that can be dissolved in a developer.

Subsequently, an organic layer (not shown) and a second electrode (not shown) including at least an organic light emitting layer are formed on the first electrode 250 exposed in the opening 295. The organic layer is one or more layers of the electron injection layer (EIL), the electron transport layer (ETL), the organic light emitting layer (EML), the hole transport layer (HTL) and the hole injection layer (HIL) in addition to the organic light emitting layer (EML). It may further include. The organic light emitting layer may be a low molecular material or a high molecular material, the low molecular material is a group consisting of aluminy chinolium complex (Alq3), anthracene (Cyclo pentadiene), Almq, ZnPBO, Balq and DPVBi It is formed into one selected from. The polymer material is selected from the group consisting of polythiophene (PT), poly (p-phenylenevinylene) (PPV; poly (p-phenylenevinylene)), polyphenylene (PPP; polyphenylene) and derivatives thereof It is formed in one kind.

The organic layer is laminated by vacuum deposition, spin coating, inkjet printing, laser induced thermal imaging (LITI), or the like. Preferably, the lamination is performed by spin coating. In addition, the patterning of the organic layer may be implemented using a laser thermal transfer method, a vacuum deposition method using a shadow mask, or the like.

The second electrode is formed by vacuum deposition, and the organic light emitting diode is completed by encapsulating the substrate formed up to the second electrode with the upper substrate by a conventional method.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

As described above, according to the present invention, by applying a lift-off method to an organic light emitting device having a bottom gate type thin film transistor, the number of existing 7 to 8 mask processes is 5 to 5 on a CMOS basis. By reducing to six masks, material and manufacturing costs can be reduced due to process tact time and process mask count reduction.

Claims (9)

Providing a substrate having first and second thin film transistor regions; Patterning a gate electrode on the substrate; Patterning a semiconductor layer on the gate electrode; Injecting an n-type impurity into the semiconductor layer of the first thin film transistor region, depositing a first electrode on the semiconductor layer, and then forming a pattern by a lift-off method; Injecting a p-type impurity into the semiconductor layer of the second thin film transistor region, depositing a first electrode on the second thin film transistor semiconductor layer, and forming a pattern by a lift-off method; Patterning the source / drain electrodes so as to contact the first electrodes of the first and second thin film transistor regions; Forming a pixel definition layer by backside exposure so as to have an opening on the source / drain electrode; Forming an organic layer including at least an organic light emitting layer on the first electrode exposed through the opening; And The method of manufacturing an organic light emitting display device, comprising forming a second electrode on the organic layer. The method of claim 1, The first electrode is a method of manufacturing an organic light emitting display device, characterized in that formed by a transparent electrode such as ITO or IZO. The method of claim 1, The lift-off method is a method of manufacturing an organic light emitting display device, characterized in that formed through a photoresist strip. The method of claim 3, wherein The photoresist strip is selected from the group consisting of a mixture of H ₂ S0 ₄ : H ₂ 0 ₂ , a mixture of NH ₄ OH: H ₂ 0 ₂ : H ₂ 0, a mixture of NH ₄ F: HF (BOE) or HF. The manufacturing method of the organic electroluminescent element which is 1 type. The method of claim 3, wherein The thickness of the first electrode satisfies t1 = t3 >> t2 manufacturing method of the organic light emitting device. Where t1 is the thickness of ITO deposited on the semiconductor layer and the substrate implanted with n-type impurities, t2 is the thickness of ITO deposited in a direction perpendicular to the mask which is the photoresist, and t3 is the thickness of ITO deposited on the mask. Refers to. The method of claim 1, The method of manufacturing an organic light emitting display device, wherein the source / drain electrode and the first electrode overlap each other. The method of claim 1, And the pixel definition layer is formed of a photosensitive insulating layer. The method of claim 7, wherein The pixel definition layer is a method of manufacturing an organic light emitting display device, characterized in that formed of acrylic resin or polyimide. The method of claim 1, The thin film transistor is a method of manufacturing an organic light emitting device, characterized in that to further form an LDD region.

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