KR20060057959A - Discharge circuit for flash memory device - Google Patents

Abstract

The present invention relates to a discharge circuit of a flash memory device, wherein a first and a second NMOS transistor are connected in series between a triple P well and a ground terminal, and the first NMOS transistor is driven at a voltage higher than a power supply voltage. Flash memory devices that can increase productivity and reliability and reduce circuit area by preventing Negative Transistors from failing and destroying by driving NMOS transistors according to a discharge signal at the supply voltage level. The discharge circuit of is presented.

Discharge Circuit, Snapback, Transistor Series Connection

Description

Discharge circuit for flash memory device             

1 is a discharge circuit diagram of a conventional flash memory device.

2 is an operational waveform diagram of FIG. 1.

3 is a discharge circuit diagram of a flash memory device according to the present invention;

4 is an operational waveform diagram of FIG. 3.

<Explanation of symbols for the main parts of the drawings>

N11 and N12: first NMOS transistor

N12 and N22: second NMOS transistor

C11 and C21: Capacitance of Triple Pwell

The present invention relates to a discharge circuit of a flash memory device, and more particularly, to a triple P well discharge circuit capable of preventing a snap back phenomenon that may occur in an erase operation.

NAND flash memory devices, which are electrically erasable and programmable memory devices, are semiconductor devices used in portable electronic devices such as notebooks, PDAs, and cellular phones, and in computer BIOS, printers, and USB drivers. The NAND-type flash memory device performs a program and erase function by changing a threshold voltage of a cell while moving an electron by a strong electric field in a thin tunnel oxide film of about 100 kW.

To erase the NAND type flash memory cell, 0V is applied to the word line of the selected block, and the word line, drain select line (DSL), source select line (SSL), common source line (CSL), and bits of the unselected block are applied. Each line is floated and a high voltage of 20V is applied to the bulk (triple P well). This causes the word lines, drain select lines (DSL), source select lines (SSL) and all bit lines, and the source of all the blocks except the word lines of the selected block to be approximately 20V Is approved. Therefore, since 20V is applied between the actual word line and the bulk only in the selected block, the erase operation is performed only in the selected block. The reason for applying to the bulk (triple P well) without applying the erase voltage to the gate is to apply a negative voltage to the erase when the erase voltage is applied to the gate. This is because the chip becomes larger and more complex as it is needed. However, to apply voltage to the bulk, triple P wells must be separated from each other in order to be able to apply voltage separately for each block. In order to implement this, the size of the chip is seriously increased, and the erase voltage is applied to the entire block at once.

However, since NAND-type flash memory devices have a large cell area, triple P wells have a capacitance of about several microwatts. In this case, a large problem does not occur in an operation of applying a voltage of 20 V to the triple P well, but a problem occurs in an operation of discharging the triple P well to 0 V after the erase operation is terminated. In general, in the NAND type flash memory device, since the breakdown voltage of the gate oxide and the junction of the high voltage transistor is designed to be higher than 20V, there is no problem in general operation. However, the breakdown voltage of the junction has a dependency on the gate voltage. For example, if the gate voltage is 0V, it has a sufficient breakdown voltage of approximately 25V or more, but the breakdown voltage drops below 20V even when the gate voltage is about 2V.

1 is a conventional triple P well discharge circuit diagram, in which reference numeral C11 denotes a capacitance of a triple P well, and the first transistor N11 is a large normal high voltage NMOS driven by a delayed discharge signal S2. A transistor, and the second transistor N12 is a small size NMOS transistor driven by the discharge signal S1. 2 is an operational waveform diagram of FIG. 1. However, in the circuit diagram of FIG. 1, when the second NMOS transistor N12 is not connected, the previous condition is satisfied at the moment when the discharge signal S1 transitions from 0V to the power supply voltage Vcc level for the discharge operation after erasing. Therefore, the first NMOS transistor N11 is instantaneously destroyed. This phenomenon is called a snap back phenomenon. Therefore, transistors that are likely to operate in the snapback state are usually set by the snapback rule and designed according to this rule. Even if the snapback phenomenon occurs with a distance between the gate and the junction contact of about 1 to 2 mu m or more, Use a method to prevent deterioration of the gate or contacts. However, as described above, since the triple P well has a very large capacitance of several orders of magnitude, a transistor having a gate width of about 10000 µm is used for sufficient discharge. However, if the distance between the gate and the junction contact is separated by approximately 1 to 2 mu m or more, an area of about 40000 mu m 2 must be taken. Accordingly, the first NMOS transistor N11 uses a large-sized general transistor and connects a relatively small (about 1/10 size) second NMOS transistor N12 for preventing snapback in parallel. In this way, the second NMOS transistor N12 is turned on first than the first NMOS transistor N11 to discharge the triple P well a little to lower the voltage, and then complete discharge to the first NMOS transistor N11. do. However, even in this case, if the erase operation is not completed and the power supply is interrupted during the operation, the second NMOS transistor N12 cannot be operated first, so that the snapback phenomenon occurs again in the first NMOS transistor N11. This can cause the chip to fail to erase, which seriously affects the reliability of the product. On the other hand, a power-off test during operation is essential for NAND flash.

The present invention provides a flash memory capable of preventing the snapback phenomenon caused when the gate voltage rises while 20V is applied to both ends of a junction of one transistor and 0V is applied to the other by connecting two transistors in series. It is to provide a discharge circuit of the device.

A discharge circuit of a flash memory device according to an embodiment of the present invention is a discharge circuit for discharging an erase voltage of a triple P well of a flash memory device, wherein a discharge circuit of the flash memory device is disposed between the triple P well and the ground terminal. Two NMOS transistors are connected in series, the first NMOS transistor is driven in accordance with a first control signal, and the second NMOS transistor is driven in accordance with a second control signal for a discharge operation.

The first control signal is a signal at a level higher than the power supply voltage.

The first control signal is a signal of 10V level.

The first control signal is applied before the erase operation and stops application after the erase operation is completed.

The second control signal is a signal of a power supply voltage level.

The second control signal is a signal at a level higher than the power supply voltage.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

3 is a discharge circuit diagram of a flash memory device according to an exemplary embodiment.

Reference numeral C21 denotes a capacitance of the triple P well to which a voltage of 20V is applied for erasing. The voltage of 20V for erasing is generated using an internal pumping circuit. Instead of generating a pumping voltage of 20V at a time, it first generates 10V using a pump with approximately a few kW of current supply and then uses this 10V voltage. Generate a 20V voltage again. This is because a 10V voltage is used during program operation. The first transistor N21 and the second NMOS transistor N22 are connected in series between the triple P well and the ground terminal Vss. Here, the first NMOS transistor N21 is a normal high voltage NMOS transistor to which a voltage of 10 V is applied to the gate terminal, the second NMOS transistor N22 is driven according to the discharge signal S21, and the first NMOS transistor N21 is provided. It is a high voltage NMOS transistor of larger size. On the other hand, a voltage of 10 V applied to the gate terminal of the first NMOS transistor N21 is applied before the erase operation and stopped after the erase is completely completed.

As described above, since a voltage of 10 V is applied to the gate terminal of the first NMOS transistor N21, the ability to flow current is approximately 15 compared to the case where the power supply voltage Vcc, that is, about 3 V is applied to the gate terminal. Since a current of about -20 times can be passed, it may have only about 1/10 the size of the second NMOS transistor N22.

A condition in which the snapback phenomenon may occur in the discharge circuit is when the triple P well is discharged and when the power supply is suddenly interrupted during the erase operation. In any case, since the gate voltage is 10V for the first NMOS transistor N21, the breakdown voltage does not decrease. The snapback phenomenon of the NMOS transistor is affected by the gate voltage, which generally has the lowest breakdown voltage when the gate voltage is between approximately 1 to 3V. In the case of the second NMOS transistor N22, only about 10V of the drain voltage is applied, so that the snapback phenomenon does not occur.

In the embodiment of the present invention, the second NMOS transistor N22 is operated by the discharge signal S21 at the power supply voltage Vcc level, but the second NMOS transistor N22 is also operated according to the discharge signal at the 10V level. In this case, the size of the second NMOS transistor N22 may be reduced to 1/10, thereby reducing the size of the chip.

As described above, according to the present invention, the discharge circuit is configured by connecting the first and second NMOS transistors in series between the triple P well and the ground terminal, wherein the first NMOS transistors are driven according to a voltage higher than the power supply voltage. In addition, the second NMOS transistor can be driven according to the discharge signal of the power supply voltage level to prevent the snapback phenomenon, thereby preventing the transistor from failing and breaking, improving productivity and reliability, and reducing the circuit area. have.

Claims (6)

A discharge circuit for discharging an erase voltage of a triple P well of a flash memory device, First and second NMOS transistors are connected in series between the triple P well and the ground terminal, the first NMOS transistor is driven according to a first control signal, and the second control is performed for the discharge operation of the second NMOS transistor. A discharge circuit of a flash memory device for driving in response to a signal. The discharge circuit of claim 1, wherein the first control signal is a signal having a level higher than a power supply voltage. The discharge circuit of claim 1, wherein the first control signal is a 10V level signal. The discharge circuit of claim 1, wherein the first control signal is applied before an erase operation and is stopped after the erase operation is terminated. The discharge circuit of claim 1, wherein the second control signal is a signal of a power supply voltage level. The discharge circuit of claim 1, wherein the second control signal is a signal having a level higher than a power supply voltage.

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