JP6298240B2 - Semiconductor device and erasing method thereof - Google Patents

Description

  The present invention relates to a semiconductor memory device having a P-type memory transistor and an erasing method thereof.

  Nonvolatile semiconductor memory devices represented by flash memory are widely used as data storage elements in various electronic devices. In recent years, with the demand for downsizing and low power consumption of electronic devices, semiconductor memory devices are also required to have high integration and low power consumption.

JP 2000-003597 A JP 2007-080338 A

  However, when the inventors of the present application have verified the erase operation of the P-type memory transistor, it is clear for the first time that a large current may flow when the erase voltage is applied to each terminal of the transistor and then returned to the standby voltage. It became. In order to enable erasing even when a large current is generated, a thick wiring that can withstand the large current and a large power supply circuit that can supply the large current are required, which hinders the integration of the semiconductor memory device. In addition, the large current that flows during erasure may possibly destroy the memory transistor itself.

  An object of the present invention is to provide a semiconductor memory device and an erasing method thereof that can prevent a large current from flowing during an erasing operation.

  According to one aspect of the embodiment, the N-type well formed in the semiconductor substrate, the P-type first impurity region and the second impurity region formed in the well, and the first impurity Method for erasing a semiconductor memory device having a P-type memory transistor including a charge storage layer formed on the well between a region and the second impurity region, and a gate electrode formed on the charge storage layer A step of applying a negative voltage to the gate electrode, applying a positive voltage to the first impurity region and the well, and extracting charges accumulated in the charge storage layer; and There is provided a method for erasing a semiconductor memory device, comprising the step of bringing the region into a floating state and lowering the well to a standby voltage.

  According to another aspect of the embodiment, the N-type well formed in the semiconductor substrate, the P-type first impurity region and the second impurity region formed in the well, and the first A P-type memory transistor having a charge storage layer formed on the well between one impurity region and the second impurity region; and a gate electrode formed on the charge storage layer; and the gate electrode A negative voltage is applied to the first impurity region and the well to extract a charge accumulated in the charge storage layer, and then the first impurity region is brought into a floating state. There is provided a semiconductor memory device having a control circuit for stepping down a well to a standby voltage.

  According to the disclosed semiconductor memory device and its erasing method, it is possible to prevent a large current from flowing when the erasing voltage is lowered to the standby voltage. In addition, the memory transistor can be prevented from being destroyed by a large current, and the reliability of the semiconductor memory device can be improved.

FIG. 1 is a schematic diagram (part 1) illustrating the structure of a semiconductor memory device according to an embodiment. FIG. 2 is a schematic diagram (part 2) illustrating the structure of the semiconductor memory device according to the embodiment. FIG. 3 is a schematic diagram (part 3) illustrating the structure of the semiconductor memory device according to the embodiment. FIG. 4 is a schematic diagram (part 4) illustrating the structure of the semiconductor memory device according to the embodiment. FIG. 5 is a schematic diagram (part 5) illustrating the structure of the semiconductor memory device according to the embodiment. FIG. 2 is a schematic diagram (part 6) illustrating the structure of the semiconductor memory device according to the embodiment. FIG. 7 is a flowchart illustrating a method for erasing a semiconductor memory device according to an embodiment. FIG. 8 is a time chart illustrating a method for erasing a semiconductor memory device according to one embodiment. FIG. 9 is a schematic diagram illustrating applied voltages to the respective terminals in the semiconductor memory device erasing method according to the embodiment. FIG. 10 is a schematic diagram showing the structure of a semiconductor memory device according to a reference example. FIG. 11 is a flowchart showing a method for erasing a semiconductor memory device according to a reference example. FIG. 12 is a time chart showing a method for erasing a semiconductor memory device according to a reference example. FIG. 13 is a schematic diagram showing voltages applied to the respective terminals in the semiconductor memory device erasing method according to the reference example.

[One Embodiment]
A structure of a semiconductor memory device according to an embodiment and an erasing method thereof will be described with reference to FIGS.

  1 to 6 are schematic views showing the structure of the semiconductor memory device according to the present embodiment. FIG. 7 is a flowchart showing the semiconductor memory device erasing method according to the present embodiment. FIG. 8 is a time chart showing the erasing method of the semiconductor memory device according to the present embodiment. FIG. 9 is a schematic diagram showing voltages applied to the respective terminals in the semiconductor memory device erasing method according to the present embodiment.

  First, the structure of the semiconductor memory device according to the present embodiment will be explained with reference to FIGS.

  As shown in FIG. 1, a word line control circuit 12, a bit line control circuit 30, a source line control circuit 46 and a well control circuit 62 are connected to the memory cell array 10. A word line voltage generation circuit 22 is connected to the word line control circuit 12. A bit line voltage control circuit 40 is connected to the bit line control circuit 30. A source line voltage generation circuit 56 is connected to the source line control circuit 46. A well voltage generation circuit 72 is connected to the well control circuit 62. A stress application signal oscillation circuit 82 is connected to the word line voltage generation circuit 22, the bit line voltage generation circuit 40, the source line voltage generation circuit 56, and the well voltage generation circuit. In this specification, the control circuit and the voltage generation circuit may be collectively referred to as “control circuit”.

  The word line control circuit 12, the word line voltage generation circuit 22, the source line voltage generation circuit 56, the well voltage generation circuit 72, and the stress application signal transmission circuit 82 are connected to the word line voltage detection circuit 28 that detects the voltage of the word line. Has been. A word line control circuit 12, a source line control circuit 46, and a well control circuit 62 are connected to a well voltage detection circuit 78 that detects the voltage of the well. An erase execution signal transmission circuit 80 is connected to the word line voltage generation circuit 22 and the bit line control circuit 30.

  As described above, in the semiconductor memory device according to the present embodiment, the output signal from the stress application signal transmission circuit 82 is supplied to the well voltage generation circuit 72 from the viewpoint of stepping down the well voltage according to the fall of the stress application signal after erasing. It can be input. From the viewpoint of returning the source voltage and the gate voltage to the standby voltage after confirming that the N well voltage has dropped to the standby voltage, the output signal from the well voltage detection circuit 72 is sent to the source line control circuit 46 and the word line control circuit 12. It can be input.

As shown in FIG. 2, the memory cell array 10 has a plurality of sectors 10A, 10B. The plurality of sectors 10A, 10B... Are defined by N wells that are electrically isolated from each other. A well signal line W is connected to each N well. Here, the wells signal line W _A N well sector 10A is connected, it is assumed that the N-well of the sector 10B are well signal line W _B are connected. Although FIG. 2 shows two sectors 10A and 10B, the total number of sectors is not limited to this.

  In the sectors 10A and 10B, P-type memory transistors MC are arranged in a matrix. The P-type memory transistor MC is formed in, for example, an N well formed in a P-type silicon substrate. The source region (first impurity region), the drain region (second impurity region), and the control gate electrode are formed of a P-type semiconductor, and the floating gate electrode (charge storage layer) is formed of an N-type semiconductor. In the following description, “gate electrode” represents “control gate electrode”.

The gate electrodes of the P-type memory transistors MC arranged in the row direction are commonly connected by a word line WL. The drain terminals of the P-type memory transistors MC arranged in the column direction are commonly connected by a bit line BL. Here, word lines WL _A1 , WL _A2 , WL _A3 ... And bit lines BL _A1 , BL _A2 , BL _A3 ... Are provided in the sector 10A, and word lines WL _B1 , WL _B2 , WL _B3 . BL _B1 , BL _B2 , BL _B3 ... _Are provided. In the figure, five word lines WL and three bit lines BL are shown in each sector 10A, 10B, but the number of word lines WL and bit lines BL is not limited to these.

The source terminal of the P-type memory transistor MC is bundled for each of the sectors 10A and 10B and connected to the source line SL. Here, the source lines SL that are commonly connected to the P-type memory transistor MC in the sector 10A represents a source line SL _A, which the source lines SL that are commonly connected to the memory cell MC of the sector 10B represents the source line SL _B And

  As shown in FIG. 3, the word line voltage generation circuit 22 includes an erase voltage 1 generation circuit 24, an erase voltage 2 generation circuit 25, and a VDD generation circuit 26. The word line voltage generation circuit 22 generates an erase voltage 1 generation circuit 24, an erase voltage 2 generation circuit 25, and a VDD generation according to signals from the word line voltage detection circuit 28, the stress application signal transmission circuit 80, and the stress signal transmission circuit 82. The voltage generated by the circuit 26 is output to the word line control circuit 12.

  As shown in FIG. 3, the word line control circuit 12 includes a power connection logic circuit 14, a power connection switch 16, a word line address decode circuit 18, and a word line selection circuit 20. The power connection logic circuit 14 determines a voltage to be applied to each word line WL according to signals from the word line voltage generation circuit 22 and the well voltage detection circuit 78, and determines the power connection switch 16, the word line address decode circuit 18, and the word The line selection circuit 20 is controlled. Thus, a desired drive voltage selected from the drive voltages output from the word line voltage generation circuit 22 can be applied to each word line WL.

Since erasing is performed on a sector basis, the word line selection circuit 20 selects a voltage applied to the word line WL for each sector. In the figure, WL _A corresponds to the word lines (WL _A1 , WL _A2 , WL _A3 ...) Arranged in the sector 10A, and WL _B represents the word lines (WL _B1 , WL _B2 , WL arranged in the sector 10B). _B3 )).

  As shown in FIG. 4, the bit line voltage generation circuit 40 includes a standby voltage generation circuit 42. The bit line voltage generation circuit 40 outputs the voltage generated by the standby voltage generation circuit 42 to the bit line control circuit 30 in accordance with the signal from the stress application signal transmission circuit 82.

  As shown in FIG. 4, the bit line control circuit 30 includes a power connection logic circuit 32, a power connection switch 34, a bit line address decode circuit 34, and a bit line selection circuit 38. The power connection logic circuit 32 determines a voltage to be applied to each bit line BL according to signals from the bit line voltage generation circuit 40 and the erase execution signal transmission circuit 80, and includes a power connection switch 34, a bit line address decode circuit 36, and The word line selection circuit 38 is controlled. Accordingly, a desired drive voltage selected from the drive voltages output from the bit line voltage generation circuit 40 can be applied to each bit line BL. Alternatively, the bit lines BL can be disconnected from the bit line voltage generation circuit 40 to be in a floating state.

Since erasing is performed on a sector basis, the bit line selection circuit 38 selects a voltage applied to the bit line BL for each sector. In the figure, BL _A corresponds to the bit lines (BL _A1 , BL _A2 , BL _A3 ...) Arranged in the sector 10A, and BL _B represents the bit lines (BL _B1 , BL _B2 , BL arranged in the sector 10B). _B3 )).

  As shown in FIG. 5, the source line voltage generation circuit 56 includes an erase voltage generation circuit 58 and a VDD generation circuit 60. The source line voltage generation circuit 50 outputs the voltage generated by the erase voltage generation circuit 58 and the VDD generation circuit 60 to the source line control circuit 46 in response to the signal from the stress application signal transmission circuit 82.

As shown in FIG. 5, the source line control circuit 46 includes a power connection logic circuit 48, a power connection switch 50, a sector decoding circuit 52, and a sector selection circuit 54. The power connection logic circuit 48 determines a voltage to be applied to each source line SL in accordance with signals from the source line voltage generation circuit 56 and the well voltage detection circuit 78, and the power connection switch 50, sector decode circuit 52, and sector selection circuit. 54 is controlled. Thus, a desired drive voltage selected from the drive voltages output from the source line voltage generation circuit 56 can be applied to the source lines SL _A , SL _B. Alternatively, the source line SL can be disconnected from the source line voltage generation circuit 56 and the source lines SL can be in a floating state.

  The well voltage generation circuit 72 includes a standby voltage generation circuit 74 and an erase voltage generation circuit 76 as shown in FIG. The well voltage generation circuit 72 outputs the voltages generated by the standby voltage generation circuit 74 and the erase voltage generation circuit 76 to the well control circuit 62 in response to signals from the word line voltage detection circuit 28 and the stress application signal transmission circuit 82. To do.

As shown in FIG. 6, the well control circuit 62 includes a power connection logic circuit 64, a power connection switch 66, a sector decoding circuit 68, and a sector selection circuit 70. The power connection logic circuit 64 determines a voltage to be applied to the N well of each sector in accordance with a signal from the well voltage generation circuit 72, and controls the power connection switch 66, the sector decode circuit 68, and the sector selection circuit 70. Thus, each sector 10 _A, 10 _B of the N-well (well signal lines W _A, W _B) to the desired driving voltage selected from among the driving voltage output from the well voltage generating circuit 72 can be applied to each of It is like that.

  Next, the erasing method of the semiconductor memory device according to the present embodiment will be explained with reference to FIGS. Here, a process of collectively erasing the P-type memory transistors MC in the sector 10A will be described. Note that the value of the drive voltage shown in the following description is an example, and the value is not limited thereto, and can be appropriately increased or decreased according to the dimensions of the semiconductor device, the power supply voltage, and the like. Further, in this specification, “boost” means to increase the absolute value of the applied voltage, and “step-down” means to reduce the absolute value of the applied voltage.

  Erase of the P-type memory transistor MC is performed by extracting electrons stored in the floating gate. This method is called an FN (Fowler-Nordheim Tunneling) erase method.

  In the semiconductor memory device erase method according to the present embodiment, the P-type memory transistor MC is erased in the order of steps S10 to S16 shown in FIG. By using the semiconductor memory device erase method according to the present embodiment, it is possible to prevent a large current from flowing between the source and the N well as occurs in the case of the erase method according to the reference example described later.

(Step S10)
In the standby state, the standby voltage of the power supply voltage VDD (here, +1.2 V) is applied to each terminal (gate, drain, source, N well) of all the P-type memory transistors MC).

(Step S11)
Here, it is assumed that an erase execution instruction is issued at time t1. When an erase execution command is issued, the erase execution signal transmission circuit 80 outputs an erase execution signal that rises from a low level to a high level to the word line voltage generation circuit 22 and the bit line voltage generation circuit 40.

The bit line voltage generation circuit 40 sets the bit line BL _A of the sector 10 _{A to be} erased in a floating state via the bit line control circuit 32 in response to the rising of the erase execution signal. The other voltage of the bit line BL _B of the sector 10 _B is maintained as a standby voltage that is an output voltage from the standby voltage generation circuit 42 (see FIGS. 8 and 4).

The word line voltage generator 22, in response to a rising edge of the erase execution signal, via the word line control circuit 12, to connect the erase voltage 1 generating circuit 24 to the word lines WL _A sector 10 _A erased. As a result, the voltage of the word line WL _A is gradually increased from the standby voltage to the output voltage (V _gate (E ′): −5.3 V) from the erase voltage 1 generation circuit 24. The other voltage of the word line WL _B of the sector 10 _B is maintained as a standby voltage that is an output voltage from the VDD generation circuit 26 (see FIGS. 8 and 3).

The output voltage from the erase voltage 1 generation circuit 24 is a voltage between the output voltage from the erase voltage 2 generation circuit 25 and the standby voltage, which is an applied voltage at the time of erase. In the erasing method of this embodiment, the voltage applied to the gate electrode is first boosted to the output voltage (V _gate (E ′)) from the erasing voltage 1 generating circuit 24, and then the erasing voltage 2 which is the applied voltage at the time of erasing. The voltage is boosted to the output voltage (V _gate (E)) from the generation circuit 25. The reason for boosting in two stages is to prevent malfunction due to coupling.

Word line voltage detection circuit 28 detects the voltage of the word lines WL _A, a predetermined value the voltage of the word line WL _A is _{(V gate (E '):} - 5.3V) before checking whether it has been charged. When it is confirmed that the voltage of the word line WL _A is charged to a predetermined value, the word line voltage detection circuit 28 outputs a V _gate (E ′) detection signal that falls from a high level to a low level for a predetermined time. The data is output to the word line voltage generation circuit 22, the source line voltage generation circuit 56, and the well voltage generation circuit 72. Here, the rising time of the V _gate (E ′) detection signal is defined as time t2.

(Step S12)
Source line voltage generator _56, in response to a rising edge of the _{V gate} (E ') detection signal, via the source line control circuit 46, connected to a source line SL _A sector 10 _A erased erase voltage generation circuit 58 To do. Thus, the output voltage from the erase voltage generating circuit 58 a voltage of the source line SL _A from the standby voltage _{(V source (E): +} 9.3V) gradually boosted to. Voltage of the source line SL _B connected to the other sectors 10B is maintained at the standby voltage which is the output voltage from the VDD generation circuit 60 (see FIG. 8 and FIG. 5).

Moreover, well voltage generating circuit _72, in response to a rising edge of the _{V gate} (E ') detection signal, through the well control circuit 62, N-well (well signal lines of the sector 10 _A erased erase voltage generation circuit 76 W _A ). As a result, the voltage of the N well is gradually raised from the standby voltage to the output voltage (V _well (E): +9.3 V) from the erase voltage generation circuit 76. The voltage of the N well (well signal line W _B ) of the other sector 10B is maintained as the standby voltage that is the output voltage from the standby voltage generation circuit 74 (see FIGS. 8 and 6).

The word line voltage generator _22, in response to a rising edge of the _{V gate} (E ') detection signal, through the word line control circuit 12, a word line WL of the sectors 10 _A erased erase voltage 2 generating circuit 25 Connect to _A. As a result, the voltage of the word line WL _A is gradually increased from V _gate (E ′) to the output voltage (V _gate (E): −9.3 V) from the erase voltage 2 generation circuit 25. The other voltage of the word line WL _B of the sector 10 _B is maintained as a standby voltage that is an output voltage from the VDD generation circuit 26 (see FIGS. 8 and 3).

Word line voltage detection circuit 28 detects the voltage of the word lines WL _A, a predetermined value the voltage of the word line WL _A is _{(V gate (E): -} 9.3V) before checking whether it has been charged. When it is confirmed that the voltage of the word line WL _A has been charged to a predetermined value, the word line voltage detection circuit 28 applies a V _gate (E) detection signal that falls from a high level to a low level for a predetermined time as a stress. It outputs to the applied signal transmission circuit 82.

(Step S13)
The stress application signal transmission circuit 82 generates a stress application signal that rises from a low level to a high level in response to the rise of the V _gate (E) detection signal, and outputs the stress application signal to the word line voltage generation circuit 22, the bit line voltage generation circuit 40, and the source line voltage. This is output to the generation circuit 56 and the well voltage generation circuit 72.

While the stress applied signal is maintained at a high level, a predetermined voltage for performing an erase is applied to each terminal of the P-type memory transistor MC in sector 10 _A erased. That is, V _gate (E) (−9.3 V) is applied to the _gate terminal, V _source (E) (+9.3 V) is applied to the source terminal, and V _well (E) (+9) is applied to the N well. .3V) is applied. The drain terminal is floating. Thereby, erasure of the P-type memory transistor MC in sector 10 _A is performed (step S13). Here, the time of execution of erasure is set as time t3.

  After a predetermined erasing time has elapsed, the stress application signal transmission circuit 82 receives a stress application end command and falls the stress application signal from the high level to the low level (time t4).

(Step S14)
Word line voltage generator 22, in response to the falling edge of the stress applied signal, via the word line control circuit 12 connects the word line WL _A sector 10 _A erased to the erase voltage 1 generating circuit 24, V discharge to _gate (E ') (-5.3V). The other voltage of the word line WL _B of the sector 10 _B is maintained as a standby voltage that is an output voltage from the VDD generation circuit 26 (see FIGS. 8 and 3).

The bit line voltage generation circuit 40 connects the standby voltage generation circuit 42 to the bit line BL _A of the sector 10 _A to be erased via the bit line control circuit 32 in response to the falling of the stress application signal. Thus, applying a standby voltage output is a voltage from the standby voltage generating circuit 42 to the bit line BL _A sector 10 _A. The other voltage of the bit line BL _B of the sector 10 _B is maintained as a standby voltage that is an output voltage from the standby voltage generation circuit 42 (see FIGS. 8 and 4).

The source line voltage generator 56, in response to the falling edge of the stress applied signal, via the source line control circuit 46, a floating state source lines SL _A sector 10 _A erased. The other voltage of the source line SL _B of the sector 10 _B is maintained as a standby voltage that is an output voltage from the VDD generation circuit 60 (see FIGS. 8 and 5).

In addition, the well voltage generation circuit 72 changes the standby voltage generation circuit 74 to the N well (well signal line W _A ) of the sector 10 _A to be erased via the well voltage control circuit 62 in response to the fall of the stress application signal. Connect to. Thus, gradually lowers the voltage of the N-well of the sector 10 _A from _{V well (E) (+ 9.3V} ) to the standby voltage which is the output voltage of the standby voltage generating circuit 74. Other sectors 10 voltage of the connected-well signal line W _B to N-well of _B is kept at the standby voltage which is the output voltage from the standby voltage generating circuit 76 (see FIGS. 8 and 6).

  As described above, in the erasing method of the present embodiment, the N well voltage is stepped down to the standby voltage while the source terminal is in a floating state. When the N-well voltage is stepped down with the source terminal in a floating state, the source-N well junction may be forward-biased, but no large current flows because the source terminal is in a floating state. This will be described later.

Well voltage detecting circuit 78 detects the voltage of the well signal line W _A, N-well to check whether it has been discharged to the standby voltage (VDD). When it is confirmed that the N well has been discharged to the standby voltage, the well voltage detection circuit 78 generates a VDD detection signal that rises from a low level to a high level for a predetermined time, and generates a word line voltage generation circuit 22 and a source line voltage. Output to the circuit 56.

(Step S15)
The word line voltage generation circuit 22 connects the word line WL _A of the sector 10 _{A to be} erased to the VDD generation circuit 26 via the word line control circuit 12 in response to the fall of the VDD detection signal, and reaches the standby voltage. Discharge. The other voltage of the word line WL _B of the sector 10 _B is maintained as a standby voltage that is an output voltage from the VDD generation circuit 26 (see FIGS. 8 and 3).

The source line voltage generator 56, in response to the falling edge of the VDD detection signal, via the source line control circuit 46, connecting the source lines SL _A sector 10 _A erased to VDD generation circuit 60. Thus, the source line SL _A of 10 _A, to apply a voltage VDD which is the output voltage from the VDD generation circuit 60. The other voltage of the source line SL _B of the sector 10 _B is maintained as a standby voltage that is an output voltage from the VDD generation circuit 60 (see FIGS. 8 and 5).

(Step S16)
Thus, the voltage applied to the terminals of the P-type memory transistor MC in sector 10 _A erased, the process returns to the standby state.

Then, it lowered the erase execution signal to the low level to complete the erase of the sector 10 _A (see FIG. 8).

Thereafter, if necessary, by the same procedure, to erase the like other sectors 10 _B.

As described above, in the erasing method of the semiconductor memory device according to the present embodiment, the erasing is executed with the terminal voltage shown in FIG. 9A, and then in the order of (1) to (3) shown in FIG. Step down each terminal voltage to standby voltage. That is, the procedure in (1), a gate voltage _{V gate (E) (- 9.3V} ) V gate (E ') from the (- 5.3V) to step down, the standby voltage to the drain voltage of the floating state (+1. 2V), and the source voltage is changed from V _source (E) (+ 9.3V) to a floating state. Then, in step (2), steps down the well voltage to _V well (E) (+ 9.3 V) from the standby voltage (+ 1.2V) (step S14). Thereafter, in the procedure (3), the source voltage in the floating state is returned to the standby voltage (+1.2 V) (step S15).

  The reason why the terminal voltage is stepped down by such a procedure in the semiconductor memory device erasing method according to the present embodiment will be described below.

First, in step (1), when the source terminal is switched from the state in which V _source (E) is applied to the floating state, the source terminal is in a state in which some charge is accumulated. Here, a case is considered in which the voltage of the source terminal is kept at V _source (E) due to the accumulated charge.

Next, when the N well voltage is stepped down in step (2), the source voltage becomes higher than the N well voltage, that is, the source-N well junction is forward-biased, and the source-N well junction has a forward current (in the figure). , Represented by an arrow). Even when the source voltage is held at a voltage lower than V _source (E), the forward current flows because the N-well voltage becomes lower than the source voltage.

  The source voltage decreases due to the movement of charges accompanying this forward current, and the forward current flows until the source voltage and the N-well voltage become equal. At this time, by keeping the source terminal in a floating state, a forward current more than the flow of electric charge held when switching to the floating state is not generated (see a reference example described later).

  Therefore, by gradually lowering the N well voltage, a forward current can be passed through the source-N well junction to gradually draw out the charge accumulated in the source terminal, and the source voltage can be gradually lowered.

  Thereafter, in step (3), the source voltage in the floating state is returned to the standby voltage, and the gate voltage is returned to the standby voltage, so that a series of erasing processes can be executed while preventing the generation of a large current.

  Therefore, in the semiconductor memory device using the erasing method of this embodiment, the current supply capability of the power supply circuit can be lowered, that is, the power supply circuit can be made smaller. Also, the wiring can be of a normal thickness. Thereby, the degree of integration of the semiconductor memory device can be improved. Further, it is possible to prevent the P-type memory transistor from being destroyed due to a large current flowing in the reverse direction, and to improve the reliability of the semiconductor memory device (see a reference example described later).

  Thus, according to the present embodiment, it is possible to prevent a large current from flowing when the erase voltage is lowered to the standby voltage after erasing the P-type memory transistor. Accordingly, a thick wiring that can withstand a large current and a large power supply circuit for supplying a large current are not required, and the degree of integration of the semiconductor memory device can be improved. In addition, the memory transistor can be prevented from being destroyed by a large current, and the reliability of the semiconductor memory device can be improved.

[Reference example]
A semiconductor memory device and its erase method according to a reference example will be described with reference to FIGS. The same components as those of the semiconductor memory device and the erasing method thereof according to the embodiment shown in FIGS. 1 to 9 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 10 is a schematic diagram showing the structure of the semiconductor memory device according to this reference example. FIG. 11 is a flowchart showing the semiconductor memory device erasing method according to the present embodiment. FIG. 12 is a time chart showing the erasing method of the semiconductor memory device according to the present embodiment. FIG. 13 is a schematic diagram showing applied voltages to the respective terminals in the semiconductor memory device erasing method according to the present embodiment.

  First, the structure of the semiconductor memory device according to this reference example will be described with reference to FIG.

  As shown in FIG. 10, a word line control circuit 12, a bit line control circuit 30, a source line control circuit 46 and a well control circuit 62 are connected to the memory cell array 10. A word line voltage generation circuit 22 is connected to the word line control circuit 12. A bit line voltage control circuit 40 is connected to the bit line control circuit 30. A source line voltage generation circuit 56 is connected to the source line control circuit 46. A well voltage generation circuit 72 is connected to the well control circuit 62. A stress application signal oscillation circuit 82 is connected to the word line voltage generation circuit 22, the bit line voltage generation circuit 40, and the source line voltage generation circuit 56.

  The word line control circuit 12, the word line voltage generation circuit 22, the source line voltage generation circuit 56, the well voltage generation circuit 72, and the stress application signal transmission circuit 82 are connected to the word line voltage detection circuit 28 that detects the voltage of the word line. Has been. An erase execution signal transmission circuit 80 is connected to the word line voltage generation circuit 22 and the bit line control circuit 30.

  Memory cell array 10, word line control circuit 12, word line voltage generation circuit, bit line control circuit 30, bit line voltage generation circuit, source line control circuit 46, source line voltage generation circuit 56, well control circuit 62 and well voltage generation circuit The internal configuration of 72 is basically the same as that of the semiconductor memory device according to the embodiment shown in FIGS.

  As described above, in the semiconductor memory device according to the present reference example, the output signal of the source line control circuit 46 is supplied to the well voltage generation circuit from the viewpoint of reducing the N well voltage to the standby voltage after the source voltage is reduced to the standby voltage after erasing. 72 can be input.

  At this point, an output signal from the stress application signal transmission circuit 82 is input to the well voltage generation circuit 72, and an output signal from the well voltage detection circuit 72 is input to the source line control circuit 46 and the word line control circuit 12. This is different from the semiconductor memory device according to the embodiment.

  Next, a method for erasing a semiconductor memory device according to this reference example will be described with reference to FIGS.

  In the semiconductor memory device erasing method according to this reference example, the P-type memory transistor MC is erased in the order of steps S20 to S27 shown in FIG.

(Step S20)
In the standby state, the standby voltage of the power supply voltage VDD is applied to each terminal (gate, drain, source, N well) of all the P-type memory transistors MC.

(Step S21)
Here, it is assumed that an erase execution instruction is issued at time t1. When an erase execution command is issued, the erase execution signal transmission circuit 80 outputs an erase execution signal that rises from a low level to a high level to the word line voltage generation circuit 22 and the bit line voltage generation circuit 40.

The bit line voltage generation circuit 40 sets the bit line BL _A of the sector 10 _{A to be} erased in a floating state via the bit line control circuit 32 in response to the rise of the erase execution signal (see FIG. 12).

The word line voltage generator 22, in response to a rising edge of the erase execution signal, via the word line control circuit 12, to connect the erase voltage 1 generating circuit 24 to the word lines WL _A sector 10 _A erased. Thus, the output voltage of the voltage of the word line WL _A from erase voltage 1 generating circuit 24 from the standby voltage _{(V gate (E '):} - 5.3V) to gradually boost (see FIG. 12).

Word line voltage detection circuit 28 detects the voltage of the word lines WL _A, a predetermined value the voltage of the word line WL _A is _{(V gate (E '):} - 5.3V) before checking whether it has been charged. When it is confirmed that the voltage of the word line WL _A is charged to a predetermined value, the word line voltage detection circuit 28 outputs a V _gate (E ′) detection signal that falls from a high level to a low level for a predetermined time. The data is output to the word line voltage generation circuit 22, the source line voltage generation circuit 56, and the well voltage generation circuit 72 (step S21). Here, the rising time of the V _gate (E ′) detection signal is defined as time t2.

(Step S22)
Source line voltage generator _56, in response to a rising edge of the _{V gate} (E ') detection signal, via the source line control circuit 46, connected to a source line SL _A sector 10 _A erased erase voltage generation circuit 58 To do. Thus, the output voltage from the erase voltage generating circuit 58 a voltage of the source line SL _A from the standby voltage _{(V source (E): +} 9.3V) to gradually boost (see FIG. 12).

Moreover, well voltage generating circuit _72, in response to a rising edge of the _{V gate} (E ') detection signal, through the well control circuit 62, N-well (well signal lines of the sector 10 _A erased erase voltage generation circuit 76 W _A ). As a result, the voltage of the N-well is gradually increased from the standby voltage to the output voltage (V _well (E): +9.3 V) from the erase voltage generation circuit 76 (see FIG. 12).

The word line voltage generator _22, in response to a rising edge of the _{V gate} (E ') detection signal, through the word line control circuit 12, a word line WL of the sectors 10 _A erased erase voltage 2 generating circuit 25 Connect to _A. Thereby, the voltage of the word line WL _A is gradually increased from V _gate (E ′) to the output voltage (V _gate (E): −9.3 V) from the erase voltage 2 generation circuit 25 (see FIG. 12).

Word line voltage detection circuit 28 detects the voltage of the word lines WL _A, a predetermined value the voltage of the word line WL _A is _{(V gate (E): -} 9.3V) before checking whether it has been charged. When it is confirmed that the voltage of the word line WL _A has been charged to a predetermined value, the word line voltage detection circuit 28 applies a V _gate (E) detection signal that falls from a high level to a low level for a predetermined time as a stress. It outputs to the applied signal transmission circuit 82.

(Step S23)
The stress application signal transmission circuit 82 generates a stress application signal that rises from a low level to a high level in response to the rise of the V _gate (E) detection signal, and generates the word line voltage generation circuit 22, the bit line voltage generation circuit 40, and the source line voltage. Output to the generation circuit 56.

While the stress applied signal is maintained at a high level, a predetermined voltage for performing an erase is applied to each terminal of the P-type memory transistor MC in sector 10 _A erased. Thereby, erasure of the P-type memory transistor MC in sector 10 _A is performed. Here, the time of execution of erasure is set as time t3.

  After a predetermined erasing time has elapsed, the stress application signal transmission circuit 82 receives a stress application end command and falls the stress application signal from the high level to the low level (time t4).

(Step S24)
Word line voltage generator 22, in response to the falling edge of the stress applied signal, via the word line control circuit 12 connects the word line WL _A sector 10 _A erased to the erase voltage 1 generating circuit 24, V discharge to _gate (E ′) (−5.3 V) (see FIG. 12).

The bit line voltage generation circuit 40 connects the standby voltage generation circuit 42 to the bit line BL _A of the sector 10 _A to be erased via the bit line control circuit 32 in response to the falling of the stress application signal. Thus, applying a standby voltage output is a voltage from the standby voltage generating circuit 42 to the bit line BL _A sector 10 _A (see FIG. 12).

The source line voltage generator 56, in response to the falling edge of the stress applied signal, via the source line control circuit 46, connects the VDD generation circuit 60 to the source line SL _A sector 10 _A erased. Accordingly, the voltage of the source line SL _A sector _{10 A V source (E))} (+ 9.3V) gradually stepped down to the standby voltage which is the output voltage from the VDD generation circuit 60 (see FIG. 12, step S24 ). Here, the voltage of the source line SL _A is to the time t5 when the step-down to the standby voltage.
(Step S25)
Then, after the voltage of the source line SL _A sector 10 _A erased is stepped down to the standby voltage, well voltage generating circuit 72, via a well voltage control circuit 62, the erased standby voltage generation circuit 74 sectors It is connected to the 10 _A N well (well signal line W _A ). Thus, gradually lowers the voltage of the N-well of the sector 10 _A from _V well (E) (+ 9.3 V) to the standby voltage which is the output voltage of the standby voltage generator circuit 74 (see FIG. 12).

Incidentally, according to the reference example, after stepping down the voltage of the source line SL _A to the standby voltage earlier, and step down the voltage of the N-well to the standby voltage. This is to prevent a forward bias from being applied to the source-N well junction.

(Step S26)
Next, after the voltage of the N well of the sector 10 _{A to be} erased is lowered to the standby voltage, the word line voltage generation circuit 22 passes the word line WL _A of the sector 10 _{A to be} erased via the word line control circuit 12. Is connected to the VDD generation circuit 26 and discharged to the standby voltage (VDD) (see FIG. 12).

(Step S27)
Thus, the voltage applied to the terminals of the P-type memory transistor MC in sector 10 _A erased, the process returns to the standby state.

Then, it lowered the erase execution signal to the low level to complete the erase of the sector 10 _A (see FIG. 12).

  As described above, in the erasing method of the semiconductor memory device according to the present reference example, after erasing is performed with the terminal voltage shown in FIG. 13A, the order of (1) to (3) shown in FIG. Step down each terminal voltage to standby voltage. When (2) the source voltage is stepped down and then (3) the N well voltage is stepped down according to the order of FIG. 13B, the source-N well junction is always reverse-biased. No current should flow.

  However, it was confirmed that when the source voltage and the N-well voltage were actually stepped down according to the above procedure, the reverse current (represented by the arrows in the figure) gradually increased, resulting in a large current of the order of 10 mA flowing. It was confirmed that no current was flowing between the N well and the P-type substrate. Further, it was confirmed that the source potential was lowered only to around + 5V.

  In order to enable erasing even if this large current occurs, a thick wiring that can withstand the large current and a large power supply circuit capable of supplying the large current are required. Even if wiring and a power supply circuit that can withstand a large current are provided, the P-type memory transistor itself may be destroyed in some cases.

  The inventors of the present application have conducted intensive studies on the cause of the large current flow and considered that the mechanism is as follows.

  In the source-N well junction, a depletion layer spreads by stepping down the source voltage and causing a reverse bias, so that no current normally flows. However, depending on the voltage condition, a breakdown state called a Zener or an avalanche occurs from a certain point, and current may flow out. Whereas a Zener has a constant current, an avalanche is called an electron avalanche, and a current flows so that the amount of current increases in a quadratic curve.

  In the P-type memory transistor structure, the voltage condition of the sequence after erasing is finished and the actual measurement value indicate that the potential difference between the source and the N well is a condition for generating a band-to-band tunneling (BTBT) current (avalanche). It is very similar.

  From these facts, it is presumed that the electrons first generated by BTBT generate a slight current, then induce an electron avalanche, resulting in a large reverse current.

[Modified Embodiment]
The semiconductor memory device and the erasing method thereof described in the above embodiment are merely examples, and can be appropriately modified or changed according to technical common sense of those skilled in the art.

  For example, in the above embodiment, when the source voltage and well voltage are returned to the standby voltage after erasing the P-type memory transistor, the standby voltage is applied to the drain terminal. May be maintained. In this case, when the source terminal is returned from the floating state to the standby voltage, the drain terminal may be returned from the floating state to the standby voltage.

  In the above embodiment, the gate voltage is stepped down / boosted in two stages, but it is not always necessary to step down / boost in two stages. For example, the voltage may be gradually increased from the standby voltage to the erase voltage and gradually decreased from the erase voltage to the standby voltage.

  Further, the procedure until the erase voltage is applied to the P-type memory transistor is not necessarily the same as the procedure described in the above embodiment. It is desirable to appropriately select a procedure that can prevent malfunction due to coupling or the like.

  In the above embodiment, the standby voltage is VDD, but it is not necessarily required to be VDD. Further, the standby voltage applied to each terminal is not necessarily the same.

  Regarding the above embodiment, the following additional notes are disclosed.

(Supplementary Note 1) An N-type well formed in a semiconductor substrate, P-type first impurity region and second impurity region formed in the well, the first impurity region, and the second impurity region A method for erasing a semiconductor memory device having a P-type memory transistor including a charge storage layer formed on the well between the impurity region and a gate electrode formed on the charge storage layer,
Applying a negative voltage to the gate electrode, applying a positive voltage to the first impurity region and the well, and extracting charges accumulated in the charge storage layer;
A method of erasing a semiconductor memory device, comprising: after the step of extracting the charge stored in the charge storage layer, lowering the well by setting the first impurity region in a floating state.

(Supplementary Note 2) In the semiconductor memory device erasing method according to Supplementary Note 1,
A method of erasing a semiconductor memory device, wherein the step of stepping down the well lowers the well to a first standby voltage.

(Supplementary Note 3) In the method for erasing a semiconductor memory device according to Supplementary Note 1 or 2,
A method of erasing a semiconductor memory device, further comprising: applying a second standby voltage to the first impurity region after the step of lowering the well.

(Appendix 4) In the method for erasing a semiconductor memory device according to any one of appendices 1 to 3,
A method for erasing a semiconductor memory device, further comprising the step of stepping down the gate electrode to a third standby voltage after the step of stepping down the well.

(Supplementary Note 5) In the method for erasing a semiconductor memory device according to Supplementary Note 4,
In the step of lowering the well, a voltage higher than the negative voltage and lower than the third standby voltage is applied to the gate electrode.

(Appendix 6) In the method for erasing a semiconductor memory device according to any one of appendices 1 to 5,
In the step of lowering the well, a fourth standby voltage is applied to the second impurity region. A method for erasing a semiconductor memory device, comprising:

(Appendix 7) In the method for erasing a semiconductor memory device according to any one of appendices 1 to 5,
In the step of lowering the well, the second impurity region is brought into a floating state,
A method of erasing a semiconductor memory device, further comprising the step of applying a fourth standby voltage to the second impurity region after the step of lowering the well.

(Appendix 8) In the method for erasing a semiconductor memory device according to any one of appendices 1 to 7,
The method for erasing a semiconductor memory device, wherein, in the step of extracting the charge, the second impurity region is brought into a floating state.

(Supplementary Note 9) An N-type well formed in a semiconductor substrate, P-type first and second impurity regions formed in the well, the first impurity region, and the second impurity region A P-type memory transistor having a charge storage layer formed on the well between the impurity region and a gate electrode formed on the charge storage layer;
A negative voltage is applied to the gate electrode, a positive voltage is applied to the first impurity region and the well, and the charge accumulated in the charge storage layer is extracted, and then the first impurity region is in a floating state And a control circuit for stepping down the well.

(Supplementary note 10) In the semiconductor memory device according to supplementary note 9,
The control circuit steps down the well to a first standby voltage when stepping down the well.

(Appendix 11) In the semiconductor memory device according to Appendix 9 or 10,
A well voltage detection circuit for detecting the voltage of the well;
The semiconductor memory device, wherein the control circuit applies a second standby voltage to the first impurity region after stepping down the well.

(Supplementary note 12) In the semiconductor memory device according to supplementary note 11,
The control circuit steps down the well and then steps down the gate electrode to a third standby voltage.

(Supplementary note 13) In the semiconductor memory device according to supplementary note 12,
The control circuit applies a voltage higher than the negative voltage and lower than the third standby voltage to the gate electrode when stepping down the well.

(Supplementary note 14) In the semiconductor memory device according to any one of supplementary notes 9 to 13,
The control circuit applies a fourth standby voltage to the second impurity region when the well is stepped down. The semiconductor memory device, wherein:

(Supplementary note 15) In the semiconductor memory device according to any one of supplementary notes 9 to 13,
The control circuit places the second impurity region in a floating state when lowering the well, and applies a fourth standby voltage to the second impurity region after lowering the well. A semiconductor memory device.

(Supplementary Note 16) In the semiconductor memory device according to any one of supplementary notes 9 to 15,
The control circuit causes the second impurity region to be in a floating state when the charge is extracted.

DESCRIPTION OF SYMBOLS 10 ... Memory cell array 12 ... Word line control circuit 14, 32, 48, 64 ... Power supply connection logic circuit 16, 34, 50, 66 ... Power supply connection switch 18 ... Word line address decoding circuit 20 ... Word line selection circuit 22 ... Word line Voltage generation circuit 24 ... Erase voltage 1 generation circuit 25 ... Erase voltage 2 generation circuit 26, 60 ... VDD generation circuit 28 ... Word line voltage detection circuit 30 ... Bit line control circuit 36 ... Bit line address decode circuit 38 ... Bit line selection circuit 40 bit line voltage generation circuits 42 and 74 standby voltage generation circuit 46 source line control circuits 52 and 68 sector decode circuits 54 and 70 sector selection circuit 56 source line voltage generation circuits 58 and 76 erase voltage generation circuit 62 ... Well control circuit 72 ... Well voltage generation circuit 7 ... well voltage detecting circuit 80 ... erase execution signal transmitting circuit 82 ... stress application signaling circuit

Claims (9)

An N-type well formed in the semiconductor substrate; a P-type first impurity region and a second impurity region formed in the well; the first impurity region and the second impurity region; A method for erasing a semiconductor memory device having a P-type memory transistor including a charge storage layer formed on the well between and a gate electrode formed on the charge storage layer,
Applying a negative voltage to the gate electrode, applying a positive voltage to the first impurity region and the well, and extracting charges accumulated in the charge storage layer;
After the step of extracting the charge accumulated in the charge accumulation layer, the step of lowering the well by bringing the first impurity region into a floating state,
In the step of lowering the well, a fourth standby voltage is applied to the second impurity region. A method for erasing a semiconductor memory device, comprising: The method for erasing a semiconductor memory device according to claim 1.
A method of erasing a semiconductor memory device, wherein the step of stepping down the well lowers the well to a first standby voltage. The method for erasing a semiconductor memory device according to claim 1 or 2,
A method of erasing a semiconductor memory device, further comprising: applying a second standby voltage to the first impurity region after the step of lowering the well. Erasing method of the semiconductor memory device according to any one of claims 1 to 3,
Prior to the step of stepping down the well, further comprising the step of bringing the second impurity region into a floating state ,
A method of erasing a semiconductor memory device. An N-type well formed in the semiconductor substrate; a P-type first impurity region and a second impurity region formed in the well; the first impurity region and the second impurity region; A P-type memory transistor having a charge storage layer formed on the well between and a gate electrode formed on the charge storage layer;
A negative voltage is applied to the gate electrode, a positive voltage is applied to the first impurity region and the well, and the charge accumulated in the charge storage layer is extracted, and then the first impurity region is in a floating state And a control circuit for stepping down the well,
The control circuit applies a fourth standby voltage to the second impurity region when the well is stepped down. The semiconductor memory device, wherein: The semiconductor memory device according to claim 5.
The control circuit steps down the well to a first standby voltage when stepping down the well. The semiconductor memory device according to claim 5 or 6,
A well voltage detection circuit for detecting the voltage of the well;
The semiconductor memory device, wherein the control circuit applies a second standby voltage to the first impurity region after stepping down the well. The semiconductor memory device according to claim 7.
The control circuit steps down the well and then steps down the gate electrode to a third standby voltage. The semiconductor memory device according to claim 5,
Wherein the control circuit, the pre-Symbol second impurity region in a floating state, when stepping down the well, and applying a fourth standby voltage to the second impurity region and the floating state Semiconductor memory device.

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