KR20060056164A - Energy recovery apparatus and method of plasma display panel - Google Patents

Abstract

The present invention relates to an energy recovery apparatus and method for a plasma display panel to improve energy recovery efficiency and discharge characteristics.

An energy recovery apparatus of a plasma display panel according to the present invention includes a plasma display panel having a scan electrode and a sustain electrode for sustain discharge; First to third voltage sources for supplying a sustain voltage to the panel; A first inductor connected between the second voltage source and the scan electrode to recover energy stored in the panel; A second inductor connected between the third voltage source and the sustain electrode to recover energy stored in the panel and to resupply the recovered energy to the panel; A first switch connected between the first voltage source and the scan electrode and turned on when a sustain voltage is supplied to the scan electrode; A second switch connected between the first voltage source and the sustain electrode and turned on when a sustain voltage is supplied to the sustain electrode; A third switch connected between the sustain electrode and a ground voltage source and synchronized with the first switch when a sustain voltage is supplied to the scan electrode; And a fourth switch connected between the scan electrode and the ground voltage source and synchronized with the second switch when a sustain voltage is supplied to the sustain electrode.

Description

Energy recovery apparatus and method of plasma display panel {ENERGY RECOVERY APPARATUS AND METHOD OF PLASMA DISPLAY PANEL}             

1 is a perspective view showing a conventional three-electrode AC surface discharge type plasma display panel.

2 is a circuit diagram illustrating an energy recovery apparatus of a conventional plasma display panel.

3 is a timing diagram and waveform diagrams illustrating on / off timings of the switches illustrated in FIG. 2 and output waveforms of the panel capacitor.

4 is a circuit diagram illustrating an energy recovery apparatus of a plasma display panel according to an exemplary embodiment of the present invention.

FIG. 5 is a waveform diagram illustrating an output waveform of the panel capacitor illustrated in FIG. 4.

6 is a waveform diagram illustrating another output waveform of the panel capacitor illustrated in FIG. 4.

FIG. 7 is a timing diagram and waveform diagrams illustrating on / off timing of the switches illustrated in FIG. 4 and an output waveform of the panel capacitor.

FIG. 8 is a circuit diagram showing on / off states and current paths of switches before the t0 period shown in FIG. 4.

FIG. 9 is a circuit diagram illustrating on / off states and current paths of switches in the t0 period shown in FIG. 4.

FIG. 10 is a circuit diagram illustrating on / off states and current paths of switches in the t1 period shown in FIG. 4.

FIG. 11 is a circuit diagram illustrating on / off states and current paths of switches in the t2 period shown in FIG. 4.

FIG. 12 is a circuit diagram illustrating on / off states and current paths of the switches in the period t3 shown in FIG. 4.

FIG. 13 is a circuit diagram illustrating on / off states and current paths of switches in the t4 period shown in FIG. 4.

FIG. 14 is a circuit diagram illustrating on / off states and current paths of switches in the t5 period shown in FIG. 4.

FIG. 15 is a circuit diagram illustrating on / off states and current paths of switches in the t6 period shown in FIG. 4.

FIG. 16 is a circuit diagram illustrating on / off states and current paths of switches in the t7 period shown in FIG. 4.

FIG. 17 is a circuit diagram illustrating on / off states and current paths of switches in the t8 period shown in FIG. 4.

FIG. 18 is a circuit diagram illustrating on / off states and current paths of the switches in the t9 period shown in FIG. 4.

FIG. 19 is a circuit diagram illustrating on / off states and current paths of switches in a period t10 shown in FIG. 4.

FIG. 20 is a circuit diagram illustrating on / off states and current paths of switches in the t11 period shown in FIG. 4.

FIG. 21 is a circuit diagram illustrating on / off states and current paths of switches in the t12 period shown in FIG. 4.

FIG. 22 is a circuit diagram showing on / off states and current paths of the switches in the period t13 shown in FIG.

FIG. 23 is a circuit diagram showing on / off states and current paths of the switches in the period t14 shown in FIG.

<Description of the symbols for the main parts of the drawings>

10: upper substrate 12Y, 12Z: transparent electrode

13Y, 13Z: bus electrode 14, 22: dielectric layer

16: protective film 18: lower substrate

24: partition 26: phosphor layer

30, 32: energy recovery device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an energy recovery apparatus for a plasma display panel, and more particularly, to an energy recovery apparatus and method for a plasma display panel capable of improving energy recovery efficiency and discharge characteristics.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such flat panel displays include Liquid Crystal Display (LCD), Field Emission Display (FED), Plasma Display Panel (hereinafter referred to as "PDP") and Electroluminescence (Electro). -Luminescence (EL) display.

PDP is a display device using a gas discharge has the advantage that it is easy to manufacture a large panel. As a PDP, a three-electrode AC surface discharge type PDP having three electrodes and driven by an alternating voltage is typical.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a scan electrode Y and a sustain electrode Z formed on the upper substrate 10, and an address electrode formed on the lower substrate 18. X). Each of the scan electrode Y and the sustain electrode Z has a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z, and is formed on one side edge of the transparent electrode 12Y and 12Z. 13Z).

The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode Y and the sustain electrode Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode X is formed in the direction crossing the scan electrode Y and the sustain electrode Z. The partition wall 24 is formed in parallel with the address electrode X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert mixed gas is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The three-electrode AC surface discharge type PDP is driven by being divided into a plurality of subfields, and gray scale display is performed by emitting light a number of times proportional to the weight of video data in each subfield period. The subfield is driven again by being divided into an initialization period, an address period, a sustain period and an erase period.

Here, the initialization period is a period during which uniform wall charges are formed in the discharge cells, the address period is a period during which selective address discharge occurs according to the logic value of the video data, and the sustain period is a discharge cell in which the address discharge has occurred. It is a period in which discharge is maintained. The erase period is a period for erasing the sustain discharge generated in the sustain period.

The address discharge and the sustain discharge of the AC surface discharge PDP driven in this way require a high voltage of several hundred volts or more. Therefore, an energy recovery apparatus is used to minimize the driving power required for the address discharge and the sustain discharge. The energy recovery apparatus recovers the voltage between the scan electrode 12Y and the sustain electrode 12Z and uses the voltage recovered as the drive voltage at the next discharge.

Referring to FIG. 2, the energy recovery devices 30 and 32 of the plasma display panel proposed by Weber (USP-5081400) are symmetrically installed with the panel capacitor Cp interposed therebetween. Here, the panel capacitor Cp equivalently represents the capacitance formed between the scan electrode Y and the sustain electrode Z. FIG. In the energy recovery device, the first energy recovery device 30 supplies sustain pulses to the scan electrodes Y, and the second energy recovery device 32 operates while alternating with the first energy recovery device 30. A sustain pulse is supplied to the electrode Z.

The configuration of the energy recovery devices 30 and 32 of the conventional plasma display panel will be described with reference to the first energy recovery device 30. The first energy recovery device 30 includes the inductor L connected between the panel capacitor Cp and the source capacitor Cs, and the first and the first connected in parallel between the source capacitor Cs and the inductor L. 3 switches S1 and S3, a second switch S2 connected between the first capacitor N1 and the sustain voltage source Vs between the panel capacitor Cp and the inductor L, and the first node N1. ) And a fourth switch S4 connected between the ground voltage source GND.

The source capacitor Cs recovers and charges the voltage charged to the panel capacitor Cp during the sustain discharge, and supplies the charged voltage to the panel capacitor Cp again. The source capacitor Cs is charged with a voltage of Vs / 2 corresponding to half of the sustain voltage source Vs. The inductor L forms a resonance circuit together with the panel capacitor Cp. To this end, the first to fourth switches S1 to S4 control the flow of current. Meanwhile, the fifth and sixth diodes D5 and D6 provided between the first and second switches S1 and S2 and the inductor L respectively prevent current from flowing in the reverse direction.

3 is a timing diagram and waveform diagrams illustrating on / off timing of the first energy recovery device switches and an output waveform of the panel capacitor.

The operation process will be described in detail with the assumption that the voltage of 0 volts is charged in the panel capacitor Cp and the voltage of Vs / 2 is charged in the source capacitor Cs before the period t1.

In the t1 period, the first switch S1 is turned on to form a current path from the source capacitor Cs to the first switch S1, the inductor L, and the panel capacitor Cp. Accordingly, the voltage of Vs / 2 charged in the source capacitor Cs is supplied to the panel capacitor Cp. At this time, since the inductor L and the panel capacitor Cp form a series resonant circuit, the panel capacitor Cp is charged with the sustain voltage Vs which is twice the voltage of the source capacitor Cs.

In the t2 period, the second switch S2 is turned on while the first switch Q1 remains on. When the second switch S2 is turned on, the sustain voltage Vs is supplied to the scan electrode Y from the sustain voltage source Vs. The sustain voltage Vs supplied to the scan electrode Y prevents the voltage of the panel capacitor Cp from falling below the sustain voltage Vs so that the sustain discharge occurs normally. On the other hand, since the voltage of the panel capacitor Cp has risen to the sustain voltage Vs in the period t1, the driving power supplied from the outside to minimize the sustain discharge is minimized.

In the t3 period, the first switch S1 is turned off. At this time, the scan electrode Y maintains the sustain voltage Vs for a period of t3.

In the t4 period, the second switch S2 is turned off and the third switch S3 is turned on. When the third switch S3 is turned on, a current path from the panel capacitor Cp to the source capacitor Cs is formed through the inductor L and the third switch S3 to charge the panel capacitor Cp. The voltage is recovered to the source capacitor Cs. At this time, the source capacitor Cs is charged with a voltage of Vs / 2.

In the t5 period, the third switch S3 is turned off and the fourth switch S4 is turned on. When the fourth switch S4 is turned on, a current path is formed between the panel capacitor Cp and the base voltage source GND, so that the voltage of the panel capacitor Cp drops to 0V.

In the t6 period, the t5 state is maintained for a certain time. In practice, the AC drive pulses supplied to the scan electrode Y and the sustain electrode Z are obtained by periodically repeating the t1 to t6 periods.

Meanwhile, the second energy recovery device 32 alternately operates with the first energy recovery device 30 to supply a driving voltage to the panel capacitor Cp. Accordingly, the sustain capacitors Vs having opposite polarities are supplied to the panel capacitor Cp. As described above, the sustain voltage Vs having opposite polarities are supplied to the panel capacitor Cp, thereby causing sustain discharge in the discharge cells.

However, such a conventional energy recovery device and recovery method uses a series resonance between the inductor (L) and the panel capacitor (Cp), so the parasitic elements of the circuit do not completely soft switch the charge and discharge time of the panel. Since it is impossible to control each, there is a disadvantage in that good discharge characteristics and high recovery efficiency cannot be secured at the same time.

Accordingly, it is an object of the present invention to provide an energy recovery apparatus and method for a plasma display panel capable of improving energy recovery efficiency and discharge characteristics.

In order to achieve the above object, the energy recovery device of the plasma display panel according to the present invention includes a plasma display panel having a scan electrode and a sustain electrode for sustain discharge; First to third voltage sources for supplying a sustain voltage to the panel; A first inductor connected between the second voltage source and the scan electrode to recover energy stored in the panel; A second inductor connected between the third voltage source and the sustain electrode to recover energy stored in the panel and to resupply the recovered energy to the panel; A first switch connected between the first voltage source and the scan electrode and turned on when a sustain voltage is supplied to the scan electrode; A second switch connected between the first voltage source and the sustain electrode and turned on when a sustain voltage is supplied to the sustain electrode; A third switch connected between the sustain electrode and a ground voltage source and synchronized with the first switch when a sustain voltage is supplied to the scan electrode; And a fourth switch connected between the scan electrode and the ground voltage source and synchronized with the second switch when a sustain voltage is supplied to the sustain electrode.

The first to third voltage sources are characterized in that they are the same voltage source.

The second and third voltage sources may be different voltage sources from the first voltage source.

The second and third voltage sources may be independent power supplies supplied from the outside.

The first and second inductors are characterized in that they have the same inductance.

The second inductor has a larger inductance than the first inductor.

An energy recovery apparatus of a plasma display panel according to the present invention includes first and second source capacitors which are connected in series between the second voltage source and the base voltage source to divide a second voltage supplied from the second voltage source, Third and fourth source capacitors connected in series between a third voltage source and the base voltage source to divide a third voltage supplied from the third voltage source, a first node and the first node between the first and second source capacitors; A parallel connection between a fifth node and a sixth switch connected in parallel between one inductor and synchronized before a time point at which the energy stored in the panel is discharged, and a second node between the third and fourth source capacitors and the second inductor And seventh and eighth switches which are synchronized before a time point at which the panel is charged with energy.

An energy recovery apparatus of a plasma display panel according to the present invention includes a first diode connected between the fifth switch and the first inductor to prevent reverse current from the panel during discharge of the panel, the first inductor and the A second diode connected between the sixth switch to prevent reverse current from the first source capacitor when the panel is discharged, and connected between the seventh switch and the second inductor from the panel when charging the panel And a third diode for preventing reverse current and a fourth diode connected between the second inductor and the eighth switch to prevent reverse current from the third source capacitor during charging of the panel.

The first and third switches may form current paths such that a voltage from the first voltage source is supplied to the scan electrode.

The first and sixth switches are configured to form a current path so that energy from the first voltage source is stored in the first inductor before the discharge time of the panel.

The third and sixth switches are configured to form a current path such that energy from the panel is stored in the first inductor and the voltage stored in the panel is stored in the second source capacitor.

The third and fourth switches may form current paths such that the voltage of the panel becomes a base voltage.

The third and seventh switches may form a current path so that energy from a voltage charged in a fourth source capacitor is stored in the second inductor before a charging time of the panel.

The fourth and seventh switches may form current paths such that the second inductor and the panel form a resonance loop.

The second and fourth switches may be configured to form current paths such that a voltage from the first voltage source is supplied to the sustain electrode.

The fourth and fifth switches are configured to form a current path so that energy from a voltage charged in the second source capacitor is stored in the first inductor before a discharge time of the panel.

The first and second switches may form a current path such that the voltage of the panel becomes a base voltage.

The second and eighth switches may form a current path so that energy from the first voltage source is stored in the second inductor before a charging time of the panel.

The first and eighth switches may be configured to form a current path such that the voltage from the first voltage source is supplied to the scan electrode and the energy from the first voltage source is stored in the second inductor.

The energy recovery method of the plasma display panel according to the present invention is a method for recovering energy of a plasma display panel having a scan electrode and a sustain electrode for sustain discharge, the voltage of the panel by supplying a voltage from a sustain voltage source to the scan electrode A first step of maintaining at a positive sustain voltage; A second step of storing energy from the sustain voltage source in a first inductor before a discharge point of the panel; Storing energy discharged from the panel in the first inductor; Supplying a base voltage to the scan electrode and the sustain electrode to maintain the panel voltage at the base voltage; A fifth step of storing energy from a voltage charged in a first capacitor in a second inductor before a charging time of the panel; Forming a resonance loop between the panel and the second inductor to supply energy stored in the first inductor to the sustain electrode; A seventh step of supplying a voltage from the sustain voltage source to the sustain electrode to maintain the voltage of the panel at a negative sustain voltage; An eighth step of storing energy from a voltage charged in a second capacitor before the discharge point of the panel in the first inductor; A ninth step of supplying a sustain voltage to the scan electrode and the sustain electrode to maintain the voltage of the panel at a base voltage; A tenth step of storing energy from the sustain voltage supplied to the sustain electrode in the second inductor; And supplying a sustain voltage to the scan electrode to maintain the voltage of the panel at the sustain voltage.

The second step is characterized by including the first step.

The fourth step may include discharging energy stored in the first inductor.

The fifth step includes the fourth step.

The seventh step may include discharging the energy stored in the second inductor.

The eighth step may include the seventh step.

The tenth step may include the ninth step.

The eleventh step may include discharging energy stored in the second inductor.

Other objects and features of the present invention in addition to the above objects will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 23.

4 is a diagram illustrating an energy recovery apparatus of a plasma display panel according to an exemplary embodiment of the present invention.

Referring to FIG. 4, an energy recovery apparatus of a plasma display panel according to an exemplary embodiment of the present invention includes a panel capacitor Cp having a scan electrode Y and a sustain electrode Z for sustain discharge, and a panel capacitor Cp. First to third sustain voltage sources Vs1 to Vs3 for supplying a sustain voltage, first and second source capacitors Cs1 and Cs2 for distributing the sustain voltage supplied from the second sustain voltage source Vs2, and The first node N1 between the third and fourth source capacitors Cs3 and Cs4 for distributing the sustain voltage supplied from the third sustain voltage source Vs3 and the first and second source capacitors Cs1 and Cs2. ) And a first inductor L1 connected between the panel capacitor Cp and a second node N2 between the third and fourth source capacitors Cs3 and Cs4 and the panel capacitor Cp. Between the second inductor L2 and the first node N1 and the first inductor L1 First and third switches S1 and S3 connected in parallel; fifth and seventh switches S5 and S7 connected in parallel between the second node N2 and the second inductor L2; Ninth and tenth diodes D9 and D10 connected in series between third switches S1 and S3, and Eleventh and twelfth diodes D11 connected in series between fifth and seventh switches S5 and S7. D12 and a second switch S2 connected between the third node N3 and the first sustain voltage source Vs1 between the first inductor L1 and the scan electrode Y of the panel capacitor Cp. And a fourth switch S4 connected between the third node N3 and the ground voltage source GND, and a fourth node N4 between the second inductor L2 and the sustain electrode Z of the panel capacitor Cp. ) And a sixth switch S6 connected between the first sustain voltage source Vs1 and an eighth switch S8 connected between the fourth node N4 and the ground voltage source GND.

The panel capacitor Cp equivalently represents the capacitance formed between the scan electrode Y and the sustain electrode Z of the PDP. The panel capacitor Cp generates the sustain discharge by the sustain voltages having opposite polarities.

The first and second source capacitors Cs1 and Cs2 are connected in series between the second sustain voltage source Vs2 and the ground voltage source GND, respectively, to distribute the sustain voltages, and the third and fourth source capacitors Cs3 and Cs4. Are connected in series between the third sustain voltage source Vs3 and the ground voltage source GND, respectively, to distribute the sustain voltage. Here, the first source capacitor Cs1 recovers the voltage charged in the panel capacitor Cp during the sustain discharge, and the third source capacitor Cs3 recovers the voltage charged in the panel capacitor Cp during the sustain discharge. In addition, it is re-supplied to the panel capacitor (Cp). The first and second source capacitors Cs1 and Cs2 and the third and fourth source capacitors Cs3 and Cs4 may be configured as one capacitor, respectively. Here, the same voltage source is used for the second and third sustain voltage sources Vs2 and Vs3. In addition, the second and third sustain voltage sources Vs2 and Vs3 may be the same or different voltage sources as the first sustain voltage source Vs1. In other words, the second and third sustain voltage sources Vs2 and Vs3 may be voltage sources supplied independently from the outside.

The first and second inductors L1 and L2 recover and store energy from the panel capacitor Cp according to the switching of the first to eighth switches S1 to S8. In addition, the second inductor L2 supplies energy stored by the LC resonance with the panel capacitor Cp to the panel capacitor Cp. The first and second inductors L1 and L2 have the same inductance or different inductances to control the charge / discharge time of the panel capacitor Cp. That is, when the first and second inductors L1 and L2 have the same inductance, the charge / discharge time of the panel capacitor Cp is the same. However, when the inductance of the second inductor L2 is larger than the inductance of the first inductor L1, the charging time of the panel capacitor Cp is faster and the discharge time is slower. At this time, even if the inductances of the first and second inductors L1 and L2 are the same, controlling the switching timing of the auxiliary switch can make the charging time of the panel capacitor Cp faster and the discharge time slower.

The first switch S1 electrically connects the first node N1 to the third node N3 according to the first switching signal. The second switch S2 supplies the sustain voltage to the third node N3 according to the second switching signal. The third switch N3 electrically connects the third node N3 to the first node N1 according to the third switching signal. The fourth switch S4 electrically connects the third node N3 to the ground voltage source GND according to the fourth switching signal. The fifth switch S5 electrically connects the second node N2 to the fourth node N4 according to the fifth switching signal. The sixth switch S6 supplies the sustain voltage to the fourth node N4 according to the sixth switching signal. The seventh switch S7 electrically connects the fourth node N4 to the second node N2 according to the seventh switching signal. The eighth switch S8 electrically connects the fourth node N4 to the ground voltage source GND according to the eighth switching signal. Here, the first and third switches S1 and S3 increase or decrease the current of the first inductor L1 before the discharge point of the panel capacitor Cp, and the fifth and seventh switches S5 and S7 It is used as an auxiliary switch to increase or decrease the current of the second inductor L2 before the charging time of the panel capacitor Cp. In addition, the second and sixth switches S2 and S6 and the fourth and eighth switches S4 and S8 maintain the voltage of the panel capacitor Cp at the sustain voltage and measure the voltage of the panel capacitor Cp. It is used as the main switch to keep the low voltage, i. Accordingly, since sufficient energy is stored in the first and second inductors L1 and L2 before the charging / discharging time of the panel capacitor Cp, and the sufficient amount of stored energy is used to charge / discharge the panel capacitor Cp. Soft switching of the main switch, which maintains the sustain voltage and the ground voltage, is possible. The first to eighth switches S1 to S8 control the flow of current while being turned on and off according to the first to eighth switching signals, and are configured to prevent reverse current during turn-on. And first and eighth diodes D1 to D8, respectively. Each of the first to eighth switches S1 to S8 is formed of any one of a semiconductor switch element, for example, a MOSFET, an IGBT, an SCR, and a BJT.

The ninth diode D9 is connected between the first switch S1 and the first inductor L1 to prevent reverse current from the panel capacitor Cp when the panel capacitor Cp is discharged. D10 is connected between the first inductor L1 and the third switch S3 to prevent reverse current from the first source capacitor Cs1 upon discharge of the panel capacitor Cp. In addition, the eleventh diode D11 is connected between the fifth switch S5 and the second inductor L2 to prevent reverse current from the panel capacitor Cp when the panel capacitor Cp is charged. The diode D12 is connected between the second inductor L2 and the seventh switch S7 to prevent reverse current from the third source capacitor Cs3 when the panel capacitor Cp is charged.

The energy recovery apparatus of the PDP according to the embodiment of the present invention can control the charge / discharge time of the panel capacitor Cp by adjusting the inductances of the first and second inductors L1 and L2. In other words, if the inductances of the first and second inductors L1 and L2 are the same, the charge / discharge times of the panel capacitor Cp may be the same as shown in FIG. 5. However, when the inductance of the second inductor L2 is larger than the inductance of the first inductor L1, more energy is stored in the second inductor L2 than the energy stored in the first inductor L1. As described above, the charging speed of the panel capacitor Cp is increased and the discharge speed is slowed. As a result, not only the discharge characteristics of the panel capacitor Cp can be improved but also the energy recovery efficiency can be increased.

FIG. 7 is a timing diagram and waveform diagrams illustrating on / off timings of the switches illustrated in FIG. 4 and voltages applied to panel capacitors and currents of inductors.

Here, the scan electrode (Y) of the panel capacitor (Cp) will be described with the positive polarity (+) and the sustain electrode (Z) with the negative polarity (−).

Referring to FIG. 7, before the t0 period, the second and eighth switches S2 and S8 are turned on by the second and eighth switching signals in the high state. Accordingly, as shown in FIG. 8, the first sustain voltage source Vs1, the second switch S2, the third node N3, the panel capacitor Cp, the fourth node N4, and the eighth switch S8. And a current path leading to the ground voltage source GND. As a result, since the sustain voltage is supplied to the scan electrode Y of the panel capacitor Cp, the panel capacitor Cp maintains the sustain voltage of positive polarity (+).

In the t0 period, the second and eighth switches S2 and S8 maintain the previous on state, and the third switch S3 is turned on by the third switching signal in the high state. Accordingly, as shown in FIG. 9, the first sustain voltage source Vs1, the second switch S2, the third node N3, the panel capacitor Cp, the fourth node N4, and the eighth switch S8. ) And the first current path leading to the ground voltage source GND, the first sustain voltage source Vs1, the second switch S2, the third node N3, the first inductor L1, the tenth diode D10, A second current path is formed that leads to the third switch S3, the first node N1, the first source capacitor Cs1, and the ground voltage source GND. As a result, the panel capacitor Cp maintains a sustain voltage, and a negative current flows through the first inductor L1 by the sustain voltage supplied from the first sustain voltage source Vs1. Accordingly, the first inductor L1 stores energy supplied from the first sustain voltage source Vs1.

In the t1 period, the third and eighth switches S3 and S8 maintain the previous on state, and the second switch S2 is turned off by the second switching signal in the low state. Accordingly, as shown in FIG. 10, the base voltage source GND, the eighth switch S8, the fourth node N4, the panel capacitor Cp, the third node N3, the first inductor L1, A current path is formed that leads to the tenth diode D10, the third switch S3, the first node N1, the first source capacitor Cs1, and the ground voltage source GND. At this time, the panel capacitor Cp discharges the sustain voltage stored therein to supply the first inductor L1 to be lowered to 0V at the sustain voltage. In addition, since the first inductor L1 receives the sustain voltage from the panel capacitor Cp, the energy stored therein is maximized by the supplied sustain voltage. That is, a minimum current flows through the first inductor L1.

In the t2 period, the third and eighth switches S3 and S8 maintain the previous on state, and the fourth switch S4 is turned on by the fourth switching signal in the high state. Accordingly, as shown in FIG. 11, the eighth switch S8, the fourth node N4, the panel capacitor Cp, the third node N3, the fourth switch S4, and the base voltage source GND are illustrated. Subsequent first current path and ground voltage source GND, fourth switch S4, third node N3, first inductor L1, tenth diode D10, third switch S3, first node A second current path is formed that leads to N1 and the first source capacitor Cs1. At this time, the panel capacitor Cp maintains 0V or the base voltage by the first current path. In addition, since the energy stored in the first inductor L1 is discharged toward the first source capacitor Cs1 through the second current path, the current flowing in the first inductor L1 is reduced. In other words, the current of negative polarity (-) flowing in the first inductor L1 increases to zero (the current does not flow).

In the t3 period, the fourth and eighth switches S4 and S8 maintain the previous on state, and the third switch S3 is turned off by the third switching signal in the low state. Accordingly, as shown in FIG. 12, the eighth switch S8, the fourth node N4, the panel capacitor Cp, the third node N3, the fourth switch S4, and the base voltage source GND are illustrated. A subsequent current path is formed. For this reason, the panel capacitor Cp maintains 0V, and no current flows through the first inductor L1.

In the t4 period, the fourth and eighth switches S4 and S8 maintain the previous on state, and the fifth switch S5 is turned on by the fifth switching signal in the high state. Accordingly, as shown in FIG. 13, the fourth switch S4, the third node N3, the panel capacitor Cp, the fourth node N4, the eighth switch S8, and the ground voltage source GND are illustrated. The first current path and the third sustain voltage source (Vs3), the fourth source capacitor (Cs4), the second node (N2), the fifth switch (S5), the second inductor (L2), the fourth node (N4), A first current path is formed that leads to the eighth switch S8 and the ground voltage source GND. At this time, the panel capacitor Cp is maintained at 0V due to the first current path, and the voltage of the second inductor L2 is applied to the second node N2, that is, the voltage charged in the third source capacitor Cs3. Positive current flows. Accordingly, the second inductor L2 stores energy supplied from the distributed sustain voltage. At this time, the energy stored in the second inductor (L2) is the speed stored in the first inductor (L1) as shown in FIG. Will be stored at a faster rate.

 In the t5 period, the fourth and fifth switches S4 and S5 maintain the previous on state, and the eighth switch S8 is turned off by the eighth switching signal in the low state. Accordingly, as shown in FIG. 14, the third sustain voltage source Vs3, the fourth source capacitor Cs4, the second node N2, the fifth switch S5, the eleventh diode D11, and the second inductor A current path is connected to L2, the fourth node N4, the panel capacitor Cp, the third node N3, the fourth switch S4, and the ground voltage source GND. For this reason, the energy stored in the second inductor L2 is maximized by the distributed sustain voltage. That is, the maximum current flows through the second inductor L2. In addition, since the second inductor L2 forms a resonance loop with the panel capacitor Cp, energy stored in the second inductor L2 is supplied to the panel capacitor Cp by LC resonance with the panel capacitor Cp. In this case, since the panel capacitor Cp forms a resonance loop with the second inductor L2, the panel capacitor Cp receives energy from the second inductor L2 by LC resonance. For this reason, the panel capacitor Cp is charged with a voltage falling from 0V to the negative sustain voltage.

In the period t6, the fourth and fifth switches S4 and S5 maintain the previous on state, and the sixth switch S6 is turned on by the sixth switching signal in the high state. Accordingly, as shown in FIG. 15, the third sustain voltage source Vs3, the fourth source capacitor Cs4, the second node N2, the fifth switch S5, the eleventh diode D11, and the second inductor The first current path leading to L2 and the fourth node N4, the first sustain voltage source Vs1, the sixth switch S6, the fourth node N4, the panel capacitor Cp, and the third node N3. ), A second current path leading to the fourth switch S4 and the ground voltage source GND is formed. As a result, the panel capacitor Cp maintains the negative sustain voltage by the second current path. At this time, since both ends of the second inductor L2 are supplied with the opposite polarity and the same sustain voltage, the current flowing through the second inductor L2 is reduced.

In the t7 period, the fourth and sixth switches S4 and S6 maintain the previous on state, and the fifth switch S5 is turned off by the fifth switching signal in the low state. Accordingly, as shown in FIG. 16, the first sustain voltage source Vs1, the sixth switch S6, the fourth node N4, the panel capacitor Cp, the third node N3, and the fourth switch S4. And a current path leading to the ground voltage source GND. As a result, the panel capacitor Cp maintains a negative sustain voltage, and no current flows through the second inductor L2.

In the t8 period, the fourth and sixth switches S4 and S6 maintain the previous on state, and the first switch S1 is turned on by the first switching signal in the high state. Accordingly, as shown in FIG. 17, the first sustain voltage source Vs1, the sixth switch S6, the fourth node N4, the panel capacitor Cp, the third node N3, and the fourth switch S4. ) And a first current path leading to the ground voltage source GND, the second sustain voltage source Vs2, the second source capacitor Cs2, the first node N1, the first switch S1, and the ninth diode D9. A second current path is formed that leads to the first inductor L1, the third node N3, the fourth switch S4, and the ground voltage source GND. In this case, the panel capacitor Cp maintains the negative sustain voltage of the negative polarity by the first current path, and the voltage applied to the first node N1 at the first inductor L1, that is, the first source capacitor Cs1. The positive current flows due to the voltage charged in the.

In the t9 period, the first and sixth switches S1 and S6 maintain the previous on state, and the fourth switch S4 is turned off by the fourth switching signal in the low state. Accordingly, as shown in FIG. 18, the first current path, the second sustain voltage source Vs, and the second source capacitor leading to the first sustain voltage source Vs1, the sixth switch S6, and the fourth node N4 are shown. A second current path is formed that leads to Cs2, the first node N1, the first switch S1, the ninth diode D9, the first inductor L1, and the third node N3. In this case, since the sustain voltage of the same magnitude is supplied to the scan electrode Y and the sustain electrode Z, that is, the third node N3 and the fourth node N4 of the panel capacitor Cp, the panel capacitor Cp The charged negative voltage (-) is discharged. As a result, the voltage charged in the panel capacitor Cp rises to 0 V or the base voltage from the negative polarity (−) sustain voltage. In addition, the energy stored in the first inductor L1 is maximized by the voltage applied to the first node N1, that is, the voltage charged in the first source capacitor Cs1. In other words, the maximum current flows through the first inductor L1.

In the t10 period, the first and sixth switches S1 and S6 maintain the previous on state, and the second switch S2 is turned on by the second switching signal in the high state. Accordingly, as shown in FIG. 19, the first current path, the second sustain voltage source Vs2, and the second source capacitor which lead to the first sustain voltage source Vs1, the sixth switch S6, and the fourth node N4. The second current path and the first sustain voltage source (Cs2), the first node N1, the first switch S1, the ninth diode D9, the first inductor L1, and the third node N3. Vs1), a third current path leading to the second switch S2 and the third node N3 is formed. Accordingly, since the sustain voltage of the same magnitude is supplied to the scan electrode Y and the sustain electrode Z, that is, the third node N3 and the fourth node N4 of the panel capacitor Cp, the panel capacitor Cp is Maintaining 0V, the current flowing in the first inductor L1 decreases due to the sustain voltage applied to the third node N3.

In the t11 period, the second and sixth switches S2 and S6 maintain the previous on state, and the first switch S1 is turned off by the first switching signal in the low state. Accordingly, as illustrated in FIG. 20, the first current path, the first sustain voltage source Vs1, and the second switch that lead to the first sustain voltage source Vs1, the sixth switch S6, and the fourth node N4 are included. A second current path is formed that leads to S2) and the third node N3. Accordingly, since the sustain voltage of the same magnitude is supplied to the scan electrode Y and the sustain electrode Z, that is, the third node N3 and the fourth node N4 of the panel capacitor Cp, the panel capacitor Cp is 0V is maintained and no current flows through the first inductor L1.

In the t12 period, the second and sixth switches S2 and S6 maintain the previous on state, and the seventh switch S7 is turned on by the seventh switching signal in the high state. Accordingly, as illustrated in FIG. 21, the first current path, the first sustain voltage source Vs1, and the sixth switch (the first sustain voltage source Vs1, the second switch S2, and the third node N3) are connected to each other. S6, the fourth node N4, the second inductor L2, the twelfth diode D12, the seventh switch S7, the second node N2, the third source capacitor Cs3, and the ground voltage source GND A second current path is formed that leads to. At this time, since the sustain voltage of the same magnitude is supplied to the scan electrode Y and the sustain electrode Z of the panel capacitor Cp, that is, the third node N3 and the fourth node N4, the panel capacitor Cp is 0V. Is maintained, and a negative current flows through the second inductor L2 by the sustain voltage supplied through the second current path. Accordingly, the second inductor L2 stores energy supplied from the first sustain voltage source Vs1. At this time, the energy stored in the second inductor (L2) is the speed stored in the first inductor (L1) as shown in Figure 6 when the inductance of the second inductor (L2) is larger than the inductance of the first inductor (L1) Will be stored at a faster rate.

In the t13 period, the second and seventh switches S2 and S7 maintain the previous on state, and the sixth switch S6 is turned off by the sixth switching signal in the low state. Accordingly, as shown in FIG. 22, the first sustain voltage source Vs1, the second switch S2, the third node N3, the panel capacitor Cp, the fourth node N4, and the second inductor L2. ), A current path leading to the twelfth diode D12, the seventh switch S7, the second node N2, the third source capacitor Cs3, and the ground voltage source GND is formed. As a result, the panel capacitor Cp is charged with a voltage rising from 0V to a positive sustain voltage of positive polarity, and the energy stored therein is maximized in the second inductor L2 by the sustain voltage. That is, the minimum current flows through the second inductor L2.

In the t14 period, the second and seventh switches S2 and S7 maintain the previous on state, and the eighth switch S8 is turned on by the eighth switching signal in the high state. Accordingly, as shown in FIG. 23, the first sustain voltage source Vs1, the second switch S2, the third node N3, the panel capacitor Cp, the fourth node N4, and the eighth switch S8. ) And the first current path leading to the ground voltage source GND, the ground voltage source GND, the eighth switch S8, the fourth node N4, the second inductor L2, the twelfth diode D12, and the seventh. A second current path is formed that leads to the switch S7, the second node N2, and the third source capacitor Cs3. At this time, the panel capacitor Cp maintains a positive sustain voltage of positive polarity by the sustain voltage supplied to the third node N3. In addition, since the energy stored therein is discharged toward the third source capacitor Cp through the second current path, the current flowing through the second inductor L2 is reduced. In other words, the current of the negative polarity (−) flowing in the second inductor L2 increases to zero (the current does not flow).

After the period t14, the second and eighth switches S2 and S8 maintain the previous on state, and the seventh switch S7 is turned off by the seventh switching signal in the low state. Accordingly, as shown in FIG. 8, the first sustain voltage source Vs1, the second switch S2, the third node N3, the panel capacitor Cp, the fourth node N4, and the eighth switch S8. And a current path leading to the ground voltage source GND. As a result, the panel capacitor Cp maintains a positive sustain voltage of positive polarity, and no current flows through the second inductor L2.

As described above, in the energy recovery method of the PDP according to the embodiment of the present invention, the first, third, fifth, and seventh switching signals in the high state are supplied before the panel capacitor Cp is charged / discharged. The first and second inductors are increased by turning on the first and third switches S1 and S3 and the fifth and seventh switches S5 and S7 to increase the current flowing in the first and second inductors L1 and L2. Since sufficient energy is stored in (L1, L2), the panel capacitor Cp is charged / discharged using the stored energy, so that the second and fourth switches S2 and S4 and the sixth and eighth switches, which are main switches, are used. Soft switching of (S6, S8) can be enabled.

As described above, the energy recovery device and recovery method of the plasma display panel according to the embodiment of the present invention to increase the inductance of the second inductor than the inductance of the first inductor to increase the charge time of the panel capacitor and slow the discharge time As a result, not only the discharge characteristics of the plasma display panel can be improved, but also the energy recovery efficiency can be increased.

In addition, the auxiliary switch stores sufficient energy in the first and second inductors and uses the stored energy to charge / discharge the panel capacitors, thereby enabling soft switching of the main switch to maintain the sustain voltage and the base voltage. have.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (27)

A plasma display panel having a scan electrode and a sustain electrode for sustain discharge; First to third voltage sources for supplying a sustain voltage to the panel; A first inductor connected between the second voltage source and the scan electrode to recover energy stored in the panel; A second inductor connected between the third voltage source and the sustain electrode to recover energy stored in the panel and to resupply the recovered energy to the panel; A first switch connected between the first voltage source and the scan electrode and turned on when a sustain voltage is supplied to the scan electrode; A second switch connected between the first voltage source and the sustain electrode and turned on when a sustain voltage is supplied to the sustain electrode; A third switch connected between the sustain electrode and a ground voltage source and synchronized with the first switch when a sustain voltage is supplied to the scan electrode; And a fourth switch connected between the scan electrode and the base voltage source and synchronized with the second switch when a sustain voltage is supplied to the sustain electrode. The method of claim 1, The energy recovery device of the plasma display panel, characterized in that the first to third voltage sources are the same voltage source. The method of claim 1, And the second and third voltage sources are different voltage sources from the first voltage source. The method of claim 3, wherein And the second and third voltage sources are independent power supplies supplied from the outside. The method of claim 1, And the first and second inductors have the same inductance. The method of claim 1, And the second inductor has a larger inductance than the first inductor. The method of claim 1, First and second source capacitors connected in series between the second voltage source and the base voltage source to divide a second voltage supplied from the second voltage source; Third and fourth source capacitors connected in series between the third voltage source and the base voltage source to divide a third voltage supplied from the third voltage source; Fifth and sixth switches connected in parallel between a first node and the first inductor between the first and second source capacitors and synchronized before a time point at which the energy stored in the panel is discharged; And a seventh and eighth switch connected in parallel between the second node and the second inductor between the third and fourth source capacitors and synchronized before the time point at which the panel is charged with energy. Energy recovery device for display panel. The method of claim 7, wherein A first diode connected between the fifth switch and the first inductor to prevent reverse current from the panel when the panel is discharged; A second diode connected between the first inductor and the sixth switch to prevent reverse current from the first source capacitor when the panel is discharged; A third diode connected between the seventh switch and a second inductor to prevent reverse current from the panel when the panel is charged; And a fourth diode connected between the second inductor and the eighth switch to prevent a reverse current from the third source capacitor when the panel is being charged. The method of claim 8, And the first and third switches form a current path such that a voltage from the first voltage source is supplied to the scan electrode. The method of claim 8, And the first and sixth switches form a current path so that energy from the first voltage source is stored in the first inductor before a discharge time of the panel. The method of claim 8, The third and sixth switches form a current path such that energy from the panel is stored in the first inductor and the voltage stored in the panel is stored in the second source capacitor. Recovery device. The method of claim 8, And the third and fourth switches form a current path such that the voltage of the panel becomes a base voltage. The method of claim 8, And the third and seventh switches form a current path so that energy from a voltage charged in a fourth source capacitor is stored in the second inductor before a charging time of the panel. . The method of claim 8, And the fourth and seventh switches form a current path such that the second inductor and the panel form a resonant loop. The method of claim 8, And the second and fourth switches form a current path such that a voltage from the first voltage source is supplied to the sustain electrode. The method of claim 8, The fourth and fifth switches form a current path so that energy from a voltage charged in the second source capacitor is stored in the first inductor before a discharge time of the panel. Device. The method of claim 8, And the first and second switches form a current path such that the voltage of the panel becomes a base voltage. The method of claim 8, And the second and eighth switches form a current path so that energy from the first voltage source is stored in the second inductor before the panel is charged. The method of claim 8, And the first and eighth switches form a current path such that the voltage from the first voltage source is supplied to the scan electrode and the energy from the first voltage source is stored in the second inductor. Energy recovery device. In the energy recovery method of the plasma display panel having a scan electrode and a sustain electrode for sustain discharge, A first step of supplying a voltage from a sustain voltage source to the scan electrode to maintain the voltage of the panel at a positive sustain voltage; A second step of storing energy from the sustain voltage source in a first inductor before a discharge point of the panel; Storing energy discharged from the panel in the first inductor; Supplying a base voltage to the scan electrode and the sustain electrode to maintain the panel voltage at the base voltage; A fifth step of storing energy from a voltage charged in a first capacitor in a second inductor before a charging time of the panel; Forming a resonance loop between the panel and the second inductor to supply energy stored in the first inductor to the sustain electrode; A seventh step of supplying a voltage from the sustain voltage source to the sustain electrode to maintain the voltage of the panel at a negative sustain voltage; An eighth step of storing energy from a voltage charged in a second capacitor before the discharge point of the panel in the first inductor; A ninth step of supplying a sustain voltage to the scan electrode and the sustain electrode to maintain the voltage of the panel at a base voltage; A tenth step of storing energy from the sustain voltage supplied to the sustain electrode in the second inductor; And an eleventh step of supplying a sustain voltage to the scan electrodes to maintain the voltage of the panel at the sustain voltage. The method of claim 20, And said second step comprises said first step. The method of claim 20, And the fourth step includes discharging energy stored in the first inductor. The method of claim 20, The fifth step includes the fourth step, the energy recovery method of the plasma display panel. The method of claim 20, The seventh step includes the step of discharging the energy stored in the second inductor. The method of claim 20, And the eighth step comprises the seventh step. The method of claim 20, And the tenth step includes the ninth step. The method of claim 20, The eleventh step includes discharging energy stored in the second inductor.

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