KR20060053554A - Reference voltage generator for memory device - Google Patents

Abstract

The present invention relates to a reference voltage generator for a memory device that generates a stable reference voltage by minimizing a change in the reference voltage due to temperature change. According to the present invention, there is provided a reference voltage generator for a memory device, the generator comprising: voltage distribution means connected between an external power source and a ground terminal and dividing the external power source into a plurality of voltage levels; A switching unit which selects one voltage level among the plurality of voltage levels output by the voltage distribution unit and supplies the selected one voltage level to a memory device; First control means for enabling the switching unit and determining a level of a voltage selected and supplied by the switching unit; And second control means for detecting the level of the voltage selected by the external power source and the switching unit to enable the first control means.

Description

Reference voltage generator for memory device

1 is a view for explaining a conventional reference voltage generator for a memory device.

2 is a graph showing reference voltages according to temperatures of a conventional reference voltage generator for a memory device.

3 is a view for explaining a reference voltage generator for a memory device according to the present invention.

Explanation of symbols on the main parts of the drawings

11, 12, 13, 14, 15, 31: switching means 16, 17, 32, 35, 36: control means

18, 33: voltage distribution means 19, 34: switching unit

The present invention relates to a reference voltage generator for a memory device, and more particularly, to a reference voltage generator for a memory device for generating a reference voltage of a stable level by minimizing the fluctuation of the reference voltage due to temperature changes.

In general, the memory device converts an external voltage VDD supplied from the outside into a reference voltage through a reference voltage generator provided therein and supplies the same to the memory device.

1 is a diagram illustrating a conventional reference voltage generator for a memory device.

The reference voltage generator for a conventional memory device includes switching means (11, 12, 13, 14, 15), control means (16, 17), voltage distribution means (18), and switching unit (19). The first switching means 11 is connected to the external voltage VDD and is enabled by the output signal Vref0 of the first control means 16. When the first switching means 11 is enabled, the external voltage VDD is transmitted to the voltage distribution means 18. The voltage distribution means 18 includes a plurality of resistors Rn, Rn-1, Rn-2, ..., R4, R3, R2, R1 connected in series between the output terminal of the first switching means 11 and the ground terminal. ). The voltage dividing means 18 is an external voltage VDD transmitted from the first switching means 11 in accordance with the resistance ratio of the resistors Rn, Rn-1, Rn-2, ..., R4, R3, R2, R1. ) Is divided into a plurality of voltage levels and applied to the switching unit 19.

The switching unit 19 has a plurality of switching means, and one of the plurality of switching means is enabled by the output signals C1, C2, ..., Ci of the second control means 17. The enabled switching means supplies one of the plurality of voltage levels received from the voltage distribution means 18 to the memory device as the reference voltage Vref1. The second to fifth switching means 12, 13, 14, and 15 are connected in parallel with the resistance elements Rn, Rn-1, R2, and R1 of the voltage distribution means 18, respectively, and the second control means 17 Is enabled by the output signals level1 and level2. The second to fifth switching means 12, 13, 14, and 15 are disabled when the voltage level of the external voltage VDD transmitted from the first switching means 11 is higher than or equal to the reference value. When low, it is enabled. That is, the second to fifth switching means 12, 13, 14, and 15 minimize variation of the reference voltage Vref1 due to the level change of the external voltage VDD.

In the conventional reference voltage generator for a memory device, as the second to fifth switching means 12, 13, 14, and 15 are configured as PMOS transistors, characteristics of the PMOS transistors are changed according to temperature changes. . As a result, as shown in FIG. 2, the reference voltage Vref1 does not maintain a constant level 22 in response to a change in temperature, and the level changes 21. In other words, the reference voltage supplied to the memory device varies according to the change in temperature, so that the memory device may operate unstablely.

Accordingly, the present invention was created to solve the problems inherent in the reference voltage generator for a memory device according to the prior art as described above, and an object of the present invention is to stabilize by minimizing the fluctuation of the reference voltage due to temperature change. A reference voltage generator for a memory device for supplying a reference voltage of a level to a memory device is provided.

In order to achieve the above object, according to an aspect of the present invention, there is provided a reference voltage generator for a memory device: the generator is connected between an external power source and a ground terminal, and the external power source is connected to a plurality of voltages. Voltage distribution means for dividing into levels; A switching unit which selects one voltage level among the plurality of voltage levels output by the voltage distribution unit and supplies the selected one voltage level to a memory device; First control means for enabling the switching unit and determining a level of a voltage selected and supplied by the switching unit; And second control means for detecting the level of the voltage selected by the external power source and the switching unit to enable the first control means.

According to another aspect of the present invention, the voltage distribution means includes a plurality of resistance elements connected in series between the external power source and the ground terminal; The voltage divider outputs the plurality of voltage levels by connecting the node of each resistor element and the output terminal of the voltage divider.

According to another aspect of the invention, the generator further comprises a switching means connected between the external power supply and the voltage distribution means, and a third control means for enabling the switching means.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a view for explaining a reference voltage generator for a memory device according to the present invention.

The reference voltage generator for a memory device of the present invention includes a switching means 31, a voltage distribution means 33, a switching part 34, and control means 32, 35, and 36. The switching means 31 includes a PMOS transistor T1 connected to the external voltage VDD and is enabled by the output signal Vref0 of the first control means 35. That is, the PMOS transistor T1 is turned on and off by the output signal Vref0 of the first control means 35 applied to the gate terminal of the PMOS transistor T1, and the PMOS transistor T1 is turned on so that the PMOS transistor T1 is turned on. When the first switching means 31 is enabled, the external voltage VDD is transmitted to the voltage distribution means 33.

The first control means 35 includes an operational amplifier (OP), the non-inverting terminal and the output terminal of the operational amplifier (OP) is connected in common, the inverting terminal of the operational amplifier (OP) to the reference voltage (externally set) Vref) is applied. The voltage distribution means 33 includes a plurality of resistance elements Rn, Rn-1, Rn-2, ..., R4, R3, R2, R1 connected in series between the output terminal of the switching means 31 and the ground terminal. do. The voltage dividing means 33 receives the external voltage VDD transferred from the switching means 31 according to the resistance ratio of the resistors Rn, Rn-1, Rn-2, ..., R4, R3, R2, R1. The voltage is divided into a plurality of voltage levels and applied to the switching unit 34. The node of each resistor element (Rn, Rn-1, Rn-2, ..., R4, R3, R2, R1) and the output terminal of the voltage distribution means 33 are connected so that the voltage distribution means 33 has a plurality of voltage levels. Outputs

The switching unit 34 includes a plurality of PMOS transistors P1, P2, ..., Pi-3, Pi-2, Pi-1, Pi as switching means. The gate terminals of the PMOS transistors P1, P2, ..., Pi-3, Pi-2, Pi-1, Pi are output signals S1, S2, ..., Si-3, Si- of the second control means 32. 2, Si-1, Si are applied, and a plurality of PMOS transistors P1, P2, ..., Pi are generated by these output signals S1, S2, ..., Si-3, Si-2, Si-1, Si. -3, Pi-2, Pi-1, Pi are turned on and off. That is, the PMOS transistors P1, P2, ..., Pi-3, Pi-2, of the switching unit 34 are output by the output signals S1, S2, ..., Si-3, Si-2, Si-1, Si. One of the PMOS transistors of Pi-1 and Pi is turned on, and one of the plurality of voltage levels delivered from the voltage distribution means 33 is selected by the turned-on PMOS transistor. As a result, the switching unit 34 supplies the selected one voltage level as the reference voltage Vref1 to the memory device.

The third control means 36 includes an external voltage VDD transmitted by the switching means 31 to the voltage distribution means 33 and a reference voltage Vref1 selected by the switching unit 34 and supplied to the memory device. Detects a voltage level and applies output signals level1, level2, C1, C2, ..., Ci to the second control means 32. In other words, the third control means 36 detects the level of the external voltage VDD, detects the level of the output signals level1 and level2 and the reference voltage Vref1 indicating the level, and outputs the level indicating the level. (C1, C2, ..., Ci) is applied to the second control means 32.

The second control means 32 is a multiplexer which is a digital switching means, and is enabled by the output signals level1, level2, C1, C2, ..., Ci of the third control means 36. The second control means 32 receives output signals C1, C2, ..., Ci representing the level of the reference voltage Vref1 as input signals, and output signals level1, representing the level of the external voltage VDD. level2) is received as a switching signal. The second control means 32 is enabled by these signals level1, level2, C1, C2, ..., Ci, and when enabled, the output signals S1, S2, ..., Si-3, Si-. 2, Si-1, Si) is applied to the switching unit 34. At this time, the second control means 32 according to the signals level1, level2, C1, C2, ..., Ci received from the third control means 36, that is, the level of the external voltage VDD and the reference voltage ( According to the level of Vref1), one of the output signals S1, S2, ..., Si-3, Si-2, Si-1, Si is enabled at a low level and applied to the switching unit 34. As a result, only one PMOS transistor among the plurality of PMOS transistors P1, P2, ..., Pi-3, Pi-2, Pi-1, Pi provided in the switching unit 34 is turned on, and the switching unit ( 34 selects one of the voltage levels and supplies it to the memory device as a reference voltage Vref1.

In the reference voltage generator for the memory device according to the present invention, the switching unit 34 is enabled by the second control means 32 operating according to the voltage level of the external voltage VDD and the reference voltage Vref1. As a result, the variation of the reference voltage Vref1 due to the level change of the external voltage VDD is minimized. In addition, the variation of the characteristics of the second control means 32 according to the temperature change is minimized, thereby minimizing the variation of the reference voltage Vref1 according to the temperature change.

According to the configuration as described above of the present invention, by minimizing the fluctuation of the reference voltage according to the change of the external voltage and the temperature, a stable level of the reference voltage can be supplied to the memory device, and as a result, the memory device can be stably operated. .

While the invention has been shown and described with reference to specific embodiments, the invention is not so limited, and it is to be understood that the invention is capable of various modifications without departing from the spirit or field of the invention as set forth in the claims below. It will be readily apparent to one of ordinary skill in the art that modifications and variations can be made.

Claims (3)

A reference voltage generator for a memory device, A voltage distribution means connected between an external power source and a ground terminal and dividing the external power source into a plurality of voltage levels; A switching unit which selects one voltage level among the plurality of voltage levels output by the voltage distribution unit and supplies the selected one voltage level to a memory device; First control means for enabling the switching unit and determining a level of a voltage selected and supplied by the switching unit; And And second control means for detecting the level of the voltage selected by the external power source and the switching unit to enable the first control means. The method of claim 1, The voltage distribution means includes a plurality of resistance elements connected in series between the external power source and the ground terminal; And a node of each resistor element and an output terminal of the voltage divider are connected so that the voltage divider outputs the plurality of voltage levels. The method of claim 1, The generator further comprises a switching means connected between the external power source and the voltage distribution means, and a third control means for enabling the switching means.

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