KR20060046085A - Semiconductor test system - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus, which uses a calibration wafer having a short circuit, has a low failure rate, minimizes calibration time, and realizes a highly accurate semiconductor test apparatus.

The present invention is an improvement of a semiconductor test apparatus in which skew adjustment between pins is performed by bringing a probe of a probe card into contact with a pad of a calibration wafer having pads in the same arrangement as the pin array of the device under test. will be. The apparatus includes a contact pad provided on a probe card and a reference pin means provided on a surface of a calibration wafer facing the contact pad and electrically contacting the contact pad.

Semiconductors, Calibration, Relays, Comparators, Drivers

Description

Semiconductor Test Equipment {SEMICONDUCTOR TEST SYSTEM}

1 is a functional block diagram showing the configuration of a conventional semiconductor test apparatus disclosed in Patent Document 1. As shown in FIG.

2 is a side view of an essential part showing an embodiment of a semiconductor test apparatus to which the present invention is applied.

3 is a diagram illustrating a configuration of a calibration wafer 400 of the apparatus shown in FIG. 2.

4 is a plan view of a calibration chip showing another embodiment of the present invention.

Cited Reference 1: Japanese Unexamined Patent Publication No. 11 (1999) -190760

The present invention is a semiconductor for performing pin-to-pin skew adjustment by bringing a probe of a test apparatus into contact with a pad of a calibration wafer having a pad array identical to the pin array of a device under test (DUT: Device Under Test). It relates to a test apparatus.

As a prior art document in which skew (timing error) adjustment (hereinafter, referred to as calibration) between pins is performed by contacting a probe of a test apparatus with a pad of a calibration wafer having pads of the same arrangement as the pin array of the DUT. There is.

1 is a functional block diagram showing the structure of a conventional semiconductor test apparatus disclosed in Reference Document 1. As shown in FIG. The test apparatus is characterized in that the pin arrangement of the DUT and the pin arrangement of the DUT are improved in order to improve the accuracy error of the conventional time domain reflect (TDR) method by opening the transmission line from the driver to the probe and from the probe to the comparator. It is an inspection method using a short DUT having the same pin arrangement as a calibration wafer.

In FIG. 1A, the first short-circuit DUT 11 has a predetermined same wiring delay amount between the comparator pin 2 as a reference and the driver pins 1 to 3 as a calibration target. Represents one of a predetermined number of short-circuit DUTs connected by short-circuit with wiring.

In FIG.1 (b), the 2nd short circuit DUT 22 has wiring which has predetermined equal wiring delay amount between the driver pin 8 which becomes a reference | standard, and the comparator pins 7-9 which are a target of calibration. 1 represents a predetermined number of short-circuit DUTs connected by short-circuit.

The function configuration and signal processing procedure for skew adjustment between pins is a technique known from various documents and the like, and is not a direct description of the present invention, and thus detailed description thereof is omitted here.

Although the short-circuit DUT disclosed in Cited Reference 1 is used as a calibration wafer, and by the simulation test (simulation) method in a state close to the actual inspection environment, the error of the accuracy of the TDR method can be greatly improved. There is this.

(1) The supply of the calibration signal to the comparator pin and the driver pin as a reference for the calibration of the short-circuit DUT uses a comparator and a driver of an inspection apparatus including a transmission line and a probe.

These comparators and drivers are often replaced by defectives due to their frequent use in the actual inspection process. When the standard comparator or driver is replaced, the calibration before replacement becomes invalid, resulting in a high failure rate of the inspection apparatus. Therefore, in order to return normally, it is necessary to perform calibration on the basis of these again after the replacement, and maintenance and maintenance are complicated.

(2) Since the short-circuit DUT disclosed in Cited Reference 1 uses the short-circuit DUT itself as a reference pin, the calibration process sequentially switches the number of short-circuit DUTs equal to the number of pins of the DUT to the inspection apparatus. It is necessary to make contact (contact), and in the case of a large number of pins, a calibration time is further required in proportion to the number of pins, and the ratio of the preparation process occupied in the inspection time increases, which causes a decrease in inspection efficiency.

(3) The method of using the short-circuit DUT pin as a reference pin is adjusted based on the comparator of one pin, and the driver of the pin that became the reference is adjusted after adjusting the comparator of the other pin. Since the adjustment is made using a comparator, the accuracy of calibration is ± 1 LSB (Least Significant Bit: minimum resolution of the clock for setting the drive waveform or minimum resolution of the compensator's judgment strobe for determining the drive waveform) You can only make adjustments that exceed.

An object of the present invention is to realize a semiconductor test apparatus using a calibration wafer having a short circuit, low failure rate, minimum calibration time, and high accuracy.

EMBODIMENT OF THE INVENTION Hereinafter, this invention is demonstrated in detail by drawing. 2 is a side view of an essential part showing an embodiment of a semiconductor test apparatus to which the present invention is applied. 3A is a plan view of a calibration wafer, and FIG. 3B is an enlarged plan view of a calibration chip group constituting the calibration wafer.

In FIG. 2, electronic components for calibration and DUT inspection are mounted on the test head 100. The wafer main board 200 is connected to the test head 100 by the connector means CN1.

The probe card 300 is connected to the wafer main board 200 by the connector means CN2. A plurality of probes 301 are installed in a probe card and contact the pins of a DUT (not shown) formed on the wafer during inspection.

The calibration wafer 400 is used as a wafer for simulating a DUT at the time of calibration. A calibration chip (described later in FIG. 3) generated by simulating a DUT on the calibration wafer 400 is disposed opposite the probe 301.

The reference pin means KP is provided on the upper surface of each of the calibration chips generated in the calibration wafer 400 in a direction opposite to the probe card 300. The contact pad 302 is provided on the probe card 300 side opposite to the reference pin means KP and is electrically connected in contact with the reference pin means KP at the time of calibration.

The reference pin means KP and the contact pads 302 disposed opposite to each other are shown in Fig. 2 in one representative form. However, in the actual apparatus, the number of calibration chips (the number of pins of the device under test) is the same. A pair of numbers is formed.

The comparators C1 and C2 and the drivers D1 and D2 are mounted on the test head 100 and connected to the probe 301 of the probe card 300 via the wafer main board 200. The reference comparator C0 and the reference driver D0 are mounted in the test head 100.

The reference comparator C0 and the reference driver D0 are switched to one of the reference comparator C0 and the reference driver D0 by the selection means 500 provided in the wafer main board 200 to face the reference pin means KP of the calibration chip. It is selectively connected to one of the installed reference pads 302.

3A is a plan view of the calibration wafer 400 that is disposed opposite to the probe card 300 and whose relative positional relationship is displayed and controlled in the X-axis and Y-axis. The calibration chip 401 is generated on the calibration wafer 400 to generate a number equal to the number of pins of the DUT.

For simplicity of explanation, assuming that the number of pins of the DUT is 8, the calibration chip 401 is constituted by eight calibration chip groups CT1 to CT8. The arrangement of the rows and columns of these calibration chip groups can be freely designed.

3B is an enlarged plan view of eight calibration chips CT1 to CT8. Each of the calibration chips CT1 to CT8 has pads of the same arrangement as the pin arrangement of the DUT, and during calibration, the probe 301 contacts the pads of the calibration chips CT1 to CT8.

The reference pin means KP1 to KP8 are provided at the center of the wafer surface of the eight calibration chips CT1 to CT8 and face the eight contact pads 302 formed on the probe card 300 side, and are in contact with each other at the time of calibration and electrically. Connected.

The short-circuit wirings SW1 to SW8 are formed by the reference pin means KP1 to KP8 of each of the calibration chips CT1 to CT8 and the first to eighth pads P11, P22, P33, P44, ... of the respective calibration chips CT1 to CT8. Connect between P88. These short-circuit wirings are substantially equidistant and have the same wiring delay amount.

The comparators C1, C2 and drivers D1, D2 shown in FIG. 2 are connected to the probe 301, and are electrically connected to the pads of the calibration chips CT1 to CT8 at the time of calibration.

In such a connection state, the reference driver D0 or the reference comparator C0 is provided with a plurality of (eight in this embodiment) in which the reference driver D0 or the reference comparator C0 faces the reference pin means KP1 to KP8 of the calibration chips CT1 to CT8. Calibration is performed while switching to the contact pad 301.

The selecting means 500 is realized by a relay circuit connected hierarchically, and a method is adopted in which a branch circuit is not formed in the middle of a circuit of a connection origin and a connection destination for reflection prevention.

As described above, in the calibration according to the present invention, the pads of the calibration chip group cannot be used as reference pins, and the calibration can be performed by switching the dedicated reference pin means in contact with the calibration wafer 400 and the probe 300.

4 is a plan view of a calibration chip illustrating another embodiment of the present invention. The feature of this embodiment lies in that the calibration chip itself is provided with a reference pin means provided in the calibration chip and a relay means for switching and connecting a plurality of pads.

In addition, the relay means for connecting the reference pin means and the odd-numbered pads is opened and closed by a signal transmitted to an adjacent even-numbered pad, and the relay means for connecting the reference pin means and the even-numbered pads. Is to open and close the signal by a signal transmitted to adjacent odd-numbered pads.

Therefore, in this embodiment, the calibration chip generated on the calibration wafer is formed by a pair of calibration chip CTod for odd pins and calibration chip CTev for even pins.

In the calibration chip CTod, the relay means RLod connects the switching connection between the reference pin means KPod and odd-numbered pads Po1, Po3, Po5, and Po7 through the probe 301 to the even-numbered pads Po2, Po4, Po6, and Po8. The opening and closing operation is performed by a signal given from the driver on the test head side.

Similarly, in the calibration chip CTev, the relay means RLev connects the switching connection to the reference pin means KPev and even-numbered pads Po2, Po4, Po6 and Po8 to the odd-numbered pads Pe1, Pe3, Pe5 and Pe7. The opening and closing operation is performed by a signal given from the driver on the test head side through the.

Also in this embodiment, the pad of a pair of calibration chips cannot be used as a reference pin, the dedicated reference pin means is switched while the calibration wafer 400 and the probe 301 are in contact with each other, and the relay means is operated to operate the reference pin means. It can be calibrated while switching the connection to each pad.

Therefore, the contact between the calibration wafer 400 and the probe 301 can be completed in one step, and the complicated operation of sequentially contacting the short-circuit DUT to the probe 301 like the conventional method is not required.

As apparent from the above description, the present invention has the following effects.

(1) Since the reference pin means dedicated for calibration is used for the reference comparator or driver, the frequency of use is significantly lower than that of the comparator or driver used in the actual test, and the failure rate of the device is extremely low.

(2) Even when the comparator or driver is defective and replaced, the reference pin is not changed. Therefore, the calibration for normal return should be executed only for the replaced comparator or driver. And maintenance becomes very simple.

(3) Since a relay is provided on the calibration chip to short-circuit between the reference pin means and the pad, the process of connecting the probe to the calibration chip can be reduced. In particular, the calibration time can be significantly shortened when the number of pins is large. The efficiency is very improved.

(4) In the case of the reference pin means method of the present invention, the calibration is possible to calibrate within ± 1 LSB with respect to the reference pin means when the calibration excludes an uncertain element such as jitter. In comparison, the accuracy of calibration can be improved.

Claims (7)

A semiconductor test apparatus for performing pin-to-pin skew adjustment by bringing a probe of a probe card into contact with a pad of a calibration wafer having a pad in the same arrangement as a pin array of a device under test. A contact pad installed on the probe card; Reference pin means provided on a surface of the calibration wafer opposite the contact pad and electrically contacting the contact pad A semiconductor test apparatus comprising: The method of claim 1, And the calibration wafer is formed of a group of calibration chips equal to the number of pins of the device under test, each of which is shorted at approximately equidistant intervals between the reference pin means and each pad. The method of claim 1, The said calibration wafer is equipped with the relay means which short-circuits between the said reference pin means and each said pad substantially equidistantly by itself, The semiconductor test apparatus characterized by the above-mentioned. The method of claim 3, The relay means for connecting the reference pin means and the odd pad is operated by a signal transmitted to an even pad, or the relay means for connecting the reference pin means and an even pad is operated by a signal transmitted to an odd pad. A semiconductor test apparatus characterized by the above-mentioned. The method according to claim 3 or 4, The calibration wafer is formed by a pair of first calibration chips to which the reference pin means and odd pads are connected by the relay means, and a pair of second calibration chips to which the reference pin means and even pads are connected by the relay means. The semiconductor test apparatus characterized by the above-mentioned. The method according to any one of claims 1 to 4, And at least one of a reference comparator or a reference driver connected to a contact pad provided in the probe card. The method of claim 6, And a selection means for selectively connecting the reference comparator or the reference driver to the reference pin means provided on each calibration chip through the contact pads.

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