KR20060038816A - Voltage level detector and internal voltage generator using the same - Google Patents

Abstract

The present invention discloses a voltage level detection device using a charge pumping method and an internal voltage generation device using the detection device.

The voltage level detecting device of the present invention includes: a voltage divider for dividing and outputting a pumping voltage at a predetermined ratio according to fuse trimming and resistance size; A distribution controller for adjusting a voltage distribution ratio of the voltage divider according to a burn-in test start signal to adjust a magnitude of the output voltage; And a differential amplifier outputting a pumping enable signal for determining whether the pumping voltage is pumped by comparing the output voltage of the voltage divider with a preset reference voltage and amplifying the voltage difference. Even after the fuse is cut for trimming, the burn-in level does not affect the burn-in level, thereby stabilizing the internal voltage, thereby improving yield and reducing test time.

Voltage level, detection, internal voltage, charge, pumping

Description

Voltage level detector and internal voltage generator using the same

1 is a circuit diagram showing a configuration of a conventional voltage level detection device using a charge pumping method.

2 is a graph showing the level of the internal voltage generated in each operation mode according to the voltage level detection device of FIG.

3 is a block diagram showing a configuration of an internal voltage generator according to the present invention;

FIG. 4 is a circuit diagram illustrating in detail the configuration of the voltage level detector according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing the configuration of the oscillator in FIG. 3 in more detail. FIG.

FIG. 6 is a circuit diagram illustrating in detail the configuration of the pumping controller in FIG. 3. FIG.

7 is a circuit diagram showing in more detail the configuration of the pumping unit in FIG.

Figure 8 is a waveform diagram showing each signal generated in the internal voltage generator of the present invention.

9 is a graph showing the level of the internal voltage generated in each operation mode according to the voltage level detection device of the present invention.

10 is a circuit diagram showing in more detail the configuration of the voltage level detecting unit according to the second embodiment of the present invention at 3;

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage level detection device and an internal voltage generation device using the same, and more particularly, to trim a fuse at a normal level in a voltage generation device using a charge pumping method. The present invention relates to a voltage level detection device which does not affect the burn-in level during a burn in test even after the fuse is cut, and an internal voltage generator using the detection device.

In addition to the external voltages (V _DD , V _REF , V _SS ) applied to the DRAM, the DRAM has an internal voltage generator that creates a voltage level for internal operation. In the internal voltage generator, two methods of converting the external voltage V _DD down as it is and a charge pumping are used. Here, in the former case, a reference voltage is made and then a current mirror is used to make an internal voltage of a desired level. In the latter case, a hole pump is applied to an external voltage (V _DD ) using a charge pump. It is a method of making an internal voltage by supplying holes (V _PP ) or by supplying electrons to an external voltage (V _SS ) (V _BB , V _BBW ).

1 is a circuit diagram showing the configuration of a conventional voltage level detecting device using a charge pumping method.

The conventional voltage level detecting device includes resistors R1 to R6, fuses FS1 to FS4, and a differential amplifier 1 to detect whether the pumping voltage V _PP is a target level. At this time, the resistors R1 to R6 are connected in series between the pumping voltage V _PP and the ground voltage to distribute the pumping voltage V _PP . The fuses FS1 to FS4 are connected in parallel to the resistors R2 to R5, respectively, and if the target level does not come out due to the device process, it is selectively cut at the wafer level to trim the level to adjust the voltage distribution. The differential amplifier 1 includes PMOS transistors P1, P2, NMOS transistors N1, N2, N3, and inverter IV1, and the PMOS transistors P1, P2 constitute a current mirror. The differential amplifier 1 compares the signal distributed by the resistors R1 to R6 and the fuses FS1 to FS4 with the reference voltage V _REF , amplifies the comparison value, and inverts the amplified signal using the inverter IV1. By outputting the pumping enable signal Vppe indicating the start of pumping.

In such a voltage level detecting device, before the fuse trimming, the resistors R2 to R5 are shorted by the fuses FS1 to FS4 so that the pumping voltage VPP is divided and output by the resistor R1 and the resistor R6. That is, the magnitude of the voltage applied to the gate of the NMOS transistor N1 before the trimming of the fuse becomes V _PP * {R 6 / (R 1 + R 6)}. However, if the pumping voltage level is lowered or raised for processing reasons, the fuses FS1 to FS4 are selectively cut for the trimming of the fuse to adjust the pumping voltage level to the target level of the normal level. For example, when fuse FS1 is cut by fuse trimming, the voltage applied to the gate of NMOS transistor N1 is lowered to V _PP * {R6 / (R1 + R2 + R6)}. _PP * {(R5 + R6) / (R1 + R5 + R6)} increases, so this fuse trims the voltage level.

However, in the conventional voltage level detecting apparatus as shown in FIG. 1, when the fuse trimming is performed to match the normal level target of the pumping voltage V _PP , the target is changed during the burn-in test to reduce the reliability of the test. Generate.

That is, as in the second, normal mode (Normal mode) when the operating flat level of the internal voltage (Vint), so the target level of the pumping voltage (V _PP _after) through a fuse trimming in the operating area level (V _PP _target), but in burn-in mode, unlike the normal mode, the internal voltage (Vint) continuously increases, so in the external voltage range where the voltage level (Vpp_before, Vpp_after) before and after fuse trimming is high. It will change a lot and make the test less reliable.

Accordingly, an object of the present invention to solve the above-described problem is to improve the circuit structure of the voltage level detection device to stabilize the internal voltage even during burn-in test so that a reliable test can be performed even after fuse trimming for the normal level. .

The voltage level detection device of the present invention for achieving the above object is a voltage divider for outputting by dividing the pumping voltage in a predetermined ratio according to the size of the fuse trimming and the resistance; A distribution controller for adjusting a voltage distribution ratio of the voltage divider according to a burn-in test start signal to adjust a magnitude of the output voltage; And a differential amplifier outputting a pumping enable signal for determining whether the pumping voltage is pumped by comparing the output voltage of the voltage divider with a preset reference voltage and amplifying the voltage difference.

The internal voltage generator of the present invention includes: a voltage level detection unit for detecting a level of a pumping voltage at different voltage distribution ratios according to an operation mode by using a burn-in test start signal and outputting a pumping enable signal according to the detection result; An oscillator for generating and outputting an oscillation signal of a predetermined period when the pumping enable signal is activated; A pumping controller configured to signal-process the oscillation signal to generate and output a pumping control signal for controlling pumping of the pumping voltage; And a pumping unit configured to generate and output the pumping voltage by amplifying an external voltage while repeating charge and discharge of electric charges according to the pumping control signal.

Hereinafter, with reference to the accompanying drawings will be described in detail preferred embodiments of the present invention.

3 is a configuration diagram showing a configuration of an internal voltage generator according to the present invention.

The internal voltage generator of the present invention includes a voltage level detector 10, an oscillator 20, a pumping controller 30, and a pumping unit 40.

The voltage level detecting unit 10 distributes the pumping voltage V _PP , which is the output voltage of the pumping unit 40, in different ratios according to an operation mode (normal mode or burn-in mode) by using the burn-in test start signal tm_bi. By comparing the divided voltage with the reference voltage and amplifying the voltage difference, the pumping enable signal Vppe is output to detect whether the pumping voltage V _PP has reached a predetermined target level. That is, the voltage level detector 10 distributes the pumping voltage V _PP according to the fuse trimming in the normal mode in which the burn-in test start signal tm_bi is deactivated, and in the burn-in mode in which the burn-in test start signal tm_bi is activated. The pumping voltage (V _PP ) is distributed at a predetermined ratio regardless of fuse trimming. The voltage level detector 10 compares the divided voltage with a reference voltage, amplifies the voltage difference, and generates and outputs a pumping enable signal Vppe.

The oscillator 20 receives the pumping enable signal Vppe from the voltage level detector 10, and generates and outputs an oscillation signal osc of a predetermined period when the pumping enable signal Vppe is activated.

The pumping control unit 30 receives the oscillation signal osc from the oscillator 20, and processes the oscillation signal osc to generate pumping control signals p1, p2, g1, and g2 for controlling pumping. To print. That is, the pumping controller 30 generates the pumping control signals p1, p2, g1, and g2 by changing the pulse period and the phase of the oscillation signal osc.

The pumping unit 40 amplifies the external voltage V _DD while repeating the charge and discharge of the charge according to the pumping control signals p1, p2, g1, and g2 to pump the voltage _VPP . Create and print The pumping voltage V _PP output from the pumping unit 40 is fed back to the voltage level detecting unit 10.

4 is a circuit diagram illustrating in detail the configuration of the voltage level detector 10 according to the first embodiment of the present invention. Hereinafter, the same reference numerals as those of FIG. 1 are given to elements that perform the same functions as those of FIG. 1 in FIG. 4.

The voltage level detector 10 includes a voltage divider 12, a divide controller 14, and a differential amplifier 16.

The voltage divider 12 divides and outputs the pumping voltage V _PP at a predetermined ratio according to the fuse trimming and the size of the resistor. The voltage divider 12 includes fuses FS1 ˜ 1 that are connected in parallel to resistors R 1 to R 6 and resistors R 2 to R 5 (trimming resistance) which are connected in series between the pumping voltage V _PP and the ground voltage V _SS . With FS4.

The distribution controller 14 adjusts the voltage distribution ratio of the voltage divider 12 according to the burn-in test start signal tm_bi to adjust the magnitude of the pumping enable signal Vppe according to the operation mode. The distribution controller 14 is connected between the node A and the node C, and is connected between the NMOS transistor N4 and the node C and the node B, which receives the gated test start signal tm_bi, and the gated test start signal tm_bi. NMOS transistor N5 is applied. That is, when the burn-in test is performed and the burn-in test start signal tm_bi is enabled high, the distribution adjusting unit 14 performs two groups of resistors R2 and R3 (first trimming target resistance group) and R4 and R5 ( The NMOS transistors N4 and N5 connected in parallel to the second trimming target resistance group) are turned on to directly connect the nodes A and B and between the nodes B and C, respectively. As a result, the fuses cut by the fuse trimming may not affect the output voltage of the voltage divider 12. On the contrary, when the burn-in test start signal tm_bi in the normal mode is disabled, the distribution controller 14 turns off the NMOS transistors N4 and N5 to determine the output voltage of the voltage divider 12 according to the fuse trimming. To make it possible.

The differential amplifier 16 outputs the pumping enable signal Vppe by comparing the output voltage of the voltage divider 12 with the reference voltage V _ref and amplifying the voltage difference. The differential amplifier 16 includes PMOS transistors P1, P2, NMOS transistors N1 to N3, and inverter IV1. The PMOS transistors P1 and P2 form a current mirror, and the NMOS transistors N1 and N2 are connected between the current mirror and the NMOS transistor N3 and receive the output voltage and the reference voltage V _{ref of the} voltage divider 12 as gates, respectively. . The NMOS transistor N3 is connected between the NMOS transistors N1 and N2 and the ground voltage and selectively activates the differential amplifier 16 by receiving a pumping active signal V _PP _act to the gate. The inverter IV1 inverts the signals amplified by the NMOS transistors N1 and N2 and outputs a pumping enable signal Vppe.

FIG. 5 is a circuit diagram illustrating in detail the configuration of the oscillator 20 in FIG. 3.

The oscillator 20 generates and outputs a pulse signal osc having a constant pulse width while the pumping enable signal VPp is activated as shown in FIG. 8. This oscillator 20 includes a NAND gate ND1 and inverters IV2 to IV7. The NAND gate ND1 performs a NAND operation on the oscillation signal osc fed back by being delayed inverted through the pumping enable signal Vppe and the inverters IV5 to IV7. Inverters IV2 to IV4 are connected in series between the output terminal of NAND gate ND1 and the output terminal of oscillator 20, and inverters IV5 to IV7 are connected in series between the output terminal of oscillator 20 and one input terminal of NAND gate ND1.

FIG. 6 is a circuit diagram illustrating in detail the configuration of the pumping controller 30 in FIG. 3.

The pumping controller 30 generates the pumping control signals p1, p2, g1, and g2 for the pumping control by changing the pulse period and the phase of the received oscillation signal osc. The pumping control unit 30 includes inverters IV8 to IV15 and NAND gates ND2 and ND3. The inverters IV8 and IV9 are connected in series and output the oscillation signal osc to one input terminal of the NAND gates ND2 and ND3 by non-inverting delay. The inverters IV10 and IV11 are connected in series and output the pumping control signal p1 by non-inverting the oscillation signal osc. The inverter IV13 inverts the pumping control signal p1 and outputs the pumping control signal p2. The NAND gates ND2 and ND3 perform NAND operations on the oscillation signals osc and the oscillation signals delayed by the inverters IV8 and IV9. Inverters IV12 and IV14 are connected in series with the output terminal of the NAND gate ND2 to output the pumping control signal g1. The inverter IV15 is connected to the output terminal of the NAND gate ND3 and outputs a pumping control signal g2. The relationship between the oscillation signal osc and the pumping control signals p1, p2, g1, g2 is shown in FIG. 8.

FIG. 7 is a circuit diagram illustrating in detail the configuration of the pumping unit 40 in FIG. 3.

The pumping unit 40 has a pair of pumping control signals p1 and g1 and pumping control signals p2 and g2, respectively, and repeats charge and discharge of an external power supply V _DD . It is configured in the form of an amplifier to amplify and generate a pumping voltage (V _PP ). The pumping unit 40 has NMOS capacitors N6 to N9, a node D and an external voltage (V) having a drain and a source connected in common with the pumping control signals p1, p2, g1, and g2, respectively, and whose gates are connected to the nodes D to G. _DD ), which is connected between NMOS transistors N10 and N11, which are connected to node D and external voltage (V _DD ), and node E and external voltage (V _DD ), respectively. NMOS transistors N12 and N13 connected to V _DD ), between the node F or G and the external voltage (V _DD ), and NMOS transistors N14 and N15 connected to the node D and node E, respectively, and the external voltage (V _DD ). And NMOS transistor N16 connected between the pumping voltage (V _PP ) terminal and the gate connected to the external voltage (V _DD ), and PMOS transistor P3 connected between the pumping voltage (V _PP ) terminal and nodes F and G in a latch form. P4 is provided.

The operation of the internal voltage generator according to the present invention having the above-described configuration will be briefly described.

In the normal mode, when the pumping voltage V _PP _before is smaller than the target level VPP_target as shown in FIG. 9, fuse trimming is performed to adjust the voltage level V _PP _after to the target level.

For this purpose, by cutting the fuse FS3, the output voltage of the voltage divider 12 is raised to V _PP * {(R4 + R6) / (R1 + R4 + R6)}.

The output voltage of the voltage divider 12 is applied to the gate of the NMOS transistor N1, and the differential amplifier 16 outputs the voltage divider 12 while the pumping active signal V _PP _act is activated high. The voltage and the reference voltage V _REFC are compared and the voltage difference is amplified to output the pumping enable signal Vppe to the oscillator 20. At this time, when the reference voltage V _REFC is greater than the output voltage of the voltage divider 12, the pumping enable signal Vppe is activated and output as high.

When the pumping enable signal VPp is activated high and applied to one input terminal of the NMOS transistor ND1 of the oscillator 20, the NMOS transistor ND1 is applied to a signal applied to another input terminal, that is, a delay inverted oscillation signal osc. Accordingly, a pulse signal having a predetermined pulse width is output, and the pulse signal is inversely delayed again and output as an oscillation signal osc.

The pumping controller 30 processes the oscillation signal osc applied from the oscillator 20 to generate four pumping control signals p1, p2, g1, and g2 as shown in FIG. 8 to generate a pumping unit ( 40).

The pumping unit 40 pumps the external voltage V _DD according to the pumping control signals p1, p2, g1, and g2 and outputs the pumped voltage V _PP . Referring to the operation of the pumping unit 40, first, when the high level pumping control signal g1 of the V _DD level is applied to the NMOS capacitor N8, the NMOS transistor N14 is turned on so that the node F is turned to the external voltage V _DD level. Precharged. At this time, the PMOS transistor P3 is kept off by the pumping control signal p2. Next, when the pumping control signal p1 is activated high while the voltage of the node F is precharged to the external voltage V _DD level, the voltage of the node F rises to " 2V _DD ".

At this time, when the low level pumping control signal p2 is applied to the NMOS capacitor N7, the PMOS transistor P3 is turned on to increase the potential of the pumping voltage terminal due to the charge sharing between the pumping voltage terminal and the node F.

In the same manner, when the pumping control signal g2 is applied to the NMOS capacitor N9 at a high level, the NMOS transistor N15 is turned on so that the node G is precharged to the external voltage V _DD level. Next, when the pumping control signal p2 is applied at the high level, the voltage of the node G is raised to "2V _DD " by the NMOS capacitor N7, and at this time, the pumping clock signal p1 is applied at the low level so that the PMOS transistor P4 is applied. When is turned on, the voltage of the pumping voltage terminal is increased by the charge distribution between the pumping voltage terminal and the node G. The pumping unit 40 repeats this operation and continues the pumping operation until the pumping voltage V _PP level reaches the target level.

In the burn-in test mode, the burn-in test start signal tm_bi indicating the start of the burn-in test is activated. In the present invention, the pumping voltage level detection is differently performed according to the operation mode by using the burn-in test start signal tm_bi. That is, the internal voltage generator according to the present invention distinguishes between the normal mode and the burn-in test mode by using the burn-in test start signal tm_bi in the state of fuse trimming, and detects the voltage level according to each operation mode. Do it differently.

When the burn-in test start signal (tm_bi) is activated, the NMOS transistors N4 and N5 are turned on so that a direct connection between node A and node B and between node B and node C causes the magnitude of the pumping voltage (V _PP ) to be applied to the resistors R1 and R6. Is distributed by In other words, the trimming by cutting the fuse does not affect the distribution of the pumping voltage V _PP . Thus, the burn-in mode is because it does not fuse trimming effect on the pumping voltage level detected voltage (V _PP _before, V _PP _after) before and after the performing fuse trimming as shown in Figure 9 are the same is not the target level change.

Since the operation of the oscillation 20, the pumping controller 30, and the pumping unit 40 using the detected voltage is the same as in the above-described normal mode, a description thereof will be omitted.

10 is a circuit diagram showing the configuration of the voltage level detector 10 according to the second embodiment of the present invention.

The operation of the voltage level detection unit 10 of FIG. 10 is the same as that of the voltage level detection unit of FIG. 4, and instead of the NMOS transistors N4 and N5 of FIG. 4, the transfer transistor TT1 is used to more reliably transfer the potentials of the nodes A and C. The only difference is that TT2 was used.

That is, the distribution controller 18 of FIG. 10 turns on / off according to the inverters IV16 and IV17 outputting the inverted burn-in test start signal tm_bi and the output signals of the burn-in test start signals tm_bi and the inverters IV16 and IV17. Transfer transistors TT1 and TT2 that are turned off.

In the voltage level detecting unit 10 of FIG. 10, the components 12 and 16 other than the distribution adjusting unit 18 are denoted by the same reference numerals because their configurations and functions are the same as those of FIG. 4, and the description of the operation is omitted. .

As described above, the voltage level detection device and the internal voltage generator of the present invention do not affect the burn-in level during burn in test even after the fuse is cut for fuse trimming at a normal level. Therefore, by stabilizing the internal voltage, it helps to improve the yield and shorten the test time.

Claims (16)

A voltage divider for dividing the pumping voltage at a predetermined ratio according to the size of the fuse trimming and the resistance; A distribution controller for adjusting a voltage distribution ratio of the voltage divider according to a burn-in test start signal to adjust a magnitude of the output voltage; And And a differential amplifier for outputting a pumping enable signal for determining whether the pumping voltage is pumped by comparing the output voltage of the voltage divider with a preset reference voltage and amplifying the voltage difference. The method of claim 1, wherein the voltage divider A plurality of resistors connected in series between the pumping voltage and the ground voltage; And And a plurality of fuses each parallel with the trimming target resistors of the plurality of resistors and selectively cut by the fuse trimming. The method of claim 2, wherein the distribution control unit A first switching element connected in parallel with a first trimming target resistor group on the pumping voltage side to directly connect both ends of the first trimming target resistance group when the burn-in test start signal is activated; And A second switching element connected in parallel with a second trimming target resistance group on the pumping voltage side to directly electrically connect both ends of the second trimming target resistance group when the burn-in test start signal is activated. Voltage level sensing device, characterized in that. The method of claim 3, wherein the first switching device And a NMOS transistor turned on and off according to the burn-in test start signal. The method of claim 3, wherein the first switching device And a transfer transistor turned on and off according to the burn-in test start signal and its inverted signal. The method of claim 4 or 5, wherein the second switching device And a NMOS transistor turned on and off according to the burn-in test start signal. The method of claim 4 or 5, wherein the second switching device And a transfer transistor turned on and off according to the burn-in test start signal and its inverted signal. A voltage level detector for detecting a level of pumping voltage at different voltage distribution ratios according to an operation mode by using a burn-in test start signal, and outputting a pumping enable signal according to the detection result; An oscillator for generating and outputting an oscillation signal of a predetermined period when the pumping enable signal is activated; A pumping controller configured to signal-process the oscillation signal to generate and output a pumping control signal for controlling pumping of the pumping voltage; And And a pumping unit configured to generate and output the pumping voltage by amplifying an external voltage while repeating charge and discharge of electric charges according to the pumping control signal. The method of claim 8, wherein the voltage level detector When the burn-in test start signal is deactivated, the level of the pumping voltage is sensed according to the voltage distribution ratio according to the previously performed fuse trimming. And when the burn-in test start signal is activated, detecting the level of the pumping voltage according to a preset voltage distribution ratio regardless of the fuse trimming. The method of claim 9, wherein the voltage level detector A voltage divider for dividing the pumping voltage at a predetermined ratio according to the fuse trimming and the magnitude of resistors connected in series between the pumping voltage and the ground voltage; A distribution controller for controlling a voltage distribution ratio of the voltage divider according to the burn-in test start signal to adjust a magnitude of the output voltage; And And a differential amplifier outputting a pumping enable signal for determining whether the pumping voltage is pumped by comparing the output voltage of the voltage divider with a preset reference voltage and amplifying the voltage difference. The method of claim 10, wherein the voltage divider A plurality of resistors connected in series between the pumping voltage and the ground voltage; And And a plurality of fuses which are respectively parallel with trimming target resistors of the plurality of resistors and selectively cut by the fuse trimming. The method of claim 11, wherein the distribution control unit A first switching element connected in parallel with a first trimming target resistor group on the pumping voltage side to directly connect both ends of the first trimming target resistance group when the burn-in test start signal is activated; And A second switching element connected in parallel with a second trimming target resistance group on the pumping voltage side to directly electrically connect both ends of the second trimming target resistance group when the burn-in test start signal is activated. Internal voltage generator, characterized in that. The method of claim 12, wherein the first switching device And an NMOS transistor turned on and off according to the burn-in test start signal. The method of claim 12, wherein the first switching device And a transfer transistor turned on and off according to the burn-in test start signal and its inverted signal. The method according to claim 13 or 14, wherein the second switching device And an NMOS transistor turned on and off according to the burn-in test start signal. The method according to claim 13 or 14, wherein the second switching device And a transfer transistor turned on and off according to the burn-in test start signal and its inverted signal.

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