KR20060038746A - Method for forming contactplug of semicondutor device - Google Patents

Method for forming contactplug of semicondutor device Download PDF

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KR20060038746A
KR20060038746A KR1020040087876A KR20040087876A KR20060038746A KR 20060038746 A KR20060038746 A KR 20060038746A KR 1020040087876 A KR1020040087876 A KR 1020040087876A KR 20040087876 A KR20040087876 A KR 20040087876A KR 20060038746 A KR20060038746 A KR 20060038746A
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forming
hard mask
contact
etching
interlayer insulating
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박수영
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

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  • Computer Hardware Design (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 SAC(Self Align Contact)페일 및 콘택 낫 오픈(Contact Not Open)을 방지할 수 있는 반도체 소자의 콘택플러그 형성 방법에 관한 것으로, 기판 상에 도전패턴을 형성하는 단계; 상기 도전패턴 상에 층간절연막을 형성하는 단계; 상기 층간절연막 상에 희생하드마스크용 물질막을 형성하는 단계; 상기 희생하드마스크용 물질막 상에 콘택홀 형성을 위한 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 식각마스크로 상기 희생하드마스크용 물질막을 식각하여 희생하드마스크를 형성하는 단계; 상기 포토레지스트 패턴을 제거하는 단계; CO를 포함하는 가스를 이용하여 상기 하드마스크를 식각마스크로 상기 층간절연막을 식각하여 상기 기판을 노출시키는 콘택홀을 형성하는 단계를 포함한다.
The present invention relates to a method for forming a contact plug of a semiconductor device capable of preventing a self alignment contact (SAC) fail and a contact not open, the method comprising: forming a conductive pattern on a substrate; Forming an interlayer insulating film on the conductive pattern; Forming a material film for a sacrificial hard mask on the interlayer insulating film; Forming a photoresist pattern for forming a contact hole on the sacrificial hard mask material layer; Forming a sacrificial hard mask by etching the material layer for the sacrificial hard mask using the photoresist pattern as an etching mask; Removing the photoresist pattern; Forming a contact hole exposing the substrate by etching the interlayer insulating layer using the hard mask as an etching mask using a gas containing CO.

콘택플러그, 자기정렬콘택(Selg Align Contact), 콘택 낫 오픈(Contact Not Open)Contact Plug, Selg Align Contact, Contact Not Open

Description

반도체 소자의 콘택플러그 형성 방법{METHOD FOR FORMING CONTACTPLUG OF SEMICONDUTOR DEVICE} Method for forming contact plug of semiconductor device {METHOD FOR FORMING CONTACTPLUG OF SEMICONDUTOR DEVICE}             

도 1은 종래기술에 따라 제조된 반도체 소자의 콘택플러그가 형성된 모습을 나타내는 단면도,1 is a cross-sectional view showing a state in which a contact plug of a semiconductor device manufactured according to the prior art is formed;

도 2a 내지 도 2d는 본 발명의 바람직한 실시예에 따른 반도체 소자의 콘택플러그 형성 방법을 도시한 공정 단면도.
2A to 2D are cross-sectional views illustrating a method for forming a contact plug in a semiconductor device according to a preferred embodiment of the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

20 : 기판 21 : 절연막20: substrate 21: insulating film

22 : 도전막 23 : 하드마스크용 질화막22 conductive film 23 nitride film for hard mask

24 : 층간절연막 25 : 희생하드마스크용 물질막24: interlayer insulating film 25: material film for sacrificial hard mask

26 : 포토레지스트 패턴 27 : 콘택홀26 photoresist pattern 27 contact hole

28 : 콘택플러그 B2 : 도전패턴
28: contact plug B2: conductive pattern

본 발명은 반도체 소자의 콘택플러그 형성 방법에 관한 것으로, 특히 SAC(Self Align Contact)페일 및 콘택 낫 오픈(Contact Not Open)을 방지할 수 있는 반도체 소자의 콘택플러그 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact plug of a semiconductor device, and more particularly, to a method for forming a contact plug of a semiconductor device capable of preventing SAC (Self Align Contact) failing and contact not opening.

일반적으로, 반도체 소자는 그 내부에 다수의 단위 소자들을 포함하여 이루어진다. 반도체 소자가 고집적화되면서 일정한 셀(Cell) 면적 상에 고밀도로 소자들을 형성하여야 하며, 이로 인하여 단위 소자, 예를 들면 트랜지스터와 캐패시터들의 크기는 점차 줄어들고 있다. 특히 DRAM(Dynamic Random Access Memory)과 같은 반도체 메모리 소자에서 디자인 룰(Design rule)이 감소하면서 셀의 내부에 형성되는 반도체 소자들의 크기가 점차 작아지고 있다. 실제로 최근 반도체 DRAM 장치의 최소 선폭은 0.1㎛ 이하로 형성되며, 80nm 이하까지도 요구되고 있다. 따라서, 셀을 이루는 반도체 소자들의 제조 공정에 많은 어려움들이 발생하고 있다.In general, a semiconductor device includes a plurality of unit devices therein. As semiconductor devices become highly integrated, devices must be formed at a high density on a predetermined cell area, thereby decreasing the size of unit devices such as transistors and capacitors. In particular, as the design rules decrease in semiconductor memory devices such as DRAM (Dynamic Random Access Memory), the size of semiconductor devices formed inside the cell is gradually decreasing. In fact, in recent years, the minimum line width of the semiconductor DRAM device is formed to 0.1㎛ or less, even up to 80nm is required. Therefore, many difficulties arise in the manufacturing process of the semiconductor elements forming the cell.

80nm 이하의 선폭을 갖는 반도체 소자에서 193nm의 파장을 갖는 ArF(불화아르곤) 노광을 이용하여 포토리소그라피 공정을 적용할 경우, 기존의 식각 공정 개념(정확한 패턴 형성과 수직한 식각 프로파일 등)에 식각 도중 발생되는 포토레지스트의 변형(Deformation)이 발생하며 이로 인해 콘택 낫 오픈(Contact Not Open)을 유발하는 문제점이 발생하였다.In the case of applying a photolithography process using ArF (argon fluoride) exposure having a wavelength of 193 nm in a semiconductor device having a line width of 80 nm or less, the etching process is performed in accordance with the conventional etching process concept (exact pattern formation and vertical etching profile, etc.). Deformation of the generated photoresist occurs and this causes a problem of causing contact not open.

상기한 문제점와 고종횡비를 갖는 구조물 사이를 식각해야 하는 과제를 해결하기 위해 희생하드마스크를 이용한 자기정렬콘택(Self Align Contact; 이하 SAC 이라함)식각이 도입되었다. In order to solve the above problem and the problem of etching between structures having a high aspect ratio, self-aligned contact (SAC) etching using a sacrificial hard mask was introduced.                         

도 1은 종래기술에 따라 제조된 반도체 소자의 콘택플러그가 형성된 모습을 나타내는 단면도이다.1 is a cross-sectional view showing a state in which a contact plug of a semiconductor device manufactured according to the prior art is formed.

도 1을 참조하면, 기판(10) 상에 하드마스크용 질화막(13)/도전막(12)/절연막(11)의 적층구조로 된 도전패턴(G1)을 형성되어 있고, 도전패턴(G1)의 측벽에는 스페이서(14)가 형성되어 있다. 도전패턴(G1)의 사이에는 소스/드레인 영역(도면에 도시되지 않음)과 전기적으로 연결되는 콘택플러그(15)가 형성되어 있다.Referring to FIG. 1, a conductive pattern G1 having a laminated structure of a hard mask nitride film 13, a conductive film 12, and an insulating film 11 is formed on a substrate 10, and the conductive pattern G1 is formed. The spacer 14 is formed in the side wall of the. A contact plug 15 is formed between the conductive patterns G1 to be electrically connected to a source / drain region (not shown).

상기와 같이 종래기술은 콘택플러그 형성을 위한 SAC식각가스로 주로 C4F6 (또는 C5F8가스)를 사용하는데, 이러한 가스는 하드마스크용 질화막에 대한 식각선택비가 낮아 SAC식각시 하드마스크용 질화막을 손상시켜, 도 1의 A에 도시된 바와 같이 도전막과 콘택플러그가 전기적으로 절연되지 못하고 서로 연결되어 SAC(Self Align Contact)페일을 유발하는 문제점이 있었다.
As described above, the conventional technology mainly uses C 4 F 6 (or C 5 F 8 gas) as an SAC etching gas for forming a contact plug, and this gas has a low etching selectivity for a nitride film for hard mask, and thus hard mask during SAC etching. By damaging the molten nitride film, as illustrated in FIG. 1A, the conductive film and the contact plug are not electrically insulated, but are connected to each other to cause a SAC (Self Align Contact) fail.

본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, SAC(Self Align Contact)페일 및 콘택 낫 오픈(Contact Not Open)을 방지할 수 있는 반도체 소자의 콘택플러그 형성 방법을 제공하는 데 그 목적있다.
SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object thereof is to provide a method for forming a contact plug of a semiconductor device capable of preventing a SAC (Self Align Contact) fail and a contact not open.

상기한 목적을 달성하기 위한 본 발명은 기판 상에 도전패턴을 형성하는 단 계; 상기 도전패턴 상에 층간절연막을 형성하는 단계; 상기 층간절연막 상에 희생하드마스크용 물질막을 형성하는 단계; 상기 희생하드마스크용 물질막 상에 콘택홀 형성을 위한 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 식각마스크로 상기 희생하드마스크용 물질막을 식각하여 희생하드마스크를 형성하는 단계; 상기 포토레지스트 패턴을 제거하는 단계; CO를 포함하는 가스를 이용하여 상기 하드마스크를 식각마스크로 상기 층간절연막을 식각하여 상기 기판을 노출시키는 콘택홀을 형성하는 단계를 포함하는 반도체 소자의 콘택플러그 형성 방법을 제공한다.
The present invention for achieving the above object is a step of forming a conductive pattern on the substrate; Forming an interlayer insulating film on the conductive pattern; Forming a material film for a sacrificial hard mask on the interlayer insulating film; Forming a photoresist pattern for forming a contact hole on the sacrificial hard mask material layer; Forming a sacrificial hard mask by etching the material layer for the sacrificial hard mask using the photoresist pattern as an etching mask; Removing the photoresist pattern; The method of claim 1, further comprising forming a contact hole exposing the substrate by etching the interlayer insulating layer using the hard mask as an etching mask using a gas containing CO.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 2a 내지 도 2d는 본 발명의 바람직한 실시예에 따른 반도체 소자의 콘택플러그 형성 방법을 도시한 공정 단면도이다.2A through 2D are cross-sectional views illustrating a method of forming a contact plug in a semiconductor device according to an exemplary embodiment of the present invention.

도 2a를 참조하면, 기판(20) 상에 하드마스크용 질화막(23)/도전막(22)/절연막(21)의 적층구조를 포함하는 도전패턴(G2)을 형성한다. 이어서, 도전패턴(G2) 상에 산화막을 포함하는 층간절연막(24)을 형성한 후, 도전패턴(G2) 상부가 노출되는 타겟으로 층간절연막(24)을 평탄화한다.Referring to FIG. 2A, a conductive pattern G2 including a stacked structure of the hard mask nitride film 23, the conductive film 22, and the insulating film 21 is formed on the substrate 20. Subsequently, after the interlayer insulating film 24 including the oxide film is formed on the conductive pattern G2, the interlayer insulating film 24 is planarized to a target to which the upper portion of the conductive pattern G2 is exposed.

이어서, 도 2b에 도시된 바와 같이, 콘택 낫 오픈(Contact Not Open) 방지 및 SAC식각을 위한 희생하드마스크용 물질막(25)을 500Å 내지 1500Å의 두께로 형성한다. 희생하드마스크용 물질막(25)은 질화막 또는 폴리실리콘막을 포함할 수 있다. Subsequently, as shown in FIG. 2B, a material film 25 for sacrificial hard mask for preventing contact not open and SAC etching is formed to a thickness of 500 kV to 1500 kPa. The sacrificial hard mask material film 25 may include a nitride film or a polysilicon film.

이어서, 희생하드마스크용 물질막(25) 상에 콘택홀 형성을 위한 포토레지스트 패턴(26)을 형성한다. Next, a photoresist pattern 26 for forming a contact hole is formed on the material layer 25 for the sacrificial hard mask.

이어서, 도 2c에 도시된 바와 같이, 포토레지스트 패턴(26)을 식각마스크로 희생하드마스크용 물질막(25)을 식각하여 희생하드마스크(25a)를 형성후, 포토레지스트 패턴(26)을 제거한다.Subsequently, as shown in FIG. 2C, the sacrificial hard mask material layer 25 is etched using the photoresist pattern 26 as an etch mask to form the sacrificial hard mask 25a, and then the photoresist pattern 26 is removed. do.

이어서, CO를 포함하는 가스를 이용하여 희생하드마스크를 식각마스크로 층간절연막(24)을 식각하여 절연막(20)을 노출시키는 콘택홀(27)을 형성한다. 여기서, CO를 포함하는 가스는 CO에 CxFy(x, y 는 1 ∼10)를 더 포함하는 가스일 수 있다.Subsequently, the interlayer insulating film 24 is etched using the sacrificial hard mask as an etch mask using a gas containing CO to form a contact hole 27 exposing the insulating film 20. Here, the gas containing CO may be a gas further including C x F y (x, y is 1 to 10) in CO.

CO를 포함하는 가스는 도전패턴(G2)의 하드마스크용 질화막(23)에 대한 식각선택비를 높여 종래기술에서 발생하던 하드마스크용 질화막(23)의 손상에 따른 SAC(Self Align Contact)페일을 방지할 수 있다.The gas containing CO increases the etching selectivity of the hard mask nitride film 23 of the conductive pattern G2, thereby preventing the self alignment contact (SAC) fail due to the damage of the hard mask nitride film 23 generated in the prior art. You can prevent it.

이어서, 도 2d에 도시된 바와 같이, 희생하드마스크(25a)를 제거한 후, 전면에 플러그 형성용 전도막을 증착하여 콘택홀을 통해 노출된 기판(20)에 형성된 불순물 확산영역(도면에 도시되지 않음)에 접속시킨다.Subsequently, as shown in FIG. 2D, after the sacrificial hard mask 25a is removed, an impurity diffusion region formed in the substrate 20 exposed through the contact hole by depositing a plug forming conductive film on the entire surface (not shown in the drawing). ).

이어서, 도전패턴(G2) 상부가 노출되는 타겟으로 플러그 형성용 전도막을 평탄화하여 콘택플러그(28)를 완성한다. Subsequently, the contact plug 28 is completed by planarizing the plug forming conductive film with a target to which the upper portion of the conductive pattern G2 is exposed.                     

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의해야 한다. 또한, 본 발명의 기술 분야의 통상의 지식을 가진자라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

예를 들어, 층간절연막 상에 형성된 비트라인 사이에 스토리지노드 콘택을 위한 콘택플러그 형성시에도 동일하게 적용될수 있음을 이해할 수 있을 것이다.
For example, it will be appreciated that the same applies to the formation of contact plugs for storage node contacts between bit lines formed on the interlayer insulating layer.

상술한 본 발명에 의하면, 희생하드마스크를 이용한 SAC식각시, CO를 포함하는 가스를 이용함으로써, 피식각층에 대한 식각선택비를 높여 피식각층의 손상에 따른 SAC(Self Align Contact)페일 및 콘택 낫 오픈(Contact Not Open)을 방지할 수 있다.According to the present invention described above, by using a gas containing CO in the SAC etching using the sacrificial hard mask, by increasing the etching selectivity for the layer to be etched SAC (Self Align Contact) fail and contact sickle due to damage of the layer to be etched It can prevent the contact (Contact Not Open).

Claims (6)

기판 상에 도전패턴을 형성하는 단계;Forming a conductive pattern on the substrate; 상기 도전패턴 상에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the conductive pattern; 상기 층간절연막 상에 희생하드마스크용 물질막을 형성하는 단계;Forming a material film for a sacrificial hard mask on the interlayer insulating film; 상기 희생하드마스크용 물질막 상에 콘택홀 형성을 위한 포토레지스트 패턴을 형성하는 단계;Forming a photoresist pattern for forming a contact hole on the sacrificial hard mask material layer; 상기 포토레지스트 패턴을 식각마스크로 상기 희생하드마스크용 물질막을 식각하여 희생하드마스크를 형성하는 단계;Forming a sacrificial hard mask by etching the material layer for the sacrificial hard mask using the photoresist pattern as an etching mask; 상기 포토레지스트 패턴을 제거하는 단계;Removing the photoresist pattern; CO를 포함하는 가스를 이용하여 상기 하드마스크를 식각마스크로 상기 층간절연막을 식각하여 상기 기판을 노출시키는 콘택홀을 형성하는 단계Forming a contact hole exposing the substrate by etching the interlayer insulating layer using the hard mask as an etching mask using a gas containing CO; 를 포함하는 반도체 소자의 콘택플러그 형성 방법.Contact plug formation method of a semiconductor device comprising a. 제1항에 있어서, The method of claim 1, 상기 콘택홀을 형성하는 단계에서, 상기 CO에 CxFy(x, y 는 1 ∼10)를 더 포함하는 반도체 소자의 콘택플러그 형성 방법.In the step of forming the contact hole, the contact plug forming method of the semiconductor device further comprising CxFy (x, y is 1 to 10) in the CO. 제2항에 있어서,The method of claim 2, 상기 희생하드마스크용 물질막은 질화막 또는 폴리실리콘막을 포함하는 반도체 소자의 콘택플러그 형성 방법.The material layer for sacrificial hard mask comprises a nitride film or a polysilicon film. 제1항 내지 제3항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 3, 상기 희생하드마스크용 절연막을 500Å 내지 1500Å의 두께로 형성하는 반도체 소자의 콘택플러그 형성 방법.A method of forming a contact plug for a semiconductor device, wherein the sacrificial hard mask insulating film is formed to a thickness of 500 kV to 1500 kV. 제4항에 있어서,The method of claim 4, wherein 상기 층간절연막은 산화막을 포함하는 반도체 소자의 콘택플러그 형성 방법.And said interlayer insulating film comprises an oxide film. 제1항에 있어서,The method of claim 1, 상기 층간절연막을 형성 후, After forming the interlayer insulating film, 상기 도전패턴 상부가 노출되는 타겟으로 상기 층간절연막을 평탄화하는 단계를 더 포함하는 반도체 소자의 콘택플러그 형성 방법.And planarizing the interlayer insulating film to a target to which the upper portion of the conductive pattern is exposed.
KR1020040087876A 2004-11-01 2004-11-01 Method for forming contactplug of semicondutor device KR20060038746A (en)

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