KR20060030551A - Forming method of bottom electrode in semiconductor device - Google Patents

Abstract

The present invention provides a method for forming a lower electrode of a capacitor having a high process margin, a relatively uniform profile compared to a conventional MPS process, and having an uneven portion which reduces the possibility of bridging. Depositing a conductive film for a capacitor lower electrode on the layer; Coating a photoresist for ArF on the conductive film; Performing a photolithography process using an ArF exposure source to form a photoresist pattern in which a pattern shape is transferred to the ArF photoresist; Forming a lower electrode by etching the conductive layer using the photoresist pattern as an etching mask; And performing an additional etching process in a gas atmosphere including Ar to induce deformation of the photoresist pattern, and transferring the shape of the photoresist pattern induced by deformation to the surface of the lower electrode to form an uneven portion. Provided is a method of forming a capacitor lower electrode of a semiconductor device.

ArF, F2, lower electrode, irregularities, MPS, capacitance, pattern deformation.

Description

FIELD OF THE INVENTION Capacitor bottom electrode formation of a semiconductor device {FORMING METHOD OF BOTTOM ELECTRODE IN SEMICONDUCTOR DEVICE}             

1A to 1F are cross-sectional views illustrating a process of forming a capacitor lower electrode of a semiconductor device using an F ₂ or ArF exposure source according to an embodiment of the present invention.

2 is a plan view of FIG. 1F;

3 is a planar SEM photograph immediately after the application of the ArF photoresist.

4 is a planar SEM photograph after etching a photoresist pattern using a chlorine-based gas as an etching mask.

FIG. 5 is a planar SEM photograph showing the shape of the lower electrode uneven portion according to the etching time using the etching gas including Ar. FIG.

* Explanation of symbols for the main parts of the drawings

100: substrate 101: insulating film

102 plug 103a lower electrode

104b: irregularities

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of increasing capacitance by forming irregularities of a lower electrode without the addition of a separate unevenness forming process for increasing the surface area.

As the degree of integration of semiconductor memory devices such as DRAM (Dynamic Random Access Memory) increases, the area of the cell capacitor is decreasing. Since the reduction of the area of the cell capacitor means the reduction of the capacitance, various efforts are underway to secure the required capacitance.

There are three main approaches to increasing capacitance.

First, high dielectric constant with high dielectric constant is used as the dielectric film. Although this method can increase capacitance, there is a problem in that leakage current characteristics are deteriorated due to smaller energy band gap toward high dielectric constant thin films.

Second, to reduce the thickness of the dielectric thin film. This method is also undesirable because the leakage current increases.

Third, increase the area of the capacitor. This method is widely used because it can increase the capacitance with the same thickness as existing dielectric materials. For example, a method such as meta-stable poly silicon (MPS) is used. On the other hand, as semiconductor devices are highly integrated, the process margin is very small during MPS growth, it is difficult to deposit uniformly on the entire surface of the wafer, local un-growth occurs, and the probability of bridges between lower electrodes is generated. This is big.

The present invention proposed to solve the above problems of the prior art, the process margin is high, can obtain a relatively uniform profile compared to the conventional MPS process, the lower electrode formation of the capacitor having a concave-convex portion reducing the possibility of bridge generation The purpose is to provide a method.

In order to solve the above problems, the present invention includes the steps of depositing a conductive film for the capacitor lower electrode on the conductive layer; Coating a photoresist for ArF on the conductive film; Performing a photolithography process using an ArF exposure source to form a photoresist pattern having a pattern shape transferred to the ArF photoresist; Forming a lower electrode by etching the conductive layer using the photoresist pattern as an etching mask; And performing an additional etching process in a gas atmosphere including Ar to induce deformation of the photoresist pattern, and transferring the shape of the photoresist pattern induced by deformation to the surface of the lower electrode to form an uneven portion. Provided is a method of forming a capacitor lower electrode of a semiconductor device.

The present invention forms a lower electrode, that is, a storage node, of a capacitor using an ArF photolithography process technology applied from a semiconductor device manufacturing technology having a line width of 100 nm or less. In the case of ArF photoresist, when the substrate is excessively exposed to the gas containing Ar, pattern deformation occurs to induce the deformation of the photoresist pattern into the gas atmosphere containing Ar after forming the lower electrode. Subsequently, a portion of the lower electrode is etched and patterned by using the modified photoresist pattern to form bends, that is, irregularities on the lower electrode surface.

Therefore, the process margin can be increased while forming irregularities on the surface of the lower electrode as in the conventional MPS method, a relatively uniform profile can be obtained compared to the conventional MPS process, and the possibility of bridge generation can be reduced.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can more easily implement the present invention.

1A to 1F are cross-sectional views illustrating a process of forming a capacitor lower electrode of a semiconductor device using an F ₂ or ArF exposure source according to an embodiment of the present invention, which will be described in detail with reference to the drawings.

In the following embodiments, a stack type capacitor will be described as an example, and the present invention can be applied to various types of capacitors such as a cylinder type or a concave type.

First, as shown in FIG. 1A, an insulating film 101 is formed on a substrate 100 on which various elements for forming a semiconductor device are formed.

When the insulating film 101 is used as an oxide-based material film, a BSG (Boro-Silicate-Glass) film, BPSG (Boro-Phopho-Silicate-Glass) film, PSG (Phospho-Silicate-Glass) film, TEOS (Tetra- Ethyl-Ortho-Silicate (HDP) films, HDP (High Density Plasma) films, SOG (Spin On Glass) films, or APL (Advanced Planarization Layer) films are used. In addition to the oxide films, inorganic or organic low dielectric constant films are used.

The substrate 100 includes a substructure on which a transistor and a bit line are formed, and are omitted for simplicity of the drawings.

Subsequently, the insulating film 101 is selectively etched to form a contact hole H exposing the substrate 100, specifically, a cell contact plug. At this time, the etching profile of the contact hole H is aligned with the side of the bit line (not shown).

As illustrated in FIG. 1B, the plug forming conductive film is deposited on the entire surface where the contact hole H is formed to fill the contact hole H, and then chemical mechanical polishing (hereinafter referred to as CMP) or full surface etching. The process may be performed to form an isolated plug 102, specifically, a contact plug for a storage node.

As the plug 102, a polysilicon film is mainly used, and a metal film such as tungsten film may be used.

The conductive film 103 for the lower electrode is deposited on the plug 102.                     

As the lower electrode conductive film 103, various types of metals such as a polysilicon film, a tungsten film, a TiN film, and a Pt film may be used.

Meanwhile, a barrier film such as Ti or TiN may be used between the conductive film 103 for the lower electrode and the plug 102.

As shown in FIG. 1C, an ArF photoresist is coated on the lower electrode conductive film 103. The photoresist for ArF is a photoresist having a polymer form of COMA (CycloOlefin-Maleic Anhydride) or Acrylate system, or a mixture thereof.

Subsequently, baking, exposure, and development processes are performed to form a photoresist pattern 104 for lower electrode patterning.

3 is a planar SEM photograph immediately after applying the ArF photoresist, and it can be seen that the surface of the applied ArF photoresist is smooth as shown.

As shown in FIG. 1D, the lower electrode conductive film 103 is etched using the photoresist pattern 104 as an etch mask to form the lower electrode 103a of the capacitor.

When the polysilicon film is used as the conductive film 103 for the lower electrode, chlorine-based gas such as Cl ₂ or HBr is used during patterning.

In addition, when using a metal film, the CxFy (x, y is 1 ~ 10), CaHbFc uses Florin-based gas, such as (a, b, c is 1-10), or SF _6.

4 is a planar SEM photograph after etching a photoresist pattern using a chlorine-based gas as an etching mask.

Figure 4 (a) is a planar picture after etching for 60 seconds using Cl ₂ gas, as shown in Figure 3 it can be seen that the surface is smooth without deformation of the pattern.

Figure 4 (b) is a planar photo after etching for 120 seconds using Cl ₂ gas, as shown in Figure 3 and 4 (a) it can be seen that the surface is smooth without deformation of the pattern.

As shown in FIG. 1E, the etching process is performed using the photoresist pattern 104a remaining after the lower electrode 103a is formed as an etching mask under etching conditions resulting in pattern deformation in the photoresist for ArF.

Accordingly, the pattern deformation of the photoresist pattern 104b proceeds, that is, the local lumping and breaking of the pattern proceeds to have the shape shown in FIG. 1E in cross section.

As an etching condition that causes pattern deformation in the photoresist for ArF, a gas containing Ar is used. That is, Ar may include CF ₄ , Cl ₂ , HBr, or the like, or use Ar alone.

By partially etching the lower electrode 103a using the patterned photoresist pattern 104b, the shape of the photoresist pattern 104b in which the local agglomeration and disconnection of the pattern has progressed is formed on the upper portion of the lower electrode 103a. The uneven part 103b transferred to the lower part can be obtained.

In this process, the remaining photoresist pattern 104b is almost removed, but in the case of some remaining portions, the photoresist pattern 104b is removed through a photoresist strip process and an additional cleaning process is performed.

1F shows a cross section in which a lower electrode 103a having unevenness 103b is formed thereon.

The size and distribution of the unevenness 103b can be adjusted by changing the etching time in the gas atmosphere containing Ar. The change in the size and distribution of the unevenness 103b indicates the change in the capacitance.

As the etching conditions increase the surface temperature of the wafer during the plasma etching process including Ar, the surface morphology of the photoresist for ArF becomes more rough.

In order to increase the unevenness 103b, the substrate temperature is preferably 20 ° C or higher and the power is 50W or higher.

FIG. 2 is a plan view of FIG. 1F, and FIG. 1F corresponds to a cut cross section taken along the line AA ′ of FIG. 2. Referring to FIG. 2, it can be seen that the shape of the uneven portion 103b may appear in various shapes on a plane.

FIG. 5 is a planar SEM photograph showing the shape of the lower electrode uneven portion according to the etching time using the etching gas including Ar.

5A illustrates a case of etching for 30 seconds using Ar, FIG. 5B illustrates a case of etching for 60 seconds, and FIG. 5C illustrates a case of etching for 120 seconds. That is, it can be seen that the pattern deformation deepens over time.

According to the present invention made as described above, the ArF photoresist is used to form the lower electrode by using the characteristics of the ArF photoresist in which the pattern deformation occurs during etching in the gas atmosphere including Ar, and this is the gas atmosphere containing Ar. By further etching to induce a pattern deformation, and the transfer of the modified pattern shape to the bottom was formed by the irregularities in the lower electrode was found through the embodiment to increase the cross-sectional area of the capacitor.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

For example, in the above-described embodiment, only the stacked capacitor lower electrode is used as an example, but it is also applicable to the capacitor lower electrode having various shapes such as a cylinder type or a concave type.

The present invention described above has an uneven portion and increases the cross-sectional area, but the process margin is high, and a relatively uniform profile can be obtained compared to the conventional MPS process, and the possibility of bridge generation can be reduced, thereby greatly improving the yield and productivity of the semiconductor device. It can be effected.

Claims (5)

Depositing a conductive film for a capacitor lower electrode on the conductive layer; Coating a photoresist for ArF on the conductive film; Performing a photolithography process using an ArF exposure source to form a photoresist pattern having a pattern shape transferred to the ArF photoresist; Forming a lower electrode by etching the conductive layer using the photoresist pattern as an etching mask; And Performing an additional etching process in a gas atmosphere including Ar to induce deformation of the photoresist pattern, and transferring the shape of the photoresist pattern induced by deformation to the surface of the lower electrode to form an uneven portion; Capacitor bottom electrode forming method of a semiconductor device comprising a. The method of claim 1, In the step of forming the concave-convex portion, the method of forming a capacitor lower electrode, characterized in that to maintain the temperature of the substrate to at least 20 ℃, at least 50W of power. The method according to claim 1 or 2, The conductive film is a capacitor lower electrode forming method comprising a polysilicon film. The method of claim 3, wherein In the forming of the lower electrode, the method of forming a capacitor lower electrode, characterized in that using the plasma etching method using a chlorine-based gas. The method of claim 1, The lower electrode is a capacitor bottom electrode forming method, characterized in that any one of a stacked, cylindrical or concave shape.

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