KR20060029094A - Plasma display panel - Google Patents

Abstract

The present invention relates to a plasma display panel capable of preventing a reduction in contrast due to light reflection.

In the plasma display panel of the present invention, a plurality of display electrodes composed of a pair of parallel scan electrodes and a sustain electrode formed on the substrate on the display surface side are disposed, and a plurality of address electrodes are arranged on the substrate on the rear side in a direction crossing the display electrodes. A three-electrode surface discharge type plasma display panel which is disposed, and divides a discharge cell into a substrate on the rear side, and a phosphor is formed between the barrier ribs, wherein the dielectric layer formed on the earth electrode and the phosphor are formed. It characterized in that it comprises a light reflection reduction layer.

Description

Plasma Display Panel             

1 is a perspective view illustrating a discharge cell structure of a conventional plasma display panel.

2 is a cross-sectional view illustrating a discharge cell structure of a conventional plasma display panel.

3 is a diagram illustrating reflection of light incident from the outside.

4 is a cross-sectional view illustrating a discharge cell structure of a plasma display panel according to a first embodiment of the present invention.

5A to 5E are views illustrating the manufacture of a plasma display panel according to an exemplary embodiment of the present invention.

6A-6C are views relating to the manufacture of FIG. 5D.

7 is a cross-sectional view illustrating a discharge cell structure of a plasma display panel according to a second embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

10,40: upper substrate

12Y, 12Z, 42Y, 42Z, 142Y, 142Z,: transparent electrode

13Y, 13Z, 43Y, 43Z, 143Y, 143Z: Bus electrode

14,22,44,52,152: dielectric layer 16,46: protective film

18,48: Lower substrate 24,54,154: Bulkhead

26,56,156: phosphor 32: black matrix

60: light reflection reduction layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a plasma display panel capable of preventing contrast reduction by reducing light reflection.

Plasma Display Panels (hereinafter referred to as "PDPs") are characterized by emitting phosphors by 147 nm ultraviolet rays generated during discharge of an inert mixed gas such as He + Xe, Ne + Xe or He + Ne + Xe. An image containing graphics is displayed. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

1 and 2 are a perspective view and a cross-sectional view showing a discharge cell structure of a conventional plasma display panel. Here, FIG. 2 shows the lower substrate rotated 90 ° with respect to the upper substrate so that the structure of the discharge cell can be shown in detail.

Referring to FIGS. 1 and 2, the discharge cells of the three-electrode AC surface discharge type PDP have a scan electrode Y and a sustain electrode Z formed on the upper substrate 10, and an address formed on the lower substrate 18. An electrode X is provided. Each of the scan electrode Y and the sustain electrode Z has a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z and is formed at one edge of the transparent electrode 13Y, 13Z).

The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance.

The light blocking layer 30 corresponding to the width of the metal bus electrodes 13Y and 13Z is formed between the transparent electrodes 12Y and 12Z and the metal bus electrodes 13Y and 13Z. The light blocking layer 30 is formed of a black material to prevent the light incident to the metal bus electrodes 13Y and 13Z from being re-emitted to the outside. In other words, the light blocking layer 30 prevents the contrast of the PDP from being lowered by absorbing the light incident from the outside and preventing the incident light from being emitted to the outside.

The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode Y and the sustain electrode Z side by side. The wall charges generated during the plasma discharge are accumulated in the upper dielectric layer 14. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. Here, the protective film 16 is usually formed of magnesium oxide (MgO).

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode X is formed, and the phosphor 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode X is formed in the direction crossing the scan electrode Y and the sustain electrode Z. The partition wall 24 is formed in a stripe or lattice shape to prevent the ultraviolet rays and the visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert mixed gas is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The black matrix 32 is formed at the boundary of the discharge cell. The black matrix 32 absorbs external incident light and light emitted from the discharge cell to the outside to prevent the contrast of the PDP from being lowered.

In such a conventional PDP, the phosphor 26 is excited at a specific wavelength band to generate sufficient visible light, that is, to improve the brightness of the PDP, so that current saturation characteristics, deterioration characteristics, color purity, afterglow characteristics, driving voltages, and resistive forces are increased. It should preferably be provided and formed white to increase the reflectance of light generated by the discharge in the discharge cell. When the white phosphor 26 discharges in a discharge cell and the plasma particles collide with the phosphor, one of the wavelengths of a specific wavelength band, that is, red (R), green (G), and blue (B), is excited and colored. Will be expressed. In order to satisfy this condition, the white phosphor 26 maintains white color, and adjusts the composition ratio of additives added to the phosphor so that a specific wavelength is excited to express color.

However, the white phosphor 26 improves the contrast by improving the efficiency of light by improving the reflectance of light generated by the discharge in the discharge cell, but also increases the reflectance of light incident from the outside as shown in FIG. 3. Accordingly, a problem arises in that the overall contrast of the panel is reduced by light reflected from the white phosphor 26 of the PDP from the outside.

Accordingly, it is an object of the present invention to provide a plasma display panel which is capable of preventing contrast degradation due to light reflection.

In order to achieve the above object, in the plasma display panel of the present invention, a plurality of display electrodes composed of a pair of parallel scan electrodes and a sustain electrode formed on a substrate on the display surface side are disposed, and the display electrode intersects the display electrodes on the substrate on the rear side. A three-electrode surface discharge plasma display panel in which a plurality of address electrodes are disposed in a direction, partition walls for dividing discharge cells are formed on the substrate on the rear side, and phosphors are formed between the partition walls. And a light reflection reduction layer between the dielectric layer and the phosphor.

The light reflection reduction layer is formed in a partial region or the entire region between the partition walls.

The light reflection reduction layer reduces the light reflectance of external light incident from the outside to within 50%.

The light reflection reduction layer is formed of a dark color resin.

In the plasma display panel according to an exemplary embodiment of the present invention, a plurality of display electrodes including a pair of parallel scan electrodes and a sustain electrode formed on a substrate on a display surface side are disposed, and a display electrode on a rear side substrate intersects with the display electrodes. In a three-electrode surface discharge plasma display panel in which a plurality of address electrodes are disposed, partition walls for dividing discharge cells are formed on the substrate on the rear side, and phosphors are formed between the partition walls, wherein the substrate on the rear side and the address electrode are formed. It is formed on the dielectric layer to reduce the light reflectance of the external light incident from the outside.

The dielectric layer is formed by adding a black pigment or black resin that reduces light reflection to the dielectric paste.

The dielectric layer has a light reflectance of 50% or less.

An electrode formed on a substrate, the dielectric layer formed on the electrode and the substrate, barrier ribs vertically spaced apart from each other at a predetermined interval on the dielectric layer, the white phosphor formed on the barrier ribs and the dielectric layer; ; And a light reflection reduction layer formed between the dielectric layer and the white phosphor to reduce reflection of light incident from the outside.

The light reflection reduction layer reduces the light reflectance to within 50%.

The light reflection reduction layer is formed of a black resin.

According to an embodiment of the present invention, a plasma display panel includes an electrode formed on a substrate, a dielectric layer formed on the electrode and the substrate and reducing reflection of light incident from the outside, and spaced apart at a predetermined interval on the dielectric layer. Barrier ribs extending vertically and a white phosphor formed on the barrier ribs and the dielectric layer.

The dielectric layer is formed by adding a material for reducing light reflection to the dielectric paste.

The substance which reduces the light reflection is any one of a black pigment and a black resin.

The dielectric layer reduces reflection of light incident from the outside to within 50%.

A method of manufacturing a plasma display panel according to an embodiment of the present invention includes forming an address electrode on a substrate; Forming a dielectric layer on the substrate and the address electrode; Forming a plurality of partitions on the dielectric layer; Forming a white phosphor on the partitions and the dielectric layer; And forming a light reflection reduction layer between the dielectric layer and the white phosphor.

A method of manufacturing a plasma display panel according to an embodiment of the present invention includes forming an address electrode on a substrate; Forming a dielectric layer on the substrate and the address electrode to reduce external light reflection; Forming a plurality of partition walls on the dielectric layer; Forming a white phosphor on the partitions and the dielectric layer.

Forming a dielectric layer to reduce light reflection on the substrate and the address electrode; A light reflection reducing material is added to the dielectric paste to form a dielectric layer on the substrate and the address electrode.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 8.

4 is a cross-sectional view illustrating a discharge cell structure of a plasma display panel according to a first embodiment of the present invention. 4 shows the lower substrate 48 rotated 90 ° with respect to the upper substrate 40 so that the structure of the discharge cell can be shown in detail.

Referring to FIG. 4, the discharge cells of the plasma display panel according to the embodiment of the present invention are formed on the scan electrode Y and the sustain electrode Z formed on the upper substrate 40, and the lower substrate 48. The dielectric layer 52 formed on the address electrode X, the lower substrate 48 and the address electrode X, and the partition wall 54 vertically spaced apart at predetermined intervals from one side of the upper portion of the dielectric layer 52. ), A phosphor 56 formed on the partition walls 54 and the dielectric layer 52, and a light reflection reduction to reduce light reflection while forming a predetermined thickness between the phosphor 56 and the dielectric layer 52. Layer 60.

Each of the scan electrode Y and the sustain electrode Z has a line width smaller than that of the transparent electrodes 42Y and 42Z and the transparent electrodes 42Y and 42Z, and is formed on one edge of the transparent electrodes 42Y and 42Z. Bus electrodes 43Y and 43Z.

The transparent electrodes 42Y and 42Z are usually formed on the upper substrate 40 by indium tin oxide (ITO). The metal bus electrodes 43Y and 43Z are formed of a metal such as chromium (Cr) on the transparent electrodes 42Y and 42Z, thereby reducing the voltage drop caused by the transparent electrodes 42Y and 42Z having high resistance.

The upper dielectric layer 44 and the passivation layer 46 are stacked on the upper substrate 40 having the scan electrode Y and the sustain electrode Z side by side. The wall charges generated during the plasma discharge are accumulated in the upper dielectric layer 44. The passivation layer 46 prevents damage to the upper dielectric layer 44 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As such a protective film 46, magnesium oxide (MgO) is usually used.

The dielectric layer 52 and the partition wall 54 are formed on the lower substrate 48 on which the address electrode X is formed, and the phosphor 56 is coated on the surfaces of the dielectric layer 52 and the partition wall 54. The address electrode X is formed in the direction crossing the scan electrode Y and the sustain electrode Z.

The partition wall 54 is formed in a stripe or lattice form to prevent ultraviolet rays and visible light generated by the discharge from leaking into adjacent discharge cells.

The phosphor 56 is white and is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue.

The light reflection reduction layer 60 is formed between the phosphor 56 and the dielectric layer 52, and has a low saturation and brightness to reduce reflection of light incident from the outside within 50%, for example, black, gray, It is formed in brown or the like. Black resin or the like may be used as a material of the light reflection reduction layer 60.

Meanwhile, the light reflection reduction layer 60 according to the first embodiment of the present invention may be formed in a portion of the dielectric layer 52 or over the entire region. That is, the light reflection reduction layer 60 may be formed over a partial region or the entire region of the space between the partition walls 54 partitioning the discharge cells. In addition, the light reflection reduction layer 60 may be formed in a connected shape without breaking, or may be formed in a plurality of divided shapes having a break.

The lower plate manufacturing process of the PDP according to the first embodiment of the present invention will be described in detail with reference to FIGS. 5A to 5D.

First, the address electrode X is formed on the lower substrate 48 using a photolithography process or the like. In detail, the electrode layer is deposited as a thin film on the lower substrate 48 by sputtering or spin and spinless methods. After total application of photoresist on the deposited thin film, a screen mask of the type required by the user is placed on top of the applied photoresist. Next, the photoresist except for the masked portion is exposed using ultraviolet (UV) light, and then the exposed photoresist is developed using a developer. Finally, after etching, the address electrode X is formed as shown in FIG. 5A.

On the lower substrate 48 on which the address electrode X is formed, as shown in FIG. 5B, a dielectric material is printed on the entire surface to form the dielectric layer 52.

Next, as shown in FIG. 5C, a partition wall is formed on the dielectric layer 52 using any one of a mold process, sandblasting, and photolithography process.

In detail, the mold process forms a partition wall by applying pressure to a mold having an intaglio shape of a partition wall to be formed on the green sheet.

In the sand blasting process, after depositing a dry film, which is a photosensitive material, on the entire surface of the barrier paste, the mask having a form of the barrier rib is disposed, and the dry film of the unmasked portion is exposed using ultraviolet rays. The exposed dry film is developed using a developer. Subsequently, the partition wall is completed by spraying the sand particles to physically remove the partition paste for the portion where the dry film is developed.

In the photolithography process, the photoresist, which is a photosensitive material, is applied to the entire surface of the barrier rib paste, and then a mask having a barrier rib shape is disposed. Thereafter, the ultraviolet light is irradiated from the upper portion of the mask to expose the unmasked photoresist. After the exposed photoresist is developed by using a developer, the partition wall is completed by removing the partition paste for the portion where the photoresist is developed by using a chemical reaction in an etching process.

After the partition wall 54 is completed, the light reflection reduction layer 60 is formed on the dielectric layer 52 as shown in FIG. 5D.

After the light reflection reduction layer 60 is completed, the white phosphor on the partition 54, the dielectric layer 52, and the light reflection reduction layer 60 by using an inkjet injection method and a squeegeeing method as shown in FIG. 5E. 56 is formed. Specifically, each phosphor is emitted in the form of white under visible light, but each of which has red, blue, and green wavelengths excited by discharge.

Here, the manufacturing process of the light reflection reduction layer 60 and the phosphor will be described in detail with reference to FIGS. 6A to 6C.

First, as illustrated in FIG. 6A, the first mask 62 is disposed on the lower substrate 48 on which the partition wall 54 is completed.

Next, as shown in FIG. 6B, a black resin or the like, which is a material of the light reflection reduction layer 60, is formed. In this case, the first mask 62 is manufactured to have a size enough to cover the partition wall 54 so that the light reflection reduction layer 60 is not formed on the partition wall 54.

Thereafter, as shown in FIG. 6C, the second mask 64 is disposed, and the white phosphor 56 is injected. In this case, the second mask 64 is fabricated in such a size that the white phosphor 56 may be deposited on the partition wall 54, the dielectric layer 52, and the light reflection reduction layer 60.

7 is a cross-sectional view illustrating a discharge cell structure of a plasma display panel according to a second embodiment of the present invention. 7 illustrates that the lower substrate 148 is rotated 90 ° with respect to the upper substrate 140 so that the structure of the discharge cell can be shown in detail.

Referring to FIG. 7, the discharge cells of the plasma display panel according to the second embodiment of the present invention are formed on the scan electrode Y and the sustain electrode Z formed on the upper substrate 140, and on the lower substrate 148. The dielectric layer 152 formed on the formed address electrode X, the lower substrate 148 and the address electrode X, and reducing light reflection, and spaced apart from one side of the upper portion of the dielectric layer 152 by a predetermined interval. Barrier ribs 154 extending vertically, and the phosphors 156 formed on the barrier ribs 154 and the dielectric layer 152.

Each of the scan electrode Y and the sustain electrode Z has a line width smaller than that of the transparent electrodes 142Y and 142Z and the transparent electrodes 142Y and 142Z, and is formed on one edge of the transparent electrodes 142Y and 142Z. Bus electrodes 143Y and 143Z.

The transparent electrodes 142Y and 142Z are typically formed on the upper substrate 140 by indium tin oxide (ITO). The metal bus electrodes 143Y and 143Z are formed on the transparent electrodes 142Y and 142Z by using a metal such as chromium (Cr), thereby reducing the voltage drop caused by the transparent electrodes 142Y and 142Z having high resistance.

The upper dielectric layer 144 and the passivation layer 146 are stacked on the upper substrate 140 having the scan electrode Y and the sustain electrode Z side by side. The wall charges generated during the plasma discharge are accumulated in the upper dielectric layer 144. The protective layer 146 prevents damage to the upper dielectric layer 144 due to sputtering generated during plasma discharge, and increases emission efficiency of secondary electrons. As such a protective film 146, magnesium oxide (MgO) is usually used.

The dielectric layer 152 and the partition wall 154 for reducing light reflection are formed on the lower substrate 148 on which the address electrode X is formed, and the phosphor 156 is coated on the surfaces of the dielectric layer 152 and the partition wall 154. The address electrode X is formed in the direction crossing the scan electrode Y and the sustain electrode Z.

The dielectric layer 152 according to the second embodiment of the present invention is formed such that reflection of light incident from the outside is reduced to within 50%, and is formed by combining a dielectric paste and a black pigment in the process of forming the dielectric layer 152. This allows the dielectric layer 152 to reduce light reflection. Here, the materials combined to form the dielectric layer 152 for reducing light reflection are not limited to black pigments. That is, the dielectric layer 152 may be formed by synthesizing a pigment and a resin of low saturation and brightness with a dielectric paste so as to reduce light reflection.

The partition wall 154 is formed in a stripe or lattice shape to prevent the ultraviolet rays and the visible light generated by the discharge from leaking to the adjacent discharge cells.

The phosphor 156 is white and is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue.

A method of manufacturing a lower plate of a PDP according to a second embodiment of the present invention having such a structure will be described.

First, an address electrode X is formed on a lower substrate 148 using a photolithography process or the like as in FIG. 5A, which illustrates a lower plate manufacturing of a PDP according to a first embodiment of the present invention.

Next, a dielectric paste containing a material for reducing light reflection is deposited on the lower substrate 148 and the address electrode X to form a dielectric layer 152 for reducing light reflection. The method of depositing such a dielectric paste is deposited in the same manner as the formation of the dielectric layer 52 described in the first embodiment of the present invention.

Subsequently, the partition and the phosphor are formed in the same manner as in the first embodiment of the present invention, so description thereof will be omitted.

 As described above, according to the plasma display panel according to the present invention, the reflectance of light incident from the outside is reduced to within 50% of the incident light by using the light reflection reduction layer and the dielectric layer to reduce the light reflection to improve the contrast of the plasma display panel. Can be.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (7)

A plurality of display electrodes composed of a pair of parallel scan electrodes and a sustain electrode formed on the substrate on the display surface side are disposed, and a plurality of address electrodes are disposed on the substrate on the rear side in a direction crossing the display electrodes. In a three-electrode surface discharge plasma display panel in which a partition wall for dividing a discharge cell is formed on a substrate, and a phosphor is formed between the partition walls. And a light reflection reduction layer between the dielectric layer formed on the address electrode and the phosphor. The method of claim 1, And the light reflection reduction layer is formed in a partial region or an entire region between the partition walls. The method of claim 2, The light reflection reduction layer reduces the light reflectance of external light incident from the outside to within 50%. The method of claim 2, The light reflection reduction layer is plasma display panel, characterized in that formed of a dark-based resin. A plurality of display electrodes composed of a pair of parallel scan electrodes and a sustain electrode formed on the substrate on the display surface side are disposed, and a plurality of address electrodes are disposed on the substrate on the rear side in a direction crossing the display electrodes. In a three-electrode surface discharge plasma display panel in which a partition wall for dividing a discharge cell is formed on a substrate, and a phosphor is formed between the partition walls. And a dielectric layer formed on the back side substrate and the address electrode to reduce light reflectance of external light incident from the outside. The method of claim 5, wherein And said dielectric layer is formed by adding black pigment or black resin for reducing light reflection to dielectric paste. The method of claim 5, wherein And said dielectric layer has said light reflectance of 50% or less.

Images