KR20060027971A - Pixel circuit in the solid state image sensing device having sensitivity controllable photodiode and driving method thereof - Google Patents

Abstract

Disclosed are a pixel circuit of a solid-state imaging device using an optical device capable of sensitivity control and a driving method thereof. An optical element used in the pixel circuit includes a diode for photoelectric conversion and an MOS capacitor whose capacitance is changed by a sensitivity control signal electrode formed over the diode. The image signal output gain may be adjusted for each pixel by controlling the sensitivity control signal.

Description

Pixel circuit in the solid state image sensing device having sensitivity controllable photodiode and driving method

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram showing a general CIS type solid-state imaging device.

2 is an example showing a general color filter pattern of an APS array.

3 is a general unit pixel driving circuit diagram of an APS array.

4 is a unit pixel circuit diagram of a CIS type solid-state imaging device according to an embodiment of the present invention.

FIG. 5 is an exemplary view illustrating a specific structure of the optical device of FIG. 4 implemented in a semiconductor substrate. FIG.

6 is a C-V graph illustrating the characteristics of the MOS capacitor formed in the optical device of FIG. 4.

7 is an exemplary view illustrating another structure of the optical device of FIG. 4.

8 is a unit pixel circuit diagram of a CIS type solid-state imaging device according to another embodiment of the present invention.                 

9 is a timing diagram for describing an operation of the pixel circuit of FIG. 8.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid state image sensing device, and more particularly, to a pixel circuit of a CMOS image sensor (CIS) type solid state imaging device and a driving method of the solid state imaging device.

The CIS-type solid-state imaging device is mounted on a mobile phone camera, a digital still camera, or the like, and captures an image developed in a field of view, converts the image into an electrical signal, and transmits it to a digital signal processor. The digital signal processing unit processes the color image data R, G, and B output from the solid state image pickup device to drive a display device such as a liquid crystal display (LCD).

1 is a block diagram showing a general CIS type solid-state imaging device 100. Referring to FIG. 1, a typical CIS type solid-state imaging device 100 includes an active pixel sensor (APS) array 110, a row driver 120, and an analog-digital converter (ADC). 130 is provided. The row driver 120 receives a control signal from a row decoder (not shown), and the analog-to-digital converter 130 receives a control signal from a column decoder (not shown). In addition, the solid-state imaging device 100 includes a control unit (not shown) for generating general timing control signals and addressing signals for selecting each pixel and outputting a sensed image signal. In general, in the case of the color solid-state imaging device 100, as shown in FIG. 2, a color filter is installed to receive only light of a specific color on each pixel forming the APS array 110. In order to arrange at least three kinds of color filters. The most common color filter array is Bayer, where the patterns of two colors R (red) and G (green) are arranged in one row, and the patterns of two colors G (green) and B (blue) are arranged in another row. ) Has a pattern. At this time, G (green), which is closely related to the luminance signal, is disposed in every row, and R (red) color and B (blue) color are alternately arranged in each row to increase the luminance resolution. Digital still cameras, etc. are applied to a CIS array of many million pixels or more in order to increase the resolution.

In the CIS type solid-state imaging device 100 having such a pixel structure, the APS array 110 detects light using a photodiode and converts the light into an electrical signal to generate an image signal. The video signal output from the APS array 110 is an analog signal of three colors of red (R), green (G), and blue (B). The analog-digital converter 130 receives an analog image signal output from the pixel array 110 and converts the analog image signal into a digital signal.

In the general CIS type solid-state imaging device 100 as shown in FIG. 1, when converting an image signal detected by an optical device into a digital signal by the analog-digital converter 130, a correlated double sampling (CDS) method is used. Such a driving method is well described in the US patent, "USP5,982,318", or "USP6,067,113". 3 is a general unit pixel driving circuit diagram of an APS array in a CDS scheme. Referring to FIG. 3, a general pixel driving circuit 300 includes a pixel circuit 310 including three metal-oxide-semiconductor field effect transistors (MMOS) M1 to M3 and one optical device PD, And a bias circuit 320 for biasing the output (VRES / VSIG) node of the pixel circuit 310. The pixel circuit 310 is provided in each pixel of the APS array 110, and the bias circuit 320 is provided around the top or bottom of the APS array 110. In the analog-to-digital conversion of the CDS method, after receiving the reset signal VRES from the pixel circuit 310, it is divided into two stages of receiving the image signal VSIG detected by the optical device PD and converting it into a digital signal. . In FIG. 3, when the reset control signal RX is activated in the logic high state while the row select signal SEL is activated in the logic high state, the voltage of the FD node transferred from the power supply VDD is the source follower ( source follower) is output through the source terminal of transistor M3. The voltage of the FD node output to the source terminal of M3 is output to the analog-to-digital converter 130 as a reset signal VRES through the source terminal of M1. On the other hand, when the reset control signal RX becomes the logic low state while the row select signal SEL is active in the logic high state, the image signal VSIG photoelectrically converted from the optical device PD is the source terminal of M1. Through the analog-to-digital converter 230 is output. When the row select signals SEL1, SEL2, SEL3,... Of FIG. 2 are sequentially activated by the operation of the pixel circuit 310 as described above, the reset signals VRES1, VRES2, VRES3, ...) and video signals VSIG1, VSIG2, VSIG3, ... are output.

The analog-digital converter 230 converts an analog signal corresponding to the difference of the image signal VSIG to the output reset signal VRES into a digital signal and outputs the digital signal. The digital signal converted as described above is output to the digital signal processor and subjected to a predetermined interpolation process. In addition, the digital signal processor generates driving signals suitable for a corresponding resolution of a display device such as an LCD to drive the display device.

As described above, the pixel circuit 310 of the CIS-type solid-state imaging device 100 typically includes an optical device PD for sensing light and converting the light into an electrical signal. Recently, a silicon retina or a high performance smart image sensor using the APS array 110 including such an optical device PD has been developed. Such new applications require easy adjustment of sensitivity or spectral response on a pixel-by-pixel basis. However, there is a problem in that the pixel area is not sufficient to add a variable capacitor for adjusting the light sensitivity of each pixel to the pixel circuit 310 as shown in FIG. 3. Even if the pixel area is sufficient, due to the area occupied by the added variable capacitor, there is a problem in that the area of the optical device PD is relatively small, which may lower the overall brightness when displaying an image.

Accordingly, the technical problem to be achieved by the present invention is a pixel circuit and a solid-state imaging of a solid-state imaging device using an optical device that simultaneously performs a photoelectric conversion action and a variable capacitor action for sensitivity control without a separate area on the semiconductor substrate occupied by the variable capacitor. It is to provide a method of driving the device.

The pixel circuit of the solid-state imaging device according to the present invention for achieving the above technical problem is characterized by comprising a first MOSFET, a second MOSFET, a third MOSFET, and an optical element. In the first MOSFET, a gate electrode receives a row select signal, one side of the source / drain electrodes is connected to the first node, and the other side is connected to the output node. In the second MOSFET, the gate electrode receives a reset control signal, one side of the source / drain electrodes is connected to the first power supply, and the other side is connected to the second node. The third MOSFET has a gate electrode connected to the second node, one side of the source / drain electrodes is connected to the first power supply, and the other side is connected to the first node. The optical device has a diode for photoelectric conversion between a second power supply and the second node and a MOS capacitor having a variable capacitance between the second node and the sensitivity control signal electrode according to a sensitivity control signal. Here, in response to the reset control signal in a state in which the row selection signal is activated, a reset signal and a photoelectrically converted signal from the optical device are output through the output node connected to a bias circuit.

A pixel circuit of a solid-state imaging device according to another aspect of the present invention for achieving the above technical problem is characterized by comprising a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET and an optical element. In the first MOSFET, a gate electrode receives a row select signal, one side of the source / drain electrodes is connected to the first node, and the other side is connected to the output node. In the second MOSFET, a gate electrode receives a reset control signal, one side of the source / drain electrodes is connected to a first power supply, and the other side is connected to a second node. The third MOSFET has a gate electrode connected to the second node, one side of the source / drain electrodes is connected to the first power supply, and the other side is connected to the first node. The optical device has a diode for photoelectric conversion between a second power supply and a third node, and an MOS capacitor having a variable capacitance between the third node and the sensitivity control signal electrode according to a sensitivity control signal. In the fourth MOSFET, a gate electrode receives a transfer control signal, one side of the source / drain electrodes is connected to the second node, and the other side is connected to the optical device output node. Here, in response to the reset control signal in a state in which the row selection signal is activated, a reset signal is output through the output node connected to a bias circuit, and in the optical device through the output node in response to the transfer control signal. And outputting a photoelectrically converted signal.

According to another aspect of the present invention, there is provided a method of driving a solid-state imaging device, wherein the reset control is performed in the method of driving a solid-state imaging device including a pixel circuit having an optical device in each pixel of an APS (Active Pixel Sensor) array. Outputting a reset signal in the pixel circuit when the signal is in a first logic state; Outputting a photoelectrically converted signal from a diode included in the optical device as an image signal when the reset control signal is in a second logic state; And converting an analog signal corresponding to the difference of the video signal with respect to the reset signal into a digital signal and outputting the digital signal, and changing the capacitance of the MOS capacitor included in the optical device according to a sensitivity control signal. The output gain can be adjusted.                     

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

The unit pixel circuit 400 of the CIS type solid-state imaging device according to the exemplary embodiment of the present invention is illustrated in FIG. 4. The pixel circuit 400 is a circuit provided in each pixel of the APS array as shown in FIG. 1, and is operated by a CDS in operation with a bias circuit (for example, 320 of FIG. 3) provided near or above the APS array. A reset signal VRES and an image signal VSIG for analog-to-digital conversion of the (Correlated Double Sampling) method are output.

The pixel circuit 400 includes a first metal-oxide-semiconductor field effect transistor (MMOS), a second MOSFET (M12), a third MOSFET (M13), and a photodiode (PD). . The photodiode PD has a MOS capacitor C _SCG that receives a sensitivity control signal SCG over an existing photonic device region as a main part of the present invention without a separate region on a semiconductor substrate. The specific structure of such a semiconductor substrate (PD) of the optical device (PD) is shown in FIG. The capacitance of the MOS capacitor C _SCG included in the optical device PD is variable according to the sensitivity control signal SCG, and thus sensitivity or spectral response in a pixel. This may vary from pixel to pixel. The optical device PD is described in more detail in the descriptions of FIGS. 6 and 7.

The first MOSFET M11 receives a row select signal SEL at its gate electrode, one side of the source / drain electrodes is connected to the first node N1, and the other side is connected to the output VRES / VSIG node. do. In the second MOSFET M12, a gate electrode receives a reset control signal RX, one of the source / drain electrodes is connected to the first power supply VDD, and the other of the second MOSFET M12 is connected to the second node FD. . In the third MOSFET M13, a gate electrode is connected to the second node FD, one side of the source / drain electrodes is connected to the first power source VDD, and the other side is the first node N1. ) Is connected. The optical device PD is connected to the second node FD according to a diode D1 and a sensitivity control signal SCG for photoelectric conversion between the second power supply VSS and the second node FD. The capacitance between the sensitivity control signal SCG electrodes has a variable MOS capacitor C _SCG .

For example, as illustrated in Figure 5, the diode (D1) is a P-type semiconductor substrate (p-sub) and the N-type impurity I ping-well (well) (n ^-) forming a PN junction diode between The MOS capacitor C _SCG is formed to have an upper vertical structure in a part of the region occupied by the diode D1. That is, in order to form the MOS capacitor C _SCG , an insulating film is formed on the low doping well n ⁻ , and then a gate metal for the gate electrodes of the MOSFETs M11 to M13 is formed thereon. During the metal process, a metal process for the sensitivity control signal SCG electrode of the MOS capacitor C _SCG is simultaneously performed. In order to allow external light to pass through the electrode receiving the sensitivity control signal _{SCG in} the MOS capacitor C _SCG and be absorbed in the diode D1 region, the metal electrode receiving the sensitivity control signal SCG is It should be formed of a transparent conductive film. At this time, poly-Si having appropriate conductivity and suitable light transmitting property is preferable as the gate metal.

The CV characteristic of the MOS capacitor C _SCG thus formed is shown in FIG. 6. Referring to FIG. 6, V _BG is a voltage between the second node N2 and the sensitivity control signal SCG electrode, and Cmos is a capacitance of the MOS capacitor C _SCG . Cox is the theoretical capacitance when there is an ideal metal electrode above and below the insulating film formed on the low doping well (n ⁻ ). In FIG. 6, as is well known, the capacitance of a typical P-type MOS capacitor is close to Cox as the capacitor operates as an inversion correction signal generator 335 when the voltage across the capacitor increases. However, the capacitance of the MOS capacitor C _SCG according to the present invention is characterized in that the capacitor operates in the charge depletion mode as the V _BG increases, and thus gradually decreases. In FIG. 4, when the reset control signal RX is in a logic high state, the second node FD has a voltage corresponding to the first power source VDD, and thus, the second node N2. The voltage between the low doping well (n ⁻ ) and the sensitivity control signal (SCG) electrode in contact with the electrode corresponds to the case where the V _BG has a positive value, and the MOS capacitor (C _SCG ) This is because it operates in a depletion mode of a hole. By using the characteristics of the MOS capacitor C _SCG , the capacitance between the second node FD and the sensitivity control signal SCG electrode is changed to a voltage applied to the sensitivity control signal SCG electrode. In this way, the sensitivity or the spectral response for each pixel can be controlled.

A diagram illustrating another structure of the optical device PD of FIG. 4 is shown in FIG. 7. The structure shown in FIG. 7 in which a separate impurity doped region is additionally inserted into the MOS capacitor C _SCG formation region as shown in FIG. 5 has a depletion mode characteristic and an inversion as shown in FIG. 6. The structure can use the mode characteristic at the same time. That is, in the structure as shown in FIG. 7, the MOS capacitor C _SCG has a MOS structure capacitor and the sensitivity control between the electrode receiving the sensitivity control signal SCG and the low doping well n ^- region. And another MOS structure capacitor between the electrode receiving the signal SGG and the separate impurity doping region. As the impurity doped region is doped with N-type or P-type impurities, the additionally added MOS structure capacitor may exhibit inversion mode characteristics or depletion mode characteristics. Accordingly, the MOS capacitor C _SCG having the structure as shown in FIG. 7 may have a characteristic between the curve of the depletion mode characteristic of FIG. 6 and a general P-type MOS capacitor curve. The modified capacitance characteristic can be applied to sensitivity control for each pixel.

The pixel circuit 400 of FIG. 4 operates as shown in FIG. 3 except for applying a predetermined voltage to the sensitivity control signal SCG electrode for capacitance control of the MOS capacitor C _SCG . That is, when the reset control signal RX is activated in a logic high state while the row select signal SEL is activated in a logic high state, the second node FD transferred from the first power source VDD is activated. The voltage is output through the source terminal of the source follower transistor M13. The voltage output to the source terminal of M13 is output to the CDS analog-to-digital converter (see FIG. 1) as a reset signal VRES through the source terminal of M11. On the other hand, when the row selection signal SEL is active in a logic high state and the reset control signal RX is in a logic low state, an image photoelectrically converted by the diode D1 included in the optical device PD The signal VSIG is output to the analog-to-digital converter through the source terminal of M11.

At this time, according to the magnitude of the voltage applied to the sensitivity control signal (SCG), the capacitance (Cmos) of the MOS capacitor (C _SCG ) included in the optical device (PD) is determined, and the output of the image signal VSIG The gain is determined. For example, when the output voltage of the source follower transistor M13 is referred to as Vout and the gain of the source follower transistor M13 is referred to as A _SF , the output voltage Vout is related to the capacitance Cmos of the MOS capacitor C _SCG . If expressed as shown in [Equation 1]. In Equation 1, Cp is the capacitance of the diode D1, i _ph is the photoelectric conversion current of the diode D1, and T is the light accumulation time of the diode D1. i _ph × T corresponds to the amount of charge of photons due to photoelectric conversion in the diode D1. Therefore, as shown in Equation 1, the output voltage Vout of the source follower transistor M13 is the capacitance Cmos of the MOS capacitor C _SCG determined according to the magnitude of the voltage applied to the sensitivity control signal SCG. It can be seen that depends on.

[Equation 1]

On the other hand, the analog-to-digital converter for receiving a reset signal (VRES) and the image signal (VSIG) from the output (VRES / VSIG) node connected to a predetermined bias circuit (for example, 320 of Figure 3), the output reset signal ( The analog signal corresponding to the difference of the video signal VSIG with respect to the VRES is converted into a digital signal and output. The digital signal converted as described above is output to a digital signal processor (not shown) and subjected to a predetermined interpolation process. In addition, the digital signal processor generates driving signals suitable for a corresponding resolution of a display device such as an LCD to drive the display device.

A unit pixel circuit 800 of the CIS type solid-state imaging device according to another embodiment of the present invention is shown in FIG. Referring to FIG. 8, the pixel circuit 800 includes a first MOSFET M11, a second MOSFET M12, a third MOSFET M13, a fourth MOSFET M14, and an optical device PD. . The pixel circuit 800 is a circuit in which the fourth MOSFET M14 is added to the pixel circuit 400 of FIG. 4.

The first MOSFET M11 receives a row select signal SEL at its gate electrode, one side of the source / drain electrodes is connected to the first node N1, and the other side is connected to the output VRES / VSIG node. do. In the second MOSFET M12, a gate electrode receives a reset control signal RX, one of the source / drain electrodes is connected to the first power supply VDD, and the other of the second MOSFET M12 is connected to the second node FD. . In the third MOSFET M13, a gate electrode is connected to the second node FD, one side of the source / drain electrodes is connected to the first power source VDD, and the other side is the first node N1. ) Is connected. The optical device PD is connected to the third node and the sensitivity control signal SCG according to a diode D1 and a sensitivity control signal SCG for photoelectric conversion between the second power supply VSS and the third node N3. The capacitance between the electrodes has a variable MOS capacitor C _SCG . The fourth MOSFET M14 has a gate electrode receiving the transfer control signal TX, one side of the source / drain electrodes is connected to the second node FD, and the other side is connected to the third node N3. Connected.

The structure of the optical device PD in the pixel circuit 800 of FIG. 8 is the same as that of FIG. 5, and the operation of the pixel circuit 800 is similar to that of the pixel circuit 400 of FIG. 4. That is, in response to the reset control signal RX while the row select signal SEL is active, through the output VRES / VSIG node connected to a bias circuit (eg, 320 of FIG. 3). The reset signal VRES is output. At this time, unlike FIG. 4, when the reset control signal RX is in a logic high state, the transfer control signal TX is also logic high to reset the optical device PD. Has a period of time. Accordingly, the optical device PD accumulates light while the transfer control signal TX maintains a logic low state, and when the reset control signal RX becomes a logic low state, the transfer control signal TX ) Becomes a logic high state, and the photoelectrically converted signal VSIG is output from the diode D1 of the optical device PD through the output VRES / VSIG node. The capacitance of the MOS capacitor C _SCG included in the optical device PD is changed according to the sensitivity control signal SCG, and when the sensitivity control signal SCG is controlled for each pixel, the image signal for each pixel. The maximum saturation voltage of the (VSIG) output can be adjusted.

As described above, in the solid-state image pickup device according to the embodiment of the present invention, an optical device PD that simultaneously performs a variable capacitor for photoelectric conversion is used for the pixel circuit 400/800. That is, the optical device PD includes a diode D1 for photoelectric conversion and a MOS capacitor C _SCG whose capacitance is changed by the sensitivity control signal SCG electrode formed on the diode D1. Since the sensitivity control signal SCG electrode for the MOS capacitor C _SCG is formed of a transparent conductive film such as poly-silicon, the photoelectric conversion action of the diode D1 is not distorted.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, in the optical device used in the solid-state imaging device according to the present invention, since a variable capacitor is formed on the diode for photoelectric conversion, a separate area on the semiconductor substrate for the variable capacitor is not required, and the sensitivity control signal of the variable capacitor is The electrode may be made by a gate metal process which is generally used, so no additional mask or additional process is required. Thus, it can be effectively used for the adjustment of sensitivity or spectral response on a pixel-by-pixel basis in new applications such as silicon retinas or high performance image sensors.

Claims (13)

The gate electrode receives a row selection signal, one of the source / drain electrodes connected to a first node, and the other one of which is connected to an output node; The gate electrode receives a reset control signal, one of the source / drain electrodes connected to a first power supply, and the other of the gate / drain electrodes connected to a second node; A third MOSFET connected to the second node, one of the source / drain electrodes connected to the first power supply, and the other of the gate / drain electrodes connected to the first node; And And an optical device having a MOS capacitor having a variable capacitance between the second node and the sensitivity control signal electrode according to a diode and a sensitivity control signal for photoelectric conversion between a second power supply and the second node,  And a photoelectric conversion signal from the optical device and a reset signal through the output node connected to a bias circuit in response to the reset control signal when the row selection signal is active. . The pixel circuit of claim 1, wherein the MOS capacitor is formed in an upward vertical structure in a portion of the region occupied by the diode on the semiconductor substrate. The pixel circuit of claim 2, wherein the electrode receiving the sensitivity control signal from the MOS capacitor is formed of a transparent conductive film. The pixel circuit of claim 2, wherein the electrode receiving the sensitivity control signal from the MOS capacitor is formed of polysilicon. The method of claim 2, wherein the MOS capacitor, A pixel circuit of a solid state image pickup device, characterized by operating in a charge depletion mode. The method of claim 5, wherein the MOS capacitor, And a separate impurity doped region in the semiconductor substrate to operate in charge depletion mode and inversion mode. The gate electrode receives a row selection signal, one of the source / drain electrodes connected to a first node, and the other one of which is connected to an output node; The gate electrode receives a reset control signal, one of the source / drain electrodes connected to a first power supply, and the other of the gate / drain electrodes connected to a second node; A third MOSFET connected to the second node, one of the source / drain electrodes connected to the first power supply, and the other of the gate / drain electrodes connected to the first node; An optical element having a MOS capacitor having a variable capacitance between the third node and the sensitivity control signal electrode according to a diode and a sensitivity control signal for photoelectric conversion between a second power supply and a third node; And A gate electrode receives a transfer control signal, one side of the source / drain electrodes is connected to the second node, and the other side has a fourth MOSFET connected to the third node,  In response to the reset control signal while the row selection signal is active, output a reset signal through the output node connected to a bias circuit, and in the photonic device through the output node in response to the transfer control signal. A pixel circuit of a solid-state imaging device, characterized in that for outputting the converted signal. A driving method of a solid-state imaging device comprising a pixel circuit having an optical element in each pixel of an APS (Active Pixel Sensor) array, Outputting a reset signal from the pixel circuit when a reset control signal is in a first logic state; Outputting a photoelectrically converted signal from a diode included in the optical device as an image signal when the reset control signal is in a second logic state; And Converting an analog signal corresponding to the difference of the video signal with respect to the reset signal into a digital signal and outputting the digital signal; And controlling the capacitance of the MOS capacitor included in the optical device according to the sensitivity control signal to adjust the image signal output gain or the maximum size. 10. The method of claim 8, wherein the MOS capacitor is formed in an upward vertical structure in a portion of the region occupied by the diode on the semiconductor substrate. The method of claim 9, wherein the electrode receiving the sensitivity control signal from the MOS capacitor is formed of a transparent conductive film. 10. The method of claim 9, wherein the electrode receiving the sensitivity control signal from the MOS capacitor is formed of polysilicon. The method of claim 9, wherein the MOS capacitor, A solid-state imaging device driving method, characterized in that it operates in the charge depletion mode. The method of claim 12, wherein the MOS capacitor, And a separate impurity doped region in the semiconductor substrate to operate in charge depletion mode and inversion mode.

Images