KR100698083B1 - CMOS image sensor and method for manufacturing the same - Google Patents

Abstract

A CMOS image sensor and a method for manufacturing the same are provided to prevent dark current by forming transistors with different sizes on a pixel array and a blocking array. A substrate(101) defined with a pixel array and a blocking array is prepared. A first gate electrode(104a) having a gate insulating layer(103) is formed on the pixel array, and a second gate electrode(104b) having a relatively wide width is formed simultaneously on the blocking array. A photodiode region is formed in the substrate of one side of the first and the second gate electrodes. A floating diffusion region(109) is formed in the substrate of the other side of the first and the second gate electrodes.

Description

CMOS image sensor and method for manufacturing the same

1 is a block diagram showing a general CMOS image sensor

FIG. 2 is a layout illustrating one unit pixel configuring a pixel array and a blocking array of FIG. 1.

3 is a cross-sectional view illustrating each gate electrode formed in a pixel array and a blocking array of a CMOS image sensor according to the related art.

Figure 4 is a cross-sectional view showing each gate electrode formed in the pixel array and blocking array of the CMOS image sensor according to the present invention

5A through 5D are cross-sectional views illustrating a method of manufacturing a transfer transistor formed in a pixel array and a blocking array in a CMOS image sensor according to the present invention.

Explanation of symbols for the main parts of the drawings

101 semiconductor substrate 102 device isolation film

103: gate insulating film 104a, 104b: first and second gate electrodes

105: first photosensitive film 106: low concentration n ^- type diffusion region

107: insulating film sidewall 108: second photosensitive film

109: high concentration n ⁺ type diffusion region

The present invention relates to a CMOS image sensor, and more particularly to a CMOS image sensor and a method of manufacturing the same to remove the dark current to improve the characteristics of the image processor.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal, and is generally classified into a charge coupled device (CCD) and a CMOS image sensor. .

In the charge coupled device (CCD), a plurality of photo diodes (PDs) for converting a signal of light into an electrical signal are arranged in a matrix form, and the photo diodes in each vertical direction arranged in the matrix form. A plurality of vertical charge coupled device (VCCD) formed between the plurality of vertical charge coupled devices (VCCD) for vertically transferring charges generated in each photodiode, and horizontally transferring charges transferred by the respective vertical charge transfer regions; A horizontal charge coupled device (HCCD) for transmitting to the sensor and a sense amplifier (Sense Amplifier) for outputting an electrical signal by sensing the charge transmitted in the horizontal direction.

However, such a CCD has a disadvantage in that the manufacturing method is complicated because the driving method is complicated, the power consumption is large, and the multi-step photo process is required.

In addition, the charge coupling device has a disadvantage in that it is difficult to integrate a control circuit, a signal processing circuit, an analog / digital converter (A / D converter), and the like into a charge coupling device chip, which makes it difficult to miniaturize a product.

Recently, CMOS image sensors have attracted attention as next generation image sensors for overcoming the disadvantages of the charge coupled device.

The CMOS image sensor uses CMOS technology that uses a control circuit, a signal processing circuit, and the like as peripheral circuits to form MOS transistors corresponding to the number of unit pixels on a semiconductor substrate, thereby forming the MOS transistors of each unit pixel. The device adopts a switching method that sequentially detects output.

That is, the CMOS image sensor implements an image by sequentially detecting an electrical signal of each unit pixel by a switching method by forming a photodiode and a MOS transistor in the unit pixel.

The CMOS image sensor has advantages such as relatively low power consumption, a simple manufacturing process with a relatively small number of photo process steps, and the like.

In addition, since the CMOS image sensor can integrate a control circuit, a signal processing circuit, an analog / digital conversion circuit, and the like into the CMOS image sensor chip, the CMOS image sensor has an advantage of easy miniaturization.

Therefore, the CMOS image sensor is currently widely used in various application parts such as a digital still camera, a digital video camera, and the like.

1 is a block diagram illustrating a general CMOS image sensor.

As shown in FIG. 1, a general CMOS image sensor 100 includes a pixel array 110, a correlated double sampling (CDS) 120, and an analog-to-digital converter (ADC). 130, an image digital signal processor (ISP) 140, and a blocking array 150.

Here, the analog-to-digital converter 130 receives a control signal from a column decoder (not shown).

In addition, the CMOS image sensor 100 includes a control unit (not shown) for generating general timing control signals and addressing signals for selecting each pixel and outputting a sensed image signal.

In the case of the CMOS image sensor 100, a color filter is installed to receive only light of a specific color on each pixel of the pixel array 110. Place the color filter.

The most common color filter array is Bayer, where the patterns of two colors R (red) and G (green) are arranged in one row, and the patterns of two colors G (green) and B (blue) are arranged in another row. ) Has a pattern.

At this time, G (green), which is closely related to the luminance signal, is disposed in every row, and R (red) color and B (blue) color are alternately arranged in each row to increase the luminance resolution. In digital still cameras, etc., a CMOS image sensor in which many pixels of 1 million pixels or more are arranged to increase the resolution is applied.

In the CMOS image sensor 100 having the pixel structure as described above, the pixel array 110 detects light using a photo diode and converts the light into an electrical signal to generate an image signal.

The image signal output from the pixel array 110 is an analog signal of three colors of red (R), green (G), and blue (B). The analog-digital converter 130 receives an analog image signal output from the pixel array 110 and converts the analog image signal into a digital signal.

In the general CMOS image sensor 100 as shown in FIG. 1, a correlated double sampling (CDS) 120 is used to convert an image signal sensed by a photodiode into a digital signal by the analog-digital converter 130. Such a driving method is well described in the US patent, "USP5,982,318", or "USP6,067,113".

In the analog-to-digital conversion of the CDS method, after receiving the reset signal from the pixel array 110, the image signal detected by the photodiode is converted into two steps.

Each time the photodiode newly detects light at a predetermined period, before the photodiode outputs the newly detected image signal to the analog-digital converter 130, the pixel array 110 converts the analog-to-digital converter 130. Outputs a reset signal. The analog-to-digital converter 130 receives the reset signal and resets it, and then converts the video signal received from the photodiode into a digital signal and outputs the digital signal.

The digital signal converted as described above is output to the digital signal processor and subjected to a predetermined interpolation process. In addition, the subsequent digital signal processor generates drive signals suitable for the corresponding resolution of the display device such as an LCD, and drives the display device.

On the other hand, the sensitivity of the photodiode with respect to the horizontal position of the pixel array 110 appears relatively smaller in the peripheral portion than in the central portion.

Therefore, if the accumulation time of the photodiode is constant in every pixel, at the center of the pixel array 110 spatially, the photodiode constituting the pixel receives a lot of light and accumulates a lot of charge, and the more peripheral pixels, the photodiode emits light. Accepts less and accumulates relatively less charge.

In the case of displaying by the image signal output from the conventional CMOS image sensor 100, there is a problem that the center portion is bright and the peripheral portion is relatively dark on the screen of the display device.

This problem appears small in the case of the Common Intermediate format (CIF) with 352 × 288 pixels, but is severe in the case of the Super Extended Graphics Adapter (SXGA) with 1280 × 1024 pixels. Worse.

In order to eliminate the difference in brightness between the center and the peripheral portion thus displayed, it is limited to rely on the pixel design and process control of the pixel array 110, and the programmable gain amplifier in the analog-to-digital converter 130 is limited. Or a method for compensating the output signal of the analog-to-digital converter 130 in the image digital signal processor (ISP) 140 has been attempted.

In addition, the blocking array 150 is formed at the outer portion of the pixel array 110 to reduce the dark current generated at the outer portion of the pixel array 110.

FIG. 2 is a layout illustrating one unit pixel configuring a pixel array and a blocking array of FIG. 1.

As shown in FIG. 2, an active region is defined, and an isolation layer is formed at a portion except the active region. One photodiode PD is formed in a wide portion of the active region, and gate electrodes 23, 33, 43, and 53 of four transistors are formed in the active region of the remaining portion, respectively.

That is, the transfer transistor 20 is formed by the gate electrode 23, the reset transistor 30 is formed by the gate electrode 33, and the drive transistor 40 is formed by the gate electrode 43. The select transistor 50 is formed by the gate electrode 53.

Here, impurity ions are implanted into the active region of each transistor except for the lower portion of each gate electrode 23, 33, 43, 53 to form a source / drain region S / D of each transistor.

On the other hand, photodiode (PD) is a region that receives light is a very important area that should be the least damage to the process.

In addition, one of the basic principles of the image sensor is a method of processing an offset of the inevitably generated dark current so as not to process a signal for a certain amount of dark current.

In order to measure the dark current, a general method is designed to place a pixel array of a certain size outside the chip.

However, the outer edge of the chip is different from the center of the chip, and the patterning effect due to the difference in pattern density is called a loading effect.

3 is a cross-sectional view illustrating each gate electrode formed in a pixel array and a blocking array of a CMOS image sensor according to the related art.

As illustrated in FIG. 3, the gate electrodes 23a and 23b of the transmitter and the reset transistors constituting the pixel array and the blocking array have the same size (A = B), that is, the same channel length.

However, since the gate electrode formed on the blocking array is subjected to more plasma damage than the gate electrode formed on the pixel array, a dark current is generated.

That is, in general, the chip edge portion receives more plasma when forming the gate electrode than the center portion.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and the CMOS image sensor and its manufacture to improve the characteristics of the image sensor by preventing the dark current by forming the size of the transistor formed in the pixel array and the blocking array differently The purpose is to provide a method.

The CMOS image sensor according to the present invention for achieving the above object is a CMOS image sensor having a blocking array configured to control the leakage current is configured in the outer portion of the pixel array, the transistor of the blocking array is It is characterized in that it is formed larger than the transistor configured in the pixel array of the same structure as the blocking array.

In addition, the method for manufacturing a CMOS image sensor according to the present invention for achieving the above object comprises the steps of preparing a semiconductor substrate defined by a pixel array and a blocking array, the pixel array via a gate insulating film on the semiconductor substrate Forming a second gate electrode having a width greater than that of the first gate electrode in a blocking array, and forming a photodiode region in a surface of the semiconductor substrate on one side of the first and second gate electrodes. And forming a floating diffusion region in a surface of the semiconductor substrate on the other side of the first and second gate electrodes.

The CMOS image sensor of the present invention is configured to control the leakage current by considering the dark current as a kind of leakage current, and has different lengths of the gate electrodes of the blocking array and the pixel array.

That is, the CMOS image sensor of the present invention is a method of reducing the dark current in the region of the transfer transistor, the reset transistor, and the drive transistor of the blocking array in a very simple manner. .

More specifically, the size of the transistors constituting the blocking array is about 10 to 15% larger than the transistors constituting the pixel array.

In order to realize this, the present invention has a method of increasing the channel length by forming a larger width of the gate electrode formed in the blocking array than the gate electrode formed in the pixel array during the patterning process of the gate electrode at the beginning. This can be achieved by using a mask manufacturing correction method, ie OPC or MDP.

In this case, the size of each transistor may be independently controlled in consideration of device characteristics.

In addition, the possible scope of the present invention may be a method of growing each transistor by an absolutely same size, and another method of increasing the same amount, that is, a certain amount based on the size of the center transistor.

Hereinafter, a CMOS image sensor and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a cross-sectional view illustrating each gate electrode formed in a pixel array and a blocking array of the CMOS image sensor according to the present invention.

As shown in FIG. 4, gate electrodes 104a and 104b of the transmitter and reset transistors constituting the pixel array and the blocking array may include gate electrodes 104a and 104b formed in the blocking array. 5 to 20% larger than the gate electrodes 104a and 104b (A1 > B1).

5A through 5D are cross-sectional views illustrating a method of manufacturing a transfer transistor formed in a pixel array and a blocking array in a CMOS image sensor according to the present invention.

As shown in Fig. 5A, an element isolation film 102 is formed on a semiconductor substrate 101 such as single crystal silicon for inter-element isolation.

Meanwhile, an epitaxial layer (not shown) may be formed on the semiconductor substrate 101 by an epitaxial process on the semiconductor substrate 101.

Here, the epi layer forms a large and deep depletion region in the photodiode region formed later, in order to increase the ability of the low voltage photodiode to collect photoelectrons and further improve the light sensitivity.

On the other hand, the semiconductor substrate 101 may form a p-type epi layer on the n-type substrate.

Although not shown in the drawings, a method of forming the device isolation layer 102 will be described below.

First, a pad oxide film, a pad nitride film, and a TEOS (Tetra Ethyl Ortho Silicate) oxide film are sequentially formed on a semiconductor substrate, and a photoresist film is formed on the TEOS oxide film.

Subsequently, the photoresist is exposed and developed using a mask defining an active region and a device isolation region to pattern the photoresist. At this time, the photoresist of the device isolation region is removed.

The pad oxide film, the pad nitride film and the TEOS oxide film of the device isolation region are selectively removed using the patterned photoresist as a mask.

Subsequently, the semiconductor substrate in the device isolation region is etched to a predetermined depth using the patterned pad oxide film, the pad nitride film, and the TEOS oxide film as a mask to form a trench. Then, all of the photosensitive film is removed.

Subsequently, a thin sacrificial oxide film is formed on the entire surface of the substrate on which the trench is formed, and an O ₃ TEOS film is formed on the substrate to fill the trench. In this case, the sacrificial oxide film is also formed on the inner wall of the trench, and the O ₃ TEOS film proceeds at a temperature of about 1000 ° C. or more.

Subsequently, the O ₃ TEOS film is removed on the entire surface of the semiconductor substrate so as to remain only in the trench region by a chemical mechanical polishing (CMP) process to form a device isolation layer 102 in the trench. Next, the pad oxide film, the pad nitride film, and the TEOS oxide film are removed.

Subsequently, a gate insulating film 103 and a conductive layer (eg, a high concentration polycrystalline silicon layer) are sequentially deposited on the entire surface of the semiconductor substrate 101 on which the device isolation film 102 is formed.

The gate insulating film 103 may be formed by a thermal oxidation process or may be formed by a CVD method.

The conductive layer and the gate insulating layer 103 are selectively removed to form first and second gate electrodes 104a and 104b in the pixel array and the blocking array, respectively.

Here, the CD of the second gate electrode 104b formed in the blocking array is formed 5 to 20% larger than the first gate electrode 104a formed in the pixel array.

Therefore, since the CD sizes of the first and second gate electrodes 104a and 104b respectively formed in the pixel array and the blocking array are different, the channel lengths are also different, so that the voltages transmitted to the transfer transistors can be different. It can effectively control the dark current generated at.

As shown in FIG. 5B, the first photosensitive film 105 is coated on the entire surface of the semiconductor substrate 101 including the first and second gate electrodes 104a and 104b and patterned by an exposure and development process.

The photodiode region 106 is formed by implanting low concentration n ⁻ -type impurity ions into the active region of the exposed semiconductor substrate 101 using the patterned first photoresist layer 105 as a mask.

As shown in FIG. 5C, the first photosensitive film 105 is completely removed, and an insulating film is formed over the entire surface of the semiconductor substrate 101.

Here, the insulating film may be formed by laminating a nitride film or a TEOS oxide film or may be formed as a single layer.

Next, anisotropic etching (RIE) is performed on the entire surface of the insulating film to form insulating film sidewalls 107 on both side surfaces of the first and second gate electrodes 104a and 104b.

Subsequently, a second photoresist layer 108 is coated on the entire surface of the semiconductor substrate 101 on which the insulating film sidewalls 107 are formed, and patterned so that the source / drain regions of the transistors are exposed through exposure and development processes.

A high concentration n ⁺ type impurity ion is implanted into the exposed source / drain region using the patterned second photoresist layer 108 as a mask to form a source / drain impurity region.

In this case, a floating diffusion region 109, which is one of source / drain impurity regions of the transfer transistor, is formed in one active region of the first gate electrode 104a and the second gate electrode 104b.

As shown in FIG. 5D, the second photoresist film 108 is removed, and the semiconductor substrate 101 is annealed to diffuse various impurity ions implanted into the semiconductor substrate 101.

Meanwhile, in the exemplary embodiment of the present invention, the transfer transistor is described as an example, but the size of the reset transistor and the drive transistor formed in the pixel array and the blocking array may also be different.

In addition, each transistor formed in the pixel array and the blocking array may be formed in different sizes, and only one transistor may be selectively formed in the blocking array by 5 to 20% larger than the pixel array.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

CMOS image sensor and a method of manufacturing the same according to the present invention as described in detail above has the following advantages.

That is, in an image sensor having a blocking array configured at an outer portion of the pixel array to control leakage current, different sizes of transistors of the pixel array and the blocking array are formed to effectively control the dark current generated in the blocking array to effectively control the image sensor. Can improve the characteristics.

Claims (5)

A CMOS image sensor having a blocking array configured at an outer portion of a pixel array to control leakage current, And a transistor configured in the blocking array is larger than a transistor configured in the pixel array having the same structure as the blocking array. The CMOS image sensor of claim 1, wherein the transistors of the blocking array are formed 5 to 20% larger than the transistors of the pixel array. The CMOS image sensor of claim 1, wherein the transistor is at least one of a transfer transistor, a reset transistor, and a drive transistor. Preparing a semiconductor substrate defined by a pixel array and a blocking array; Forming a first gate electrode on the pixel array through a gate insulating layer on the semiconductor substrate, and simultaneously forming a second gate electrode having a width greater than that of the first gate electrode on the blocking array; Forming a photodiode region in a surface of the semiconductor substrate on one side of the first and second gate electrodes; And forming a floating diffusion region in a surface of the semiconductor substrate on the other side of the first and second gate electrodes. The method of claim 4, wherein the second gate electrode is formed to have a width that is 5 to 20% larger than that of the first gate electrode.

Images