KR20060027516A - Plasma display panel - Google Patents

Abstract

A plasma display panel according to the present invention comprises: an upper substrate; A plurality of sustain electrode pairs formed under the upper substrate; An upper dielectric layer filling the sustain electrode pairs; A lower substrate disposed to face the upper substrate; Address electrodes formed on the lower substrate so as to intersect with the storage electrode pairs; A lower dielectric layer filling the address electrodes; A main partition wall disposed between the upper substrate and the lower substrate, the main partition walls extending in parallel with the address electrode therebetween; Dummy barrier ribs each extending from the main barrier ribs, the dummy barrier ribs being respectively lowered to the outer ends in a direction extending from the portions adjacent the main barrier ribs; Phosphor layers disposed in spaces defined by the main partition walls and the dummy partition walls, respectively.

Description

Plasma display panel {Plasma display panel}

1 is a plan view of a plasma display panel according to an embodiment of the present invention;

FIG. 2 is a partially separated perspective view illustrating a part of the plasma display panel of FIG. 1; FIG.

3 is a cross-sectional view taken along the line III-III of FIG.

4 is a cross-sectional view illustrating a modification of the dummy partition wall of FIG. 3.

<Brief description of the major symbols in the drawings>

111. Upper substrate 112. Holding electrode pair

115. Upper dielectric layer 121. Lower substrate

122. Address electrode 123. Lower dielectric layer

124..Main bulkhead 125..Discharge space

126. phosphor layer 130. sealing member

140.Dummy space 141.Dummy bulkhead

The present invention relates to a plasma display panel, and more particularly, to a plasma display panel having an improved structure to ensure uniform image quality.

Recently, the plasma display panel, which is attracting attention as a substitute for the cathode ray tube, is discharged after a discharge gas is filled between two substrates on which a plurality of electrodes are formed, and a discharge voltage is applied in a predetermined pattern by ultraviolet rays generated thereby. The formed phosphor layer is excited to display an image.

Such plasma display panels are classified into DC type and AC type according to the driving method. In a DC plasma display panel, electrodes are exposed to a discharge space to directly transfer charges between corresponding electrodes. In an AC plasma display panel, at least one electrode is covered with a dielectric layer to accumulate wall charges accumulated in the dielectric layer. The discharge is caused by the movement of the wall charge.

In the DC plasma display panel, since the charge is directly transferred between the corresponding electrodes, there is a problem that the electrodes are severely damaged. In recent years, an AC plasma display panel having a three-electrode surface discharge structure has been adopted. There is a trend.

In general, the AC plasma display panel includes two main substrates that are spaced apart in parallel, and main partitions partitioning a space therebetween in a predetermined pattern, and the discharge spaces between the main partition walls are red, One of the green and blue phosphor layers is selectively disposed respectively.

The red, green, and blue phosphor layers may be formed by various methods. For example, the screen printing method prints the red, green, and blue phosphors sequentially three times. There is a problem of wasting. In order to solve such a problem, the nozzle injection method is used recently.

The nozzle spraying method is a method of forming red, green, and blue phosphor layers by simultaneously spraying red, green, and blue phosphors in a paste state into discharge spaces between main partition walls by a plurality of nozzles, respectively. Since the nozzle spraying method is unstable in the discharged amount and discharge pressure, the nozzles are sprayed in such a way that red, green, and blue phosphor layers are formed to have a uniform thickness, respectively, in order to obtain a uniform image quality of the panel. After the discharge amount and the discharge pressure are stabilized, the discharge volume is injected into the discharge spaces between the main partition walls. To this end, dummy spaces are provided at the outermost discharge spaces between the main bulkheads, so that the discharge amount and discharge pressure of the phosphor are stabilized and the phosphors having an unstable discharge amount and discharge pressure, before being injected into the discharge spaces, first. To be sprayed. The phosphor layer continuously sprayed into the dummy space and the discharge space is applied to the spaces, and the thickness and the coating area gradually increase from zero to reach the maximum value. The thickness and the coating area of the phosphor layer reach the maximum value. One point corresponds to a point in which the discharge amount, discharge pressure, etc. of the phosphor are stabilized.

However, in the structure in which the dummy bulkheads extend from the main bulkheads to the same height and form dummy spaces as in the related art, a state in which the thickness and the coating area of the phosphor layer reaches a maximum value, that is, the discharge amount and the discharge pressure of the phosphor are stabilized. There is a problem that is difficult to determine the point.

The present invention is to solve the above problems, by improving the structure of the dummy partition wall so that the discharge amount and the discharge pressure of the phosphor is stabilized, the phosphor layer can be formed to a constant thickness in the discharge spaces The purpose is to provide a plasma display panel that can obtain a uniform image quality.

Plasma display panel according to the present invention for achieving the above object,

An upper substrate;

A plurality of sustain electrode pairs formed under the upper substrate;

An upper dielectric layer filling the sustain electrode pairs;

A lower substrate disposed to face the upper substrate;

Address electrodes formed on the lower substrate so as to cross the sustain electrode pairs;

A lower dielectric layer filling the address electrodes;

A main partition wall disposed between the upper substrate and the lower substrate and extending in parallel with the address electrode therebetween;

Dummy barrier ribs extending from the main barrier ribs, the dummy barrier ribs being respectively lowered to outer ends along a direction extending from the portions adjacent to the main barrier ribs;

And phosphor layers disposed in spaces defined by the main barrier ribs and the dummy barrier ribs, respectively.

Here, the upper surface of the dummy partition wall is preferably inclined at a predetermined angle.

Here, it is preferable that the upper surface of the dummy partition wall protrudes upward and is curved.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a plasma display panel according to an exemplary embodiment of the present invention.

The illustrated plasma display panel 100 includes an upper panel 110 and a lower panel 120 that is opposite to and coupled to the upper panel 110. The common area C, which is an area where the upper panel 110 and the lower panel 120 overlap, may be roughly divided into a display area D and a non-display area N. FIG. Here, the display area D is located at the center of the common area C to correspond to the area where the image is displayed, and the non-display area N is located at the edge of the common area C to display the image. It corresponds to an area that is not displayed. In the non-display area N, a sealing member 130 such as a frit is formed to surround the display areas along an edge thereof, thereby bonding the upper panel 110 and the lower panel 120 to each other to seal the display area.

The display area D and the non-display area N will be described in more detail with reference to FIGS. 2 and 3. In FIG. 2, a partially separated perspective view of a portion of the display area and the non-display area is illustrated in FIG. 1, and FIG. 3 is a cross-sectional view taken along the line III-III of FIG. 2.

2 and 3, the upper substrate 111 is formed of a transparent glass material through which an image can pass, and the lower substrate 121 is disposed to face the upper substrate 111.

A plurality of storage electrode pairs 112 extending in one direction are disposed below the upper substrate 111, and an upper portion of the lower substrate 121 extends to cross the storage electrode pairs 112. The address electrodes 122 are disposed. The address electrodes 122 are arranged in a stripe shape on the upper surface of the lower substrate 121, and are covered by the lower dielectric layer 123 formed on the upper surface of the lower substrate 121.

In addition, the storage electrode pairs 112 are formed on the lower surface of the upper substrate 111, and each of the storage electrode pairs 112 includes a common electrode 113 and a scan electrode 114 that form a discharge gap G. The scan electrode 114 generates an address discharge together with the address electrode 122, and the common electrode 113 generates a sustain discharge together with the scan electrode 114.

As illustrated, the common electrode 113 includes a common transparent electrode 113a and a common bus electrode 113b connected to the common electrode 113, and the scan electrode 114 is a scan transparent electrode 114a and a scan connected thereto. The bus electrode 114b may be provided.

The common and scan transparent electrodes 113a and 114a are formed of indium tin oxide (ITO), which is a transparent material in order to transmit visible light generated during discharge. The common and scan bus electrodes 113b and 114b connected to the common and scan transparent electrodes 113a and 114a respectively serve to apply voltages to the common and scan transparent electrodes 113a and 114a, respectively. In order to improve the electrical resistance of the common and scan transparent electrodes 113a and 114a formed of ITO having relatively low electrical conductivity, it is preferable to be formed of a metal such as copper, silver, etc. having excellent conductivity. The common and scan bus electrodes 113b and 114b have a width smaller than that of the common and scan transparent electrodes 113a and 114a and extend in a direction crossing the address electrode 122.

The storage electrode pairs 112 are covered by the upper dielectric layer 115 formed on the lower surface of the upper substrate 111. In addition, the upper dielectric layer 115 may be covered by a protective film 116 formed of MgO or the like, wherein the protective film 116 directly impinges the upper dielectric layer 115 by collision of charged particles with the upper dielectric layer 115 during discharge. It can prevent damage, and when charged particles collide, it can release secondary electrons and play a role of increasing discharge efficiency.

The main barrier ribs 124 are formed in a predetermined pattern between the upper substrate 111 and the lower substrate 121, that is, between the passivation layer 116 and the lower dielectric layer 123, and have a stripe shape. Here, the main partitions 124 are disposed in parallel with each other between the address electrodes 122. The main partitions 124 are limited to the plurality of discharge spaces 125 and prevent cross talk between adjacent discharge spaces 125. Discharge gas is filled in the discharge spaces 125 defined by the main partitions 124, and a penning mixture gas may be employed as the discharge gas. In the discharge spaces 125, the storage electrode pairs 112 and the address electrode 122 intersect with each other, and the intersections of the storage electrode pairs 112 and the address electrode 122 cross each other. This corresponds to each of them. On the other hand, the main partition wall is not limited to the above, it may be formed in a structure that can limit the discharge space in the form of a matrix or delta.

As described above, the phosphor layer 126 is disposed in the discharge spaces 125 defined by the main partition walls 124. That is, the phosphor layer 126 is formed by applying a phosphor on the inner surface of the main partitions 124 and the upper surface of the lower dielectric layer 123. Phosphors forming the phosphor layer 126 are roughly divided into red, green, and blue phosphors whose colors emit red, green, and blue colors, respectively, so that red, green, and blue phosphors are formed. It can be roughly divided into layers 126R, 126G and 126B. The discharge spaces 125 in which the red, green, and blue phosphor layers 126R, 126G, and 126B are disposed respectively constitute red, green, and blue discharge spaces 125R, 125G, and 125B, respectively. Done. In the red, green, and blue discharge spaces 125R, 125G, and 125B configured as described above, three adjacent red, green, and blue subpixels constitute a unit pixel.

Meanwhile, the phosphor layer 126 may be formed by various methods. For example, the nozzle spray method may spray red, green, and blue phosphors in a paste state into the discharge spaces 125 by a plurality of nozzles, respectively. The red, green, and blue phosphor layers 126R, 126G, and 126B are formed to have a predetermined thickness. According to the nozzle spray method, the phosphor layer 126 is formed by spraying the phosphor paste into the discharge space 125 along the direction in which the address electrode 122 extends by at least one nozzle.

The red, green, and blue phosphor layers 126R, 126G, and 126B formed as described above should be formed to have substantially uniform thicknesses in the discharge spaces 125, respectively, to obtain a uniform image quality of the panel 100. After the discharge amount, the discharge pressure, etc. of the phosphor are stabilized, the discharge spaces 125 must be injected into the discharge spaces 125 between the main partition walls 124. Since the nozzle injection method is generally in an unstable state in which the discharge amount, discharge pressure, etc. of the initially injected phosphor are unstable, the discharge space is a buffer space in which the unstable initial state phosphor is first sprayed to reach a stabilized state. The dummy spaces 140 are provided at the outermost sides of the 125.

The phosphor layer 126 formed by the phosphors injected into the dummy space 140 and the discharge space 125 begins to form from the outermost bottom of the dummy space 140 and gradually goes toward the inside of the dummy space 140. The thickness and coating area gradually increase, and tend to reach the maximum value. Therefore, it is difficult to determine the thickness and the coating area of the phosphor layer 126 in the dummy space 140, for which the dummy partitions 141 according to an aspect of the present invention extends from the main partitions 124, respectively Each of the dummy partitions 141 has a structure in which the height gradually decreases from the portion adjacent to the main partition 124 to the outer end portion in the direction in which the dummy partition 141 extends.

That is, the dummy partition 141 is formed in a structure in which the height gradually increases from the outer end portion to the portion adjacent to the main partition 124. In this case, the dummy partition wall 141 may be formed to be closer to the site where the phosphor layer 126 is formed. As such, the dummy partition wall 141 has a structure corresponding to a tendency of increasing the thickness and the coating area of the phosphor layer 126, thereby increasing the thickness and the coating area of the phosphor layer 126 in the dummy space 140. It is easy to check whether the thickness and the coating area of the phosphor layer 126 at the point reach the maximum value.

Since the time when the thickness and the coating area of the phosphor layer 126 reaches the maximum value corresponds to the time when the discharge amount and the discharge pressure of the phosphor have stabilized, as a result, to confirm the time when the discharge amount and the discharge pressure of the phosphor have stabilized. Can be facilitated. Accordingly, the phosphor layers 126 may be formed in the discharge spaces 125 in a predetermined thickness, respectively, thereby ensuring a uniform image quality of the panel 100.

The dummy partition wall 141 that serves as described above may be formed in various shapes. As examples, as shown in FIGS. 2 and 3, the top surface of the dummy partition wall 141 is formed to be inclined at a predetermined angle. It may be formed of a structure having almost no height of the outer end, or as shown in FIG. 4, the upper surface of the dummy partition wall 141 may protrude upward and be curved. Meanwhile, the dummy partition wall 141 may be formed to have substantially the same width as the main partition wall 124, but is not limited thereto. In addition, the dummy partition wall 141 may be disposed to be spaced apart from the sealing member 130 at predetermined intervals. Accordingly, the dummy partition wall 141 may be smoothly exhausted through a space between the dummy partition wall 141 and the sealing member 130. have.

 As described above, according to the present invention, it is easy to check the time point at which the discharge amount, the discharge pressure, etc. of the phosphor is stabilized, so that the phosphor layer may be formed at a constant thickness for each discharge space between the main partition walls. Therefore, there is an effect that a uniform image quality of the panel can be obtained.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Could be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

Claims (6)

An upper substrate; A plurality of sustain electrode pairs formed under the upper substrate; An upper dielectric layer filling the sustain electrode pairs; A lower substrate disposed to face the upper substrate; Address electrodes formed on the lower substrate so as to cross the sustain electrode pairs; A lower dielectric layer filling the address electrodes; A main partition wall disposed between the upper substrate and the lower substrate and extending in parallel with the address electrode therebetween; Dummy barrier ribs extending from the main barrier ribs, the dummy barrier ribs being respectively lowered to outer ends along a direction extending from the portions adjacent to the main barrier ribs; And a phosphor layer disposed in spaces defined by the main barrier ribs and the dummy barrier ribs, respectively. The method of claim 1, And an upper surface of the dummy partition wall is inclined at a predetermined angle. The method of claim 2, And an upper surface of the dummy partition wall protrudes upward and is curved. The method of claim 1, The phosphor layer includes red, green, and blue phosphor layers, and phosphor layers having the same color are disposed along a direction in which the main partition walls extend. The method of claim 1, The dummy barrier ribs are disposed to be spaced apart from the sealing member for coupling between the upper substrate and the lower substrate. The method of claim 1, And the dummy barrier ribs are formed to have substantially the same width as the main barrier ribs.

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