KR20060027484A - Synchronous semiconductor memory device and method for read operating the same - Google Patents

Abstract

The present invention relates to a synchronous semiconductor memory device pursuing low power consumption, and the synchronous semiconductor memory device according to the present invention comprises: a memory cell array including a plurality of memory blocks including a plurality of memory cells; A word line decoder circuit for selecting at least one or more blocks of the plurality of memory blocks and enabling word lines of the selected block in response to an applied address signal; A column decoder circuit for enabling bit lines sequentially in response to an address signal applied to read data of memory cells to which the enabled word lines are connected; A sense amplifier circuit for sequentially sensing and amplifying data output from a memory cell through each of the enabled bit lines; A plurality of register circuits for storing the data sequentially output from the sense amplifier. According to the invention, it consumes less current and therefore is suitable for low power consumption memories.

Burst, Sync, Resistor, Low Power

Description

Synchronous semiconductor memory device and method for read operating the same}             

1 is a schematic block diagram of a conventional synchronous semiconductor memory device

FIG. 2 is a drive block diagram in the burst read operation of FIG.

3 is a timing diagram illustrating a read operation of FIG. 1.

4 is a schematic block diagram of a synchronous semiconductor memory device according to an embodiment of the present invention;

FIG. 5 is a drive block diagram during the read operation of FIG. 4. FIG.

6 is a timing diagram of a read operation of FIG. 4.

* Description of the symbols for the main parts of the drawings *

110: cell array region 120: wordline decoder circuit

130: bit line precharge circuit 150: column decoder circuit

160: data line precharge circuit 170: sense amplifier

180: resistor circuit

The present invention relates to a semiconductor memory device and an operation method thereof, and more particularly, to a synchronous semiconductor memory device and a read operation method thereof capable of reducing power consumption.

Recently, semiconductor memory devices have been developed in two directions, one of which is pursuing high frequency and the other of pursuing low power dissipation.

 The data read method of a semiconductor memory device can be classified into two types. One is asynchronous outputting the data of memory cells selected by the transition of an address from the outside through input / output pins (I / O) one by one without synchronization of an external clock. It is an asynchronous random access method. The other reads data stored in a plurality of memory cells in advance by the transition of the address, and then controls the input / output pins by controlling a control signal synchronized with the data to the external clock CLK. Burst method that outputs through (I / O).

Currently, many semiconductor memory devices (eg, SRAM, DRAM, flash memories, etc.) support burst read mode of operation. The burst read operation refers to sequentially reading data from a given start address in synchronization with a clock signal provided from the outside. In the burst read mode of operation, it takes a certain amount of time for the first data to be output from the memory device after the start address is given to the memory device. , Waiting time). During such latency, the sense amplification circuit senses data from the memory cells, and the sensed data is temporarily stored in a register. Thereafter, the stored data is output to the outside through the output buffer circuit in synchronization with the rising or falling edge of the clock signal.

In the case of an asynchronous or random access method in which data corresponding to a given address is output whenever an address is given from the outside, the semiconductor memory device includes sense amplifiers as many as the number of data lines. Unlike the random access method, the burst read type semiconductor memory device requires a plurality of groups of sense amplifiers because the burst data is read at a time and the read data is loaded on the data bus one group at a time. Therefore, in the case of the semiconductor memory device supporting the burst read method, the number of sense amplifiers required is determined by the number of data lines and the burst length.

While the data comes out through one burst cycle, the data of the next burst cycle can be output without delay by reading the data for the next burst cycle in the semiconductor memory device and temporarily storing the data in the data register. This operation is called a continuous burst read operation. Through the continuous burst read operation described above, the semiconductor memory device may continuously read data from an arbitrary address to the end of the address space. Therefore, continuous burst read operation makes it possible to access a continuous large amount of data at high speed.

1 is a schematic block diagram of a synchronous semiconductor memory device which performs a conventional burst read operation.

As shown in FIG. 1, the conventional synchronous semiconductor memory device includes a cell array region 10, a word line decoder 20, a column decoder 50, a bit line precharge circuit 30, and a data line free. A charge circuit 60, a sense amplifier 70, and a resistor 80 are provided.

The cell array region 10 is formed by arranging a plurality of memory cells positioned at intersections of word lines SWL0 and SWLn and bit lines BL1, BL1B, BLn, and BLnB.

The word line decoder 20 enables the word line corresponding to the address in response to the applied address signal.

The column decoder 30 enables the bit line corresponding to the address signal in response to the applied address signal.

The bit line precharge circuit 30 receives the output of the column decoder 30 to precharge the bit lines BL and BLB.

The data line precharge circuit 60 is for precharging the data lines DL and DLB in response to the data line precharge signal PDL.

The sense amplifier 70 senses amplifies and outputs data of the memory cells in response to the sense amplifier enable signal PSA.

The register 80 stores the data amplified by the sense amplifier 70 in response to the register enable signal PLA.

The non-described fast transistor circuit 40 is operated by the bit line enable signal of the column decoder 50 to connect the bit line and the data line.

FIG. 2 illustrates a driving block diagram of the synchronous 16 burst read operation of FIG. 1, and FIG. 3 illustrates an operation timing diagram of FIG. 1.

As shown in FIGS. 2 and 3, the conventional synchronous semiconductor memory device includes a sub word line decoder circuit SDEC and a main circuit configured between memory blocks BLK0 to BLK7 and the memory blocks BLK0 to BLK7. The word line decoder circuit MDEC, the sense amplifier 70, and the register 80 are provided. In FIG. 2, the hatched portions on the tops of the memory blocks BLK0 to BLK7 indicate that the word line is enabled.

In the conventional synchronous semiconductor memory device as described above, the burst read operation is an operation for reading data of a selected plurality of cells, and simultaneously activates and senses and amplifies a plurality of word lines during a latency period, and stores the cell data in a register. Data is outputted by the clock signal.

First, when the input row address signal XADD is applied, a word line enable signal is applied to the word line decoder 20 and SDEC in order to enable the designated word line W / L so that the specified word line is applied for a predetermined period. Enable it. That is, the word lines of all the blocks are all enabled by being driven simultaneously in the 16 memory blocks BLK0 to BLK7. On the other hand, when the input column address XADD is applied, the bit line enable signal Y is applied to the column decoder 50 to enable the designated bit line, and enable the column pass transistor 40 for a predetermined period. Let's do it.

  Data stored in the memory cell comes out of the cell data through the enabled bit lines BL and BLB, and inputs the sense amplifier 70 through the two cell data lines DL and DLB through the column pass transistor 40. Is entered.

The data lines DL and DLB are normally precharged in the data line precharge circuit 60 by the data line precharge signal PDL, and do not precharge during the read operation. Do not.

The sense amplifier 70 senses and amplifies the cell data by a sense amplifier enable signal PSA until it can sufficiently sense and amplify the cell data. The sense amplified data stores cell data in the register 80 by a register enable signal PLA generated by inputting the output signal of the sense amplifier 70.

The read operation of the conventional synchronous semiconductor memory device as described above is driven simultaneously in 16 blocks. As a result, all the word lines of all the blocks are enabled, resulting in large current consumption. In the case of 16 bursts, the number of enabled cells is about 8K to 16K, which means that a tremendous cell current flows. Therefore, it is difficult to cope with the current trend of low power consumption.

 Accordingly, an object of the present invention is to provide a synchronous semiconductor memory device and a read operation method thereof capable of overcoming the above-described conventional problems.

It is another object of the present invention to provide a synchronous semiconductor memory device and a read operation method thereof which seeks low power consumption by reducing operating current.

According to an aspect of the present invention for achieving some of the above technical problem, a synchronous semiconductor memory device according to the present invention comprises a memory cell array having a plurality of memory blocks having a plurality of memory cells; A word line decoder circuit for selecting at least one or more blocks of the plurality of memory blocks and enabling word lines of the selected block in response to an applied address signal; A column decoder circuit for enabling bit lines sequentially in response to an address signal applied to read data of memory cells to which the enabled word lines are connected; A sense amplifier circuit for sequentially sensing and amplifying data output from a memory cell through each of the enabled bit lines; A plurality of register circuits for storing the data sequentially output from the sense amplifier.

The synchronous semiconductor memory device may further include a bit line precharge circuit for precharging the bit line, and a plurality of register circuits may be connected to the single sense amplifier.

According to another aspect of the present invention for achieving some of the above technical problems, the read operation method of the synchronous semiconductor memory device according to the present invention, the word lines of the selected memory blocks are enabled in response to the applied address signal Steps; Disabling the bit line precharge signal while enabling the selected bit line in response to the applied address signal; Enabling bit lines sequentially with the bit line precharge signal disabled; Sensing and amplifying data sequentially output through the bit lines and sequentially storing the data in the respective registers.

According to the above apparatus and method configuration, it is possible to reduce the drive current for word line enable, which is suitable for low power consumption memory products.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, without any other intention than to provide a thorough understanding of the present invention to those skilled in the art.

4 is a schematic block diagram of a synchronous semiconductor memory device according to an embodiment of the present invention.

As shown in FIG. 4, a synchronous semiconductor memory device according to an embodiment of the present invention includes a cell array region 110, a word line decoder circuit 120, a column decoder circuit 150, and a bit line precharge circuit. A furnace 130, a data line precharge circuit 160, a sense amplifier 170, and a register circuit 180.

The cell array region 110 includes a plurality of memory blocks that include a plurality of memory cells in which data is stored.

The word line decoder 120 selects at least one or more blocks of the plurality of memory blocks and generates an enable signal for enabling word lines of the selected block in response to an applied address signal.

The column decoder circuit 150 is configured to sequentially enable the bit lines BL and BLB in response to an address signal applied to read data of memory cells to which the enabled word lines are connected. 140).

 The sense amplifier circuit 170 sequentially senses and amplifies data output from a memory cell through each of the enabled bit lines in response to the sense amplifier enable signal PSA.

The register circuit 180 is provided in plural to store data sequentially output from the sense amplifier 170. The register circuit 180 includes a plurality of registers 182, 184, 186, and 188 for one sense amplifier 170 to store data in response to each of the register enable signals PLA0, PLA1, PLA2, and PLA3. The number of registers constituting the register circuit 180 is inversely proportional to the number of the selected memory blocks.

The bit line precharge circuit 130 is for precharging the bit lines BL and BLB in response to the precharge signal PBLB. The bit line precharge circuit 130 may be configured to precharge off only selected bit lines in a conventional synchronous semiconductor memory device, and to leave the remaining unselected bit lines in a precharge state. By the charge signal PBLB, all the bit lines in the memory block are configured to be in the precharge off state.

The data line precharge circuit 160 precharges the data lines DL and DLB in response to the data line precharge signal PDL.

 FIG. 5 is a block diagram illustrating a synchronous 16 burst read operation of FIG. 4, and FIG. 6 is a timing diagram of the read operation of FIG. 4.

As shown in FIGS. 5 and 6, a conventional synchronous semiconductor memory device includes a sub word line decoder circuit SDEC and a main circuit configured between memory blocks BLK0 to BLK7 and the memory blocks BLK0 to BLK7. The word line decoder circuit MDEC, the sense amplifier 70, and the register 80 are provided. In FIG. 5, the hatched portions of the memory blocks BLK0 to BLK7 indicate that the word line is enabled. That is, it indicates that the word line of the block 200 selected for the read operation is enabled. In FIG. 5, four memory blocks are selected.

In the synchronous semiconductor memory device according to the embodiment of the present invention as described above, the burst read operation is an operation for reading data of a plurality of selected cells. The word line W / W of the selected block 200 is newly applied. L) and the selected bit lines BL and BLB are enabled.

The bit line precharge circuit 130 and the data line precharge circuit 160 are bit line free at the same time as the enable signal Y0 of the word line W / L and the first bit line BL1 and BL1B. The precharge off state is caused by the charge signal PBLB and the data line precharge signal PDL. The selection of the memory blocks BLK0 to BLK7 is configured to be at least one memory block.

Thereafter, data is output from the selected memory cell in the selected memory block 200, and is developed on the bit lines BL and BLB and transferred to the data lines DL and DLB.

The data transferred to the data lines DL and DLB is sensed and amplified by the sense amplifier 170 enabled by the sense amplifier enable signal PSA and transferred to the register circuit 180. The sense amplified data is stored in the first register 182 enabled by the register enable signal PLA0.

When data storage is completed in the first register 182, the enable signal Y0 of the first bit lines BL1 and BL1B is disabled, and the corresponding data line is precharged. On the other hand, the word line W / L remains enabled and the bit line precharge circuit 130 remains off. In this case, since the bit line is not precharged, the selected word line W / L is enabled and all the bit lines in the selected memory block 200 are kept in the data developed state.

In this state, the bit line enable signals Y1 to Y3 are sequentially enabled one by one, and the data lines DL and DLB are set to enable the precharge circuit so as to correspond thereto.

Then, the data is sequentially transmitted through the data line and sensed and amplified by the sense amplifier 170 enabled by the sense amplifier enable signal PSA. Thereafter, the sensed amplified data is sequentially stored in the second to fourth registers 184, 186, and 188.

 In the synchronous semiconductor memory device according to the embodiment of the present invention as described above, unlike 16-bit synchronous semiconductor memory device that must simultaneously drive 16 blocks in the case of 16Burst, cell data of 4 blocks in 16 words (Word) Since only 4 blocks can be driven.

Therefore, one memory block or a few memory blocks (for example, 4 blocks) is sufficiently long (Burst Length) without the need to enable a large number of memory blocks (for example, 16 blocks) to increase power consumption as in a conventional circuit. The cell data may be sensed, amplified and stored to output data according to a clock signal CLK or an address signal.

 Therefore, the present invention can sense-amplify a plurality of cell data in one selected word line or a few word lines, thereby significantly reducing the current flowing in the cell or in other circuits for driving the cell.

The description of the above embodiments is merely given by way of example with reference to the drawings for a more thorough understanding of the present invention, and should not be construed as limiting the invention. In addition, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the basic principles of the present invention. For example, it is clear that in other cases, the internal configuration of the circuit may be changed or the internal components of the circuit may be replaced with other equivalent elements.

As described above, according to the present invention, since only one or a few word lines can be enabled by reducing the number of selected memory blocks, current consumption can be considerably reduced.

Claims (4)

In a synchronous semiconductor memory device: A memory cell array including a plurality of memory blocks including a plurality of memory cells; A word line decoder circuit for selecting at least one or more blocks of the plurality of memory blocks and enabling word lines of the selected block in response to an applied address signal; A column decoder circuit for enabling bit lines sequentially in response to an address signal applied to read data of memory cells to which the enabled word lines are connected;  A sense amplifier circuit for sequentially sensing and amplifying data output from a memory cell through each of the enabled bit lines; And a plurality of register circuits for storing data sequentially output from the sense amplifiers. The method of claim 1, And the bit line precharge circuit for precharging the bit line is further included in the synchronous semiconductor memory device. The method of claim 2, And a plurality of register circuits connected to the one sense amplifier. In a read operation method of a synchronous semiconductor memory device: Enabling word lines of selected memory blocks in response to an applied address signal; Disabling the bit line precharge signal while enabling the selected bit line in response to the applied address signal; Enabling bit lines sequentially with the bit line precharge signal disabled; And sensing and amplifying the data sequentially output through the bit lines and sequentially storing the data in the respective registers.

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