KR20060026686A - Varistor and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a varistor in which EMI filter characteristics are added to a varistor having excellent surge protection and antistatic properties, and a method of manufacturing the varistor, wherein the pair of internal electrode pairs and ground electrodes including a first internal electrode and a second internal electrode are provided. A varistor portion that is alternately stacked one or more times through a varistor material layer, a laminate including a resistance layer disposed above the varistor portion and having the same number of resistance layers as the number of internal electrode pairs, one or more first external electrodes, and one The second external electrode and the ground external electrode are provided, and one end of the first internal electrode, one end of the second internal electrode, one end of the ground electrode, and both ends of the resistance layer are exposed to the outside of the laminate, and the exposed agent One end of the internal electrode and one end of the resistance layer are electrically connected by the first external electrode, and one end of the exposed second internal electrode and the other end of the resistance layer are second Unit is electrically connected by the electrode, one end of the exposed ground electrode provides a varistor and its manufacturing method which is electrically connected by the ground external electrode.

Varistors, EMI

Description

Varistor and its manufacturing method {VARISTOR AND MANUFACTURING METHOD THEREOF}

1 is an exploded perspective view of a chip varistor 1 according to an embodiment of the present invention.

2 is a perspective view of a chip varistor 1 according to an embodiment of the present invention.

3 is a circuit diagram illustrating a circuit between a pair of external electrodes 25a and 25b and ground external electrodes 30a and 30b of the chip varistor 1 according to an embodiment of the present invention.

4 is a connection diagram when the chip varistor 1 is mounted on a circuit according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

1 chip varistor 2 internal electrode layer

3: ground electrode layer 4: dummy sheet

5: resistive layer 6: resistive protective layer

7: varistor 8: capacitor

20a, 20b: first and second internal electrodes 25a, 25b: first and second external electrodes

30: ground electrode 30a, 30b: ground external electrode

The present invention relates to a varistor and a method of manufacturing the same, and more particularly, to a varistor having an EMI filter function and a method of manufacturing the same.

Electromagnetic Interference (EMI) is a phenomenon that can cause interference in the detection and interpretation of a desired signal due to unnecessary electromagnetic signals or degrades the performance of the equipment. Low pass filters are commonly used as EMI filters, by connecting resistor R and capacitor C in series with the signal source and taking the output across C. In this case, when the frequency of the signal is ω, the gain ratio expressed by 1 / √ (1+ (ω R C) ^ 2) increases in the low frequency component, while the gain decreases rapidly in the high frequency component in which the frequency ω increases. Indicates. The change of the filtered property is determined by adjusting the values of R and C.

In addition to the function of the EMI filter, the signal line of the electronic device also requires surge protection and anti-static functions to reliably prevent damage and malfunction of semiconductor components, and conventionally connects a varistor which is a separate component to the EMI filter. The chip varistor, which is a separate component from the EMI filter package, was mounted on the substrate. However, such a conventional method has a problem such as a space problem for mounting, an increase in the labor of the separate process and an increase in manufacturing cost due to the mounting of additional parts.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and adds an EMI filter characteristic to a varistor having excellent surge protection and antistatic characteristics, and has an ESD filter and EMI filter characteristics for minimizing electromagnetic interference. It is an object of the present invention to provide a varistor and a method of manufacturing the same, which can contribute to miniaturization of electronic equipment and reduction of mounting cost by simultaneously implementing a configuration having such characteristics in a plurality of arrays.

The inventors have studied chip varistors having EMI filter characteristics in order to solve the space problem in the circuit, the cost of packaging or mounting separate components by simultaneously implementing excellent withstand voltage characteristics and EMI filter characteristics. The invention has been completed.

The varistor according to the present invention includes a varistor portion in which at least one pair of inner electrode pairs including the first inner electrode and the second inner electrode and the ground electrode are alternately stacked one or more times through the varistor material layer, and above the varistor portion. One end of the first internal electrode, comprising: a laminate including a plurality of resistance layers disposed and including the same number of resistance layers as the number of internal electrode pairs, at least one first external electrode, at least one second external electrode, and a ground external electrode; One end of the second internal electrode, one end of the ground electrode, and both ends of the resistance layer are exposed to the outside of the stack, and one end of the exposed first internal electrode and one end of the resistance layer are electrically connected by the first external electrode. One end of the exposed second internal electrode and the other end of the resistance layer are electrically connected by the second external electrode, and one end of the exposed ground electrode is transferred by the ground external electrode. It is ever connected to each other.

In the varistor according to the present invention, one end of the plurality of first internal electrodes and the second internal electrodes is preferably exposed to the same surface of the stack, and the other end of the first internal electrode and the other end of the second internal electrode are spaced apart. It is more preferable to face each other.

In the varistor according to the present invention, it is preferable that one end of the ground electrode is exposed on a surface different from the exposed surface of the internal electrode in the laminate, and the resistive layer and the first and second internal electrodes overlap approximately when viewed from above. It is preferable to arrange | position to the position which becomes, and it is preferable to further provide the resistance protective layer which is arrange | positioned above the resistance layer and electrically insulates a resistance layer and a ground external electrode.

A method of manufacturing a varistor according to the present invention includes the steps of preparing a plurality of varistor material layer sheets, forming an inner electrode layer including a first inner electrode and a second inner electrode on the sheet, and forming a ground electrode layer on the sheet. Forming a varistor layer by alternately stacking the inner electrode layer and the ground electrode layer one or more times, laminating a dummy sheet on both sides of the varistor layer, and then pressing and forming a laminate, and sintering the laminate. Forming a first and a second external electrode on the outside of the laminate, the first and second external electrodes connecting the exposed portions of the first and second internal electrodes to each other in the laminate; Forming a resistance layer having both ends connected to the second external electrode, and a ground external electrode connecting the exposed portions of the ground electrode to each other in the stack; And a step of forming a.

In addition, it is preferable that the manufacturing method of the varistor which concerns on this invention further includes forming the resistance protective layer on the upper surface of the laminated body in which the resistance layer was formed.

Hereinafter, a chip varistor and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the accompanying drawings.

1 is an exploded perspective view of a chip varistor according to an embodiment of the present invention. After the layers shown in FIG. 1 are stacked, an external electrode or the like is formed as shown in FIG. 2 to form a practical chip varistor 1. Hereinafter, for the sake of simplicity, the chip varistor 1 will be referred to collectively before and after the external electrode is formed.

Referring to the layers shown in FIG. 1 in order from below, the dummy sheet 4, the ground electrode layer 3, the internal electrode layer 2, the ground electrode layer 3, the dummy sheet 4, the resistance layer 5, Resistance protective layer 6. Hereinafter, each layer will be described as being laminated, but forming another layer on the surface of one layer by printing or the like is also referred to as lamination for convenience of explanation. Here, two ground electrode layers 3 and one internal electrode layer 2 form one varistor layer. Although only one inner electrode layer 2 is shown in FIG. 1, it is apparent to those skilled in the art that a structure in which the ground electrode layer 3 and the inner electrode layer 2 are alternately stacked several times in order to set the electrical characteristics of the varistor to a predetermined value is possible. will be. It is also possible to use only one ground electrode layer 3 and one internal electrode layer 2. Hereinafter, for the sake of understanding, the configuration in which the internal electrode layer 2 is interposed between the pair of ground electrode layers 3 will be described as shown in the drawing.

The internal electrode layer 2 is formed by forming four pairs of internal electrodes 20a and 20b on a ceramic sheet (varistor material layer) mainly composed of ZnO. One end of the first internal electrode 20a faces the one end of the second internal electrode 20b, and the other ends of the first and second internal electrodes are chipped to connect with the external electrodes 25a and 25b of FIG. It is exposed to the opposite side of the varistor 1. Here, four pairs of internal electrodes are shown. According to an embodiment of the present invention, four pairs of signal lines may be connected by implementing four arrays having the same role in one chip varistor 1. It means that there is. That is, according to the number of signal lines to be connected to one chip varistor 1, the number of internal electrodes 20a and 20b (the number of resistor layers 5 may be the same) may be determined.

The ground electrode layer 3 is stacked on the upper and lower portions of the inner electrode layer 2. Similar to the internal electrode layer 2, the ground electrode layer 3 is formed by forming a ground electrode 30 on a ceramic sheet containing ZnO as a main component. The ground electrode 30 is exposed to the opposite side of the chip varistor 1 at a position which does not overlap with the exposed position of the inner electrodes 20a, 20b to connect with the ground outer electrodes 30a, 30b of FIG. have. In the present embodiment, the ground electrode 30 is exposed at two places in a direction orthogonal to the exposure direction of the internal electrodes 20a and 20b, but if it does not overlap with the exposure direction of the internal electrodes 20a and 20b, Position and number can be arbitrarily determined.

In this way, the internal electrode layer 2 and the ground electrode layer 3 are stacked to form a varistor layer. Here, the varistor function can be performed in an electrical path from each exposed portion of the internal electrodes 20a and 20b to the exposed portion of the ground electrode 30 through the ceramic sheet. At this time, the capacitor (C) is formed in the same electrical path, it is possible to implement a chip varistor having an EMI filter characteristics using this capacitor component. In other words, by connecting the resistor R to the capacitor C component of the varistor as described later, an RC circuit is formed to integrate an EMI filter that reduces noise generated during data transmission to the chip varistor. It can be formed. Here, the electrical characteristics such as the electrical characteristics of the varistor and the capacitance value of the capacitor can be set to a desired value by adjusting the distance between the electrodes, the electrode area, and the number of stacks. On the other hand, the dummy sheet 4 is stacked on the upper and lower portions of the varistor layer in which the internal electrode layer 2 and the ground electrode layer 3 are stacked one or more times. The number of stacks and the thickness of the dummy sheet 4 can be appropriately adjusted according to the embodiment.

Four resistive layers 5 are stacked on the upper dummy sheet 4 in parallel with the internal electrodes 20a and 20b. As described above, although four pairs of configurations having the same role are implemented in the embodiment of FIG. 1, the number of resistance layers 5 to be stacked is determined according to the number of internal electrodes 20a and 20b. Both ends of the resistive layer 5 are exposed to opposite sides of the chip varistor 1 at the same positions as the exposed positions of the internal electrodes 20a and 20b, respectively, in order to connect with the external electrodes 25a and 25b of FIG. have. In addition, a resistive protective layer 6 for insulation or the like is laminated on the resistive layer 5.

2 is a perspective view of a chip varistor according to an embodiment of the present invention. As shown in Fig. 1, four layers of external electrodes 25a and 25b for connection with an external circuit and a pair of ground externals for connection to ground are provided in the chip varistor 1 in which each layer is stacked. Electrodes 30a and 30b are formed. As can be seen from the above description, the first inner electrode 20a of the inner electrode layer 2 is connected to the first outer electrode 25a, and the inner electrode layer 2 of the second outer electrode 25b is connected to the first outer electrode 25a. The second internal electrode 20b is connected. In addition, the both ends of the resistance layer 5 are connected to the 1st external electrode 25a and the 2nd external electrode 25b, respectively. 3 shows a circuit diagram formed between the pair of external electrodes 25a and 25b and the ground external electrodes 30a and 30b.

As can be seen in FIG. 3, a resistor 5 ′ formed by the resistive layer 5 is interposed between the external electrodes 25a and 25b, and the respective external electrodes 25a and 25b and the ground external electrode are interposed. The varistor 7 and the capacitor 8 which are formed by the internal electrode layer 2 and the ground electrode layer 3 are interposed between 30a and 30b. Therefore, it can be seen that the varistor 7 having the withstand voltage characteristic and the RC circuits 5 'and 8 having the EMI filter characteristic are simultaneously implemented in the chip varistor 1. In addition, a varistor 7 and a capacitor 8 are formed between the external electrodes 25a and 25b and the ground, respectively. That is, two varistors 7 and a capacitor 8 are symmetrically formed between the pair of external electrodes 25a and 25b, and thus there is no directivity in the connection between the chip varistor 1 and the signal line. It also has an effect.

4 is a connection diagram when a chip varistor is mounted on a circuit according to an embodiment of the present invention. Signal lines are connected to the four pairs of external terminals 25a and 25b of the chip varistor 1, and ground terminals are connected to the pair of ground external electrodes 30a and 30b. As can be seen here, the chip varistor 1 according to the present invention is implemented as four arrays of varistors having EMI filter characteristics in one chip varistor.

Hereinafter to provide a preferred embodiment of the method of manufacturing a chip varistor to help the understanding of the present invention. The following examples are provided to more easily understand the present invention, and the present invention is not limited by these examples.

A method of manufacturing the chip varistor according to the present embodiment will be described with reference to FIGS. 1 and 2.

First, a powder is obtained by mixing ZnO as a main raw material, a binder, and a solvent to obtain a slurry, and a plurality of sheets having a thickness of 10 to 60 µm are produced by a tape casting method using a doctor blade. Then, the internal electrode layers (by printing the internal electrodes 20a and 20b by screen printing) on a sheet of metal paste mixed with palladium, platinum, copper, etc. on one sheet in the pattern shown in the internal electrode layer 2 of FIG. 2) form. Further, the ground electrode layer 3 is formed by printing the ground electrode 30 on the other sheet by the screen printing method with a metal paste mixed with palladium, platinum, copper, and the like in the pattern shown in the ground electrode layer 3 of FIG. Form.

Then, the inner electrode layer 2 sheet on which the inner electrodes 20a and 20b are printed, and the ground electrode layer 3 sheet on which the ground electrode 30 is printed are alternately stacked to form a varistor layer, and on both sides of the stacked layers. The dummy sheets 4 are laminated to have a total thickness of 200 to 2000 µm, and then pressed at a pressure of 50 to 500 MPa to form a laminate. At this time, the number of laminations of the inner electrode layer 2 sheet and the ground electrode layer 3 sheet can be appropriately adjusted according to the desired electrical characteristics of the varistor as described above. Next, a plurality of green chips are manufactured by cutting the compressed laminate into a rectangular shape having a predetermined dimension. The green chip is degreased at 200 to 600 ° C. and then sintered at a temperature of 800 to 1400 ° C. for 10 to 180 minutes to produce a varistor having desired electrical characteristics.

Next, the external electrodes 25a and 25b are formed by connecting the exposed portions of the internal electrodes 20a and 20b to each other by using a silver-based paste on a part of the side, top and bottom surfaces of the varistor, and forming a 500 to 900 ° C. Be quenched in degree. Then, using the resist paste whose main material is Ru, the resistive layer 5 is formed in the pattern shown in FIG. 1 between the first external electrode 25a and the second external electrode 25b on the varistor upper surface, Heat treatment between 100 ~ 700 ℃. Here, it is possible to set a desired resistance value by adjusting the heat treatment temperature with the change of the thickness, area, etc. of the resistance layer 5.

In order to insulate the resistive layer 5 from the ground external electrodes 30a and 30b formed thereafter, the resistive protective layer 6 is made of epoxy, silicon, polymer, or the like on the upper surface of the varistor on which the resistive layer 5 is formed. ) And then hardened by heat treatment at 100 ~ 400 ℃. Next, the ground external electrodes 30a and 30b are formed by connecting the exposed portions of the ground electrodes 3 to each other using a curing paste composed mainly of silver, and then cured by heat treatment at 100 to 400 캜. The chip varistor 1 according to the invention is completed through a coating and a series of plating processes.

It is to be understood that the present invention is not limited to the above-described exemplary preferred embodiments but may be embodied in various ways without departing from the spirit and scope of the present invention. If you grow up, you can easily understand. If the implementation by such improvement, change, replacement or addition falls within the scope of the appended claims, the technical idea should also be regarded as belonging to the present invention.

      According to the varistor manufactured according to the varistor of the present invention and the method of manufacturing the same, an EMI filter characteristic is added to a varistor having excellent surge protection and antistatic characteristics, and thus the EMI filter characteristic of minimizing the withstand voltage characteristics and the electromagnetic interference is one. Since the device can be implemented as a large number of arrays, the electronic device can be miniaturized and the mounting cost can be reduced. Therefore, the electronic device can be widely used in electronics and communication fields that require both withstand voltage characteristics and EMI filter functions.

Claims (8)

A pair of at least one inner electrode pair and a ground electrode including a first inner electrode and a second inner electrode and a varistor portion alternately stacked one or more times through a varistor material layer, and disposed above the varistor portion and having the inner electrode pair A laminate comprising a resistive layer equal to the number of At least one first external electrode, At least one second external electrode, With a ground external electrode, One end of the first internal electrode, one end of the second internal electrode, one end of the ground electrode, and both ends of the resistance layer are exposed to the outside of the laminate, One end of the exposed first internal electrode and one end of the resistance layer are electrically connected by the first external electrode, One end of the exposed second internal electrode and the other end of the resistance layer are electrically connected by the second external electrode, One end of the exposed ground electrode is electrically connected by the ground external electrode. The method of claim 1, One end of each of the plurality of first internal electrodes and the second internal electrode is exposed to the same surface of the laminate, respectively. The method of claim 2, The other end of the first internal electrode and the other end of the second internal electrode are opposed to each other with a gap. The method of claim 1, One end of the ground electrode is exposed to a surface different from the exposed surface of the internal electrode in the laminate. The method of claim 1, And the resistive layer and the first and second internal electrodes are disposed at substantially overlapping positions when viewed from above. The method of claim 1, And a resistive protection layer disposed above the resistive layer to electrically insulate the resistive layer and the ground external electrode. Preparing a plurality of varistor material layer sheets, Forming an inner electrode layer on the sheet, the inner electrode layer including a first inner electrode and a second inner electrode; Forming a ground electrode layer on the sheet; Forming a varistor layer by alternately stacking the inner electrode layer and the ground electrode layer one or more times; Stacking the dummy sheets on both sides of the varistor layer and then pressing them to form a laminate; Sintering the laminate; Forming first and second external electrodes on the outside of the laminate to connect portions of the laminate to which the first and second internal electrodes are exposed; Forming a resistance layer having both ends connected to a first external electrode and a second external electrode on an upper surface of the laminate; And forming a ground external electrode on the outside of the stack, which connects portions of the stack exposed by the ground electrodes to each other. The method of claim 7, wherein And forming a resistance protective layer on an upper surface of the laminate in which the resistance layer is formed.

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