KR20060019491A - Methods of fabricating a mim capacitor employing a metal nitride layer as a lower electrode - Google Patents

Abstract

Provided are a method of fabricating an M capacitor using a metal nitride film as a lower electrode. The methods include forming an insulating film on a semiconductor substrate. A metal source gas and a nitride gas are supplied onto the insulating film to deposit metal nitride. A nitrogen-containing flushing gas is supplied onto the metal nitride to enhance nitriding. In addition to the supply of the metal source gas and the nitride gas, the supply of the flushing gas is repeatedly performed alternately at least once to form a metal nitride film.

Nitriding Flushing, Molding Film, Lower Electrode, Wet Etching, SFD, CVD

Description

Methods of fabricating a MIM capacitor employing a metal nitride layer as a lower electrode}

1A through 1F are cross-sectional views sequentially illustrating a method of manufacturing an M capacitor according to the present invention.

2 is a timing diagram illustrating a method of forming a lower electrode of an M capacitor according to the present invention.

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing an IC capacitor.

In general, a semiconductor memory device, particularly a dynamic random access memory (DRAM), is a memory device that stores data in a capacitor of a unit cell. That is, the unit cell of the DRAM is composed of one access transistor and one cell capacitor connected in series.

As the cell capacitor, a metal-insulator-silicon (MIS) structure has been conventionally applied. As the capacitor of the MIS structure, a polysilicon electrode is used as a storage electrode which is a lower electrode. And a metal electrode is used as a plate electrode which is an upper electrode. A dielectric layer is disposed between the storage electrode and the plate electrode. However, in the case of the MIS structure, an oxidation reaction occurs at an interface between the polysilicon electrode and the dielectric layer, thereby changing electrical characteristics. In addition, depending on the magnitude of the voltage applied to the metal plate electrode, the capacitor exhibits an uneven capacitance. For example, when the polysilicon storage node electrode is doped with n-type impurities and a negative voltage is applied to the metal plate electrode, holes are induced on the surface of the polysilicon storage node electrode. That is, a depletion layer may be formed on the surface of the lower electrode, and the width of the depletion layer changes according to the magnitude of the negative voltage. As a result, the capacitance of the capacitor is not constant and changes depending on the magnitude of the voltage applied to the electrodes. As a result, the capacitor of the MIS structure is unsuitable for semiconductor devices requiring sophisticated characteristics.

In addition, when the design rule of DRAM devices is reduced, it is difficult to increase cell capacitance within a limited area. In order to increase the cell capacity, there are a method of increasing the height of a cell capacitor and a method of reducing an equivalent oxide thickness (Toexq) of a dielectric film. If the design rule is 100 nm or less, there may be a limit to increasing the height of the cell capacitor to be larger than 2.0 μm. Therefore, in order to implement a cell capacitor suitable for a highly integrated DRAM (DRAM) device, it is required to reduce the equivalent oxide thickness of the dielectric film of the cell capacitor. In a capacitor having a conventional MIS (Metal / Insulator / Polysilicon) structure, there is a limitation in forming a dielectric film having an equivalent oxide film thickness of less than about 20 mW.

In order to solve the above-mentioned problems, a MIM structure in which both the upper electrode and the lower electrode are formed of a metal layer has recently been applied. In particular, a technique of forming the lower electrode with a titanium nitride film (TiN) has been applied to the MIM capacitor. The lower electrode formed of the titanium nitride film has a low specific resistance and excellent electrical reliability because it suppresses parasitic capacitance caused by the depletion layer. In addition, since the titanium nitride film has strong oxidation resistance, formation of a native oxide layer on the titanium nitride film can be suppressed. Therefore, it may be easy to reduce the equivalent oxide film thickness of the dielectric film formed on the titanium nitride film. Accordingly, research on the metal / insulator / metal (MIM) capacitor has been continuously conducted, and the titanium nitride film TiN is widely used as the lower electrode.

However, as the lower electrode material is changed to a titanium nitride film (TiN) instead of a polysilicon film, contact resistance increases at a lower electrode made of a titanium nitride film (TiN) and a polysilicon plug interface disposed thereunder, thereby operating characteristics of the device. Is lowered. In order to improve such contact resistance, a method of forming a titanium silicide layer (TiSi2), which is an ohmic contact layer, on the upper surface of the polysilicon plug is applied.

After forming a titanium silicide layer on the upper surface of the polysilicon plug, a method of forming a lower electrode made of a metal layer has been disclosed in Korean Patent Publication No. 2002-84596 entitled “Capacitor Manufacturing Method”.

As disclosed in Korean Laid-Open Patent Publication No. 2002-84596, an etch stop film and a molding insulating film are sequentially formed on a substrate having a polysilicon plug penetrating an interlayer insulating film, and the patterned insulating film and the etch stop film are patterned to form the polysilicon. A capacitor hole is formed to expose the plug. A titanium film is formed on the entire surface of the substrate having the capacitor hole, and a titanium silicide film is formed on the surface of the polysilicon plug. The unreacted titanium film remaining on the surface of the molding insulating film is removed, and the titanium silicide film is exposed to ammonia (NH 3) plasma. As a result, a nitrided titanium silicide film (Ti-Si-N) is formed on the surface of the titanium silicide film. A titanium nitride film and a sacrificial film are sequentially formed on the substrate having the nitrided titanium silicide film. The sacrificial layer and the titanium nitride layer are planarized to form a titanium nitride layer pattern, that is, a lower electrode, in the capacitor hole. Subsequently, the molding insulating layer and the sacrificial layer are removed to expose the inner and outer walls of the lower electrode.

In the method of manufacturing a capacitor disclosed in Korean Patent Laid-Open Publication No. 2002-84596, an etching solution is formed on the lower electrode and the etch stop layer while removing the molding insulating layer and the sacrificial layer to expose the inner and outer walls of the lower electrode. The interlayer insulating layer may be further etched by penetrating through an interface between a stopper (Si 3 N 4). As a result, through holes may be formed in the interlayer insulating film. As a result, the through-holes in the interlayer insulating film may act as defects to reduce the yield of the semiconductor device.

In particular, in the case where the titanium nitride film is formed by using a chemical vapor deposition (CVD) technique, the productivity is improved, but through holes may be formed in the interlayer insulating film as described above. In addition, since the chemical vapor deposition titanium nitride film (CVD-TiN) film is formed by the continuous reaction of titanium tetrachloride (TiCl 4) gas and ammonia (NH 3) gas, the chlorine content in the CVD-TiN film may be high. . In this case, the chlorine atoms may cause cracking of the CVD-TiN film.

The technical problem to be achieved by the present invention is to completely nitride the unreacted metal film remaining after forming the metal silicide film serving as the ohmic contact layer to prevent the formation of etching defects by the unreacted titanium film To provide a method of forming a.

Another object of the present invention is to provide a method of manufacturing a MIM capacitor capable of minimizing chlorine content in an electrode formed of a metal nitride film and improving productivity.

One aspect of the present invention for solving the above technical problem provides a method of forming a metal nitride film. The method of forming the metal nitride film includes forming an insulating film on a semiconductor substrate. A metal source gas and a nitride gas are supplied onto the insulating layer to deposit metal nitride. A nitrogen-containing flushing gas is supplied onto the metal nitride to enhance nitriding. Subsequently, the supply of the flushing gas as well as the supply of the metal source gas and the nitriding gas are repeatedly performed alternately at least once. As a result, a sequential flow deposition (SFD) metal nitride film is formed on the insulating film.

In some embodiments of the present invention, the metal source gas may be a gas containing titanium, tungsten or tantalum. The gas containing titanium may be titanium tetrachloride (TiCl 4) gas.

In other embodiments, the nitriding gas may be nitrogen gas or ammonia (NH 3) gas.

In still other embodiments, the flushing gas may be nitrogen gas or ammonia (NH 3) gas.

In still other embodiments, a purge gas may be supplied onto the semiconductor substrate after deposition of the metal nitride. In addition, a purge gas may be supplied onto the semiconductor substrate after the nitriding reaction is enhanced. The purge gas may be an inert gas. The inert gas may be nitrogen gas.

In still other embodiments, a chemical vapor deposition (CVD) metal nitride layer may be further formed on the sequential flow deposition (SFD) metal nitride layer. The chemical vapor deposition metal nitride film may be formed by the continuous reaction of the metal source gas and the nitride gas without supply of the flushing gas. According to another aspect of the present invention, there is provided a method of manufacturing an IC capacitor do. The method includes forming an interlayer insulating film on a semiconductor substrate and forming a polysilicon contact plug penetrating the interlayer insulating film. A molding layer is formed on the contact plug and the interlayer insulating layer, and the molding layer is patterned to form a storage node hole exposing the contact plug. An ohmic contact layer is formed on an upper surface of the contact plug. The metal nitride is deposited by supplying a metal source gas and a nitride gas on the substrate having the ohmic contact layer. A flushing gas containing nitrogen is supplied onto the substrate having the metal nitride to strengthen the nitriding reaction of the metal film remaining under the metal nitride. Subsequently, the supply of the flushing gas as well as the supply of the metal source gas and the nitride gas are repeatedly performed at least once alternately to form a lower electrode film made of a metal nitride film. As a result, a sequential flow deposition (SFD) metal nitride film is formed on the substrate having the ohmic contact layer.

In some embodiments of the present disclosure, forming the ohmic contact layer may include depositing a metal film on the substrate having the storage node hole. During the deposition of the metal layer, the contact plug may react with the metal layer to form a metal silicide layer.

In other embodiments, the metal source gas may be a gas containing titanium, tungsten or tantalum. The titanium-containing gas may be titanium tetrachloride (TiCl 4) gas, and the nitriding gas may be ammonia (NH 3) gas or nitrogen gas. In this case, the metal nitride may be titanium nitride. The titanium nitride may be deposited to a thickness of 150 ~ 350Å.

In still other embodiments, the flushing gas may be an NH 3 gas or an N 2 gas.

In still other embodiments, a purge gas may be supplied after the supply of the metal source gas and the nitriding gas. In addition, a purge gas may be supplied after the supply of the flushing gas. The purge gas may be nitrogen gas.

In still other embodiments, a chemical vapor deposition (CVD) metal nitride layer may be further formed on the sequential flow deposition (SFD) metal nitride layer. The chemical vapor deposition metal nitride film may be formed by continuous reaction of the metal source gas and the nitride gas without supply of the flushing gas.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

1A to 1F are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device having an M capacitor according to embodiments of the present invention, and FIG. 2 is a method of forming a lower electrode of an M capacitor according to the present invention. This is a timing diagram for explaining.

Referring to FIG. 1A, an isolation layer (not shown) is formed on the semiconductor substrate 100. The device isolation layer (not shown) may proceed in a conventional shallow trench isolation (STI) process. An active region is defined by the device isolation layer (not shown). A gate insulating layer 102 and a gate conductive layer are sequentially formed on the semiconductor substrate on which the device isolation layer (not shown) is formed. The gate conductive layer may be formed of a refractory metal polycide layer. More specifically, the gate conductive layer may be formed by sequentially stacking a polysilicon layer and a tungsten silicide layer. The gate conductive layer is patterned to form a gate electrode 108. As a result, the gate electrode 108 may be formed to have the polysilicon pattern 104 and the tungsten silicide pattern 106 sequentially stacked.

The impurity ions are implanted into the active region using the gate electrode 108 as an ion implantation mask to form low concentration impurity regions 110. The insulating film spacer 112 is formed on the sidewall of the gate electrode 108 using a conventional method. Impurity ions are implanted into the active region using the insulating layer spacer 112 and the gate electrode 108 as an ion implantation mask to form high concentration impurity regions 114 having a higher concentration than the low concentration impurity region 110. do. The low concentration impurity region 110 and the high concentration impurity region 114 constitute an LED-type source / drain regions 116, and the source / drain regions 116 and the gate electrode 108 are MOS transistors. Configure

Referring to FIG. 1B, an interlayer insulating layer 118 is formed on a substrate having the source / drain regions 116. The interlayer insulating layer 118 is patterned to form a contact hole 120 exposing any one of the source / drain regions 116. A conductive film is formed on the interlayer insulating film 118 to fill the contact hole 120. The conductive film is planarized using a chemical mechanical polishing process or the like to expose an upper surface of the interlayer insulating film 118. Accordingly, the contact plug 122 is formed in the contact hole 120. The contact plug 122 may be formed of a polysilicon film.

An etch stop layer 124 is formed on the contact plug 122 and the interlayer insulating layer 118. The etch stop layer 124 may be formed of a silicon oxynitride layer (SiON) or a silicon nitride layer (SiN).

Referring to FIG. 1C, a molding layer 126 is formed on the etch stop layer 124. The molding layer 126 may be formed of a material layer having an etching selectivity with respect to the etch stop layer 124. For example, the molding layer 126 may be formed of a silicon oxide layer such as a plasma enhanced tetraethylorthosilicate (PE-TEOS) layer, a BPSG layer, or a PSG layer. The molding layer 126 and the etch stop layer 124 are patterned to form a storage node hole 128 exposing the contact plug 122.

A titanium film is formed on the substrate having the storage node hole 128. The titanium film may be deposited to a thickness of about 85 kV using chemical vapor deposition (CVD) technology. The titanium silicide layer 130 may be formed on the surface of the contact plug 122 during the deposition of the titanium layer. The titanium silicide layer 130 is formed by mutual reaction between the titanium layer and the contact plug 122. The titanium silicide layer 130 serves as an ohmic contact layer to improve contact resistance between the contact plug 122 and a lower electrode formed in a subsequent process. The titanium silicide layer 130 may be formed by a heat treatment process performed under an ammonia plasma (NH 3 plasma) atmosphere after the titanium layer is formed. The unreacted titanium film remaining on the surface of the molding film may be nitrided during the heat treatment process.

Referring to FIG. 1D, a lower electrode layer 152 is formed on a semiconductor substrate having the titanium silicide layer 130. The lower electrode layer 152 may be formed of a metal nitride layer, for example, a titanium nitride layer, a tantalum nitride layer, or a tungsten nitride layer. The lower electrode layer 152 may be formed by sequentially stacking the first lower electrode layer 132 and the second lower electrode layer 151. The first lower electrode layer 132 may be formed using a sequential flow deposition (SFD) technique, and the second lower electrode layer 151 may be formed using chemical vapor deposition (CVD). can do. In this case, the first and second lower electrode films 132 and 151 may be formed to have a total thickness of 200 to 300 Å. For example, the first lower electrode film 132 may be formed to a thickness of 70 to 200 kPa, and the second lower electrode film 151 may also be formed to a thickness of 70 to 200 kPa. Alternatively, the lower electrode layer 152 may be formed of only the first lower electrode layer 132. That is, the process of forming the second lower electrode layer 151 may be omitted. In this case, the first lower electrode layer 132 may be formed to a thickness of 150 ~ 350Å.

Meanwhile, the chemical vapor deposition process for forming the second lower electrode film 151 may be continuously performed in a chamber in which the sequential flow deposition process for forming the first lower electrode film 132 is performed. have. That is, the first and second lower electrode films 132 and 151 may be formed using an in-situ method. In addition, the first and second lower electrode layers 132 and 151 may be formed at the same temperature. Alternatively, the first and second lower electrode films 132 and 151 may be formed in two different chambers, respectively. However, the first and second lower electrode films 132 and 151 are preferably formed using an in-situ method from the viewpoint of productivity. Before forming the lower electrode film 152, the molding film is formed. Unreacted metal film (eg, unreacted titanium film) remaining on the surface of 126 can be removed using a conventional wet etching process. The titanium film remaining after the wet etching process may be plasma-treated using a gas containing nitrogen. The nitrogen plasma process may be performed for 80 seconds using NH 3 gas or N 2 gas.

In other embodiments of the present invention, the titanium film for forming the titanium silicide film 130 and the metal nitride film for forming the lower electrode film 152 may be continuously formed using an in situ process.

The first lower electrode layer 132 may be formed of a titanium nitride layer using the sequential flow deposition (SFD) technique. In this case, the method of forming the first lower electrode layer 132 will be described in more detail with reference to the timing diagram of FIG. 2.

First, a semiconductor substrate having the titanium silicide layer 130 is loaded into a reaction chamber. A metal nitride is deposited on the semiconductor substrate by injecting a metal source gas and a nitride gas into the reaction chamber loaded with the semiconductor substrate for a first time T1 (first step). The metal source gas uses TiCl 4 and is supplied at a flow rate of 5 to 50 sccm. The nitriding gas injection may be performed using NH 3 or N 2 gas. In this case, the nitriding gas may be supplied at a flow rate of 10 to 50 sccm. While the metal source gas and the nitride gas are injected, the inside of the reaction chamber may maintain a pressure of 1 to 5 Torr and a temperature of 550 to 800 ° C. Accordingly, titanium nitride (the metal nitride) is deposited on an inner wall of the storage node hole 128 and an upper surface of the molding layer 126.

Subsequently, the unreacted metal source gas and the nitride gas remaining in the reaction chamber for the second time T2 may be purged (second step). The purge process may be carried out using an inert gas, for example nitrogen (N 2) gas.

After the purge process, a gas such as ammonia (NH 3) is injected into the reaction chamber for a third time T3 to perform a nitriding flushing process (third step). The nitriding flushing process is preferably performed for at least 5 seconds. The internal temperature of the reaction chamber during the nitriding flushing process may be 500 ~ 650 ℃. Usually, the nitriding flushing process may be performed using an in-situ manner at the same temperature as that of the first step.

Although the unreacted titanium film remains on the inner wall of the storage node hole 128 after the titanium silicide film 130 is formed, the unreacted titanium film may be nitrided by the nitriding flushing process. After the nitriding flushing process, the nitriding gas remaining in the reaction chamber may be purged for a fourth time T4 (fourth step).

The one process cycle consisting of the first to fourth steps is repeated at least twice. This is to completely nitride the unreacted titanium film remaining in the storage node hole by repeatedly performing the nitriding flushing process while forming the titanium nitride film. The single process cycle may run for 10 seconds. During the single process cycle, the titanium nitride film may be formed to a thickness of 20 to 25 kPa. The purge process of at least one of the purge processes (second and fourth steps) may be omitted during the single process cycle.

As a result, at least the first lower electrode layer 132 may be formed by repeatedly performing the single process cycle several times to completely nitride the titanium film remaining on the surface of the molding film. Therefore, it is possible to prevent the etching defect caused by the wet etching solution from being removed during the molding film and the sacrificial film in a subsequent process. In addition, when at least the first lower electrode film 132 is formed using the sequential flow deposition technique, the chlorine content in the lower electrode film 152 including the first lower electrode film 132 may be adjusted. It can be minimized. Accordingly, the lower electrode layer 152 may be prevented from being cracked.

In another embodiment of the present invention, the first lower electrode film 132 may be formed using an atomic layer deposition technique. The nitride flushing process is repeatedly performed at least twice while the first lower electrode film 132 is formed using the atomic layer deposition technique.

The chemical vapor deposition process for forming the second lower electrode layer 151 may be formed by continuous reaction of the metal source gas and the nitride gas without using the flushing gas. Therefore, when the lower electrode film 152 is formed by sequentially stacking the first and second lower electrode films 132 and 151, the lower electrode film 152 is formed only by the first lower electrode film 132. Productivity can be improved as compared to the case formed.

According to the embodiments described above, the nitride flushing process is repeatedly performed at least twice while the lower electrode film (metal nitride film) 152 is formed. Therefore, the titanium film remaining in the storage node hole 128 can be efficiently nitrided.

Referring back to FIG. 1D, a sacrificial layer 133 filling the storage node hole 128 is formed on the lower electrode layer 152. The sacrificial layer 133 may be formed of the same material layer as the molding layer 126.

Referring to FIG. 1E, the sacrificial layer 133 and the lower electrode layer 152 are planarized using a chemical mechanical polishing process or a dry etch back process to expose the top surface of the molding layer 126. As a result, an isolated storage node, that is, a lower electrode 152a is formed in the storage node hole 128. In addition, a sacrificial layer pattern (not shown) may remain in a space surrounded by the lower electrode 152a.

When the lower electrode layer 152 is formed by sequentially stacking the first and second lower electrode layers 132 and 151, the lower electrode 152a is formed of the first lower electrode 132a and the first electrode. The second lower electrode 151a may be formed to cover the inner wall of the lower electrode 132a. Alternatively, when the process of forming the second lower electrode film 151 is omitted, the lower electrode 152a may be formed to have only the first lower electrode 132a.

After the lower electrode 152a is formed, the molding layer 126 and the sacrificial layer pattern are removed to expose an inner wall and an outer sidewall of the lower electrode 152a. The molding layer 126 and the sacrificial layer pattern may be removed using a wet etching solution such as a hydrofluoric acid solution. The wet etching solution may not penetrate into the interlayer insulating layer 118 while the molding layer 126 is removed. This is because no titanium film exists at the interface between the first lower electrode 132a and the etch stop layer 124. Therefore, it is possible to prevent the formation of an etching defect in the interlayer insulating layer 118.

Referring to FIG. 1F, a dielectric film 134 and an upper electrode 136 covering the surface of the lower electrode 152a are sequentially formed on the semiconductor substrate from which the molding layer 126 is removed. Before forming the dielectric layer 134, the etch stop layer 124 may be selectively removed. The dielectric layer 134 may be formed of a high dielectric layer such as hafnium oxide (HfO 2), aluminum oxide (Al 2 O 3), tantalum oxide (Ta 3 O 5), lanthanum oxide (La 2 O 3), or zirconium oxide (ZrO 2). In order to improve the characteristics of the dielectric layer 134, the dielectric layer 134 may be heat treated or a plasma treatment may be performed. The upper electrode 136 may be formed of a metal film such as a titanium film, a tungsten film, a tantalum film, a titanium nitride film, a tungsten nitride film, or a tantalum nitride film.

According to the present invention described above, at least two nitriding flushing steps are repeatedly performed during the formation of the metal nitride film as the lower electrode film covering the inner wall of the storage node hole passing through the molding film. As a result, even though an unreacted metal film remains in the storage node hole, the unreacted metal film can be completely nitrided during the nitriding flushing step. Accordingly, while the molding layer is removed using the wet etching solution, the wet etching solution may be prevented from penetrating into the interlayer insulating layer through an interface between the lower electrode and the etching stop layer.

In addition, according to the present invention, the lower electrode film can be formed using at least a sequential flow deposition process and a chemical vapor deposition process. As a result, cracking of the lower electrode layer can be prevented and productivity of the semiconductor device including the lower electrode can be improved.

Claims (27)

Forming an insulating film on the semiconductor substrate; Supplying a metal source gas and a nitride gas onto the insulating film to deposit metal nitride; Supplying a nitrogen-containing flushing gas onto the metal nitride to enhance nitriding; And repeatedly supplying the flushing gas alternately with the supply of the metal source gas and the nitride gas to form a first metal nitride film. The method of claim 1, And the metal source gas is a gas containing titanium, tungsten or tantalum. The method of claim 2, And the titanium-containing gas is titanium tetrachloride (TiCl 4) gas. The method of claim 1, The nitriding gas is nitrogen gas or ammonia (NH 3) gas, characterized in that the metal nitride film forming method. The method of claim 1, And the flushing gas is nitrogen gas or ammonia (NH 3) gas. The method of claim 1, Supplying a purge gas onto the semiconductor substrate after deposition of the metal nitride; And supplying a purge gas onto the semiconductor substrate after strengthening the nitriding reaction. The method of claim 6, The purge gas is an inert gas (inert gas) characterized in that the metal nitride film forming method. The method of claim 7, wherein And said inert gas is nitrogen gas. The method of claim 1, Forming a second metal nitride film on the first metal nitride film using a chemical vapor deposition process, wherein the chemical vapor deposition process provides for continuous supply of the metal source gas and the nitride gas without supply of the flushing gas. Metal nitride film forming method characterized in that proceeds through. An interlayer insulating film is formed on the semiconductor substrate, Forming a polysilicon contact plug penetrating the interlayer insulating film, Forming a molding film on the contact plug and the interlayer insulating film; Patterning the molding layer to form a storage node hole exposing the contact plug, Forming an ohmic contact layer on an upper surface of the contact plug, Depositing a metal nitride by supplying a metal source gas and a nitride gas onto a substrate having the ohmic contact layer, Supplying a flushing gas containing nitrogen to the substrate having the metal nitride to intensify the nitriding reaction of the metal film remaining under the metal nitride; And supplying the flushing gas alternately at least once with the supply of the metal source gas and the nitride gas to form a first lower electrode film made of a metal nitride film. The method of claim 10, wherein forming the ohmic contact layer And depositing a metal film on the substrate having the storage node hole. The method of claim 11, And the contact plug reacts with the metal film to form a metal silicide film during the deposition of the metal film. The method of claim 12, And removing the unreacted metal film remaining on the surfaces of the interlayer insulating film and the molding film after forming the metal silicide film. The method of claim 10, And the metal source gas is a gas containing titanium, tungsten or tantalum. The method of claim 14, The titanium-containing gas is a titanium tetrachloride (TiCl4) gas, the nitride gas is ammonia (NH3) gas or nitrogen gas manufacturing method characterized in that the M capacitor. The method of claim 15, The metal nitride is titanium nitride, the total thickness of the titanium nitride manufacturing method of the M capacitor, characterized in that 150 ~ 350Å. The method of claim 10, The flushing gas (MI) capacitor manufacturing method, characterized in that the NH3 gas or N2 gas. The method of claim 15, The titanium tetrachloride gas is a method of manufacturing the M capacitor, characterized in that supplied at a flow rate of 5 ~ 50sccm. The method of claim 10, The nitride gas manufacturing method of the M capacitor, characterized in that supplied at a flow rate of 10 ~ 50sccm. The method of claim 15, The titanium tetrachloride (TiCl 4) gas and the ammonia (NH 3) gas are supplied under a pressure of 1 to 5 Torr and a temperature of 550 to 800 ° C. The method of claim 10, Supplying a purge gas after the supply of the metal source gas and the nitriding gas; And supplying a purge gas after the supply of the flushing gas. The method of claim 21, The purge gas is nitrogen gas manufacturing method, characterized in that the M capacitor. The method of claim 10, Forming a sacrificial layer on the first lower electrode layer, By planarizing the sacrificial layer and the first lower electrode layer until the upper surface of the molding layer is exposed, a lower electrode covering the inner wall of the storage node hole and a sacrificial layer pattern remaining in the lower electrode are formed. Removing the sacrificial layer pattern and the molding layer to expose the inner and outer walls of the lower electrode; The method of claim 18, further comprising forming a dielectric film and an upper electrode on the lower electrode. The method of claim 10, A second lower electrode layer is formed on the first lower electrode layer using a chemical vapor deposition technique, wherein the chemical vapor deposition technique is performed through continuous supply of the metal source gas and the nitride gas without supplying the flushing gas. , Forming a sacrificial film on the second lower electrode film, By planarizing the sacrificial layer, the second lower electrode layer, and the first lower electrode layer until the upper surface of the molding layer is exposed, the lower electrode covering the inner wall of the storage node hole and the sacrificial layer pattern remaining in the lower electrode are formed. Forming, Removing the sacrificial layer pattern and the molding layer to expose the inner and outer walls of the lower electrode; The method of claim 18, further comprising forming a dielectric film and an upper electrode on the lower electrode. The method of claim 24, The first and second lower electrode films are formed using an in-situ method. The method of claim 24, The first and second lower electrode films are formed of a titanium nitride film, characterized in that the M capacitor manufacturing method. The method of claim 26, The first lower electrode film is formed of a thickness of 70 kHz to 200 kHz, the second lower electrode film manufacturing method of the M capacitor, characterized in that formed to a thickness of 70 kHz to 200 kHz.

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