KR20060019214A - Liquid crystal display - Google Patents

Abstract

In the liquid crystal display according to the present invention, a plurality of gate lines, a plurality of data lines insulated from and intersecting the gate lines, and two pixel electrodes are formed adjacent to each other in the gate line direction for each of the dual pixel regions defined by the intersection of the gate lines and the data lines. , A first display panel having a thin film transistor having three terminals connected to a gate line, a data line, and a pixel electrode, a second display panel having a common electrode facing the pixel electrode, and a liquid crystal layer formed between the first display panel and the second display panel. A display unit including a display unit, a backlight unit for supplying light to the display unit, an optical film unit including a diffusion film, horizontal and vertical prism films, positioned between the display unit and the backlight unit; It is preferable that 1/9 is larger than the pitch of a horizontal prism film. Accordingly, the liquid crystal display according to the present invention has an advantage of preventing the moiré phenomenon caused by the interference between the prism of the horizontal prism film and the plurality of gate lines by widening the distance between the gate lines.

LCD, horizontal prism film, vertical prism film, pitch, moire phenomenon

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

1 is a cross-sectional view of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a perspective view schematically illustrating a thin film transistor array panel, vertical and horizontal prism films of a liquid crystal display according to an exemplary embodiment of the present invention;

3 is a layout view of a thin film transistor array panel of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a cross-sectional view taken along the line IV-IV 'of FIG. 3,

5 is a perspective view schematically illustrating a thin film transistor array panel, vertical and horizontal prism films of a liquid crystal display according to another exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

110: substrate 121, 129: gate line

124: gate electrode 140: gate insulating film

151 and 154 semiconductor 161 and 165 resistive contact members

171, 179: data line 173: source electrode

175: drain electrode 180: protective film

181, 182, 185: contact hole 190: pixel electrode

81, 82: contact auxiliary member 141: diffusion film                 

142: horizontal prism film 143: vertical prism film

The present invention relates to a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which a field generating electrode is formed and a liquid crystal layer interposed therebetween. It is a display device which controls the transmittance | permeability of the light which passes through a liquid crystal layer by rearranging.

Such a liquid crystal display includes a backlight unit for generating light, an optical film unit for uniforming the luminance of light generated by the backlight unit, and a display unit for displaying an image using uniform light.

The optical film unit includes a diffusion film, a vertical prism sheet, a horizontal prism sheet, and a protector film that protects the surface of the prism.

However, when the pitch of the vertical prism film or the horizontal prism film and the gate line or data line of the display portion overlap each other, a moire fringe, which is an interference fringe in the form of a wave pattern, is likely to occur.

In order to prevent such a moiré phenomenon, AG (Anti Glare) treatment which scatters external light by surface irregularities was performed on the upper or lower polarizing plate. However, in this case, there is a problem of lowering the luminance, and in recent years, the moire phenomenon caused by the interference between the prism film and the gate line is generated while applying the upper polarizing plate to the glare type to improve the display quality.

The technical problem of the present invention is to provide a liquid crystal display device which prevents occurrence of moiré phenomenon.

In the liquid crystal display according to the present invention, a plurality of gate lines, a plurality of data lines insulated from and intersecting the gate lines, and two double pixel regions defined by the intersection of the gate lines and the data lines are adjacent to each other in the gate line direction. Display panel having three pixel electrodes, the gate line, the data line, and a thin film transistor having three terminals connected to the pixel electrode, a second display panel on which a common electrode facing the pixel electrode is formed, the first display panel, and the first display panel A display unit including a liquid crystal layer formed between two display panels, a backlight unit for supplying light to the display unit, an optical film unit positioned between the display unit and the backlight unit and including a diffusion film, horizontal and vertical prism films, 1/7 to 1/9 of the interval between the gate line is greater than the pitch of the horizontal prism film It is preferable.

Further, when the dual pixel areas adjacent to the upper and lower portions of the gate line are referred to as a first double pixel area and a second double pixel area, respectively, the gate line includes a pixel electrode and a second double pixel of the first double pixel area. It is preferable to apply a signal to all the pixel electrodes of the region.

In addition, the pixel electrode may be rectangular or triangular.

In the case where the pixel electrode has a triangular shape, it is preferable that the data line is bent along side surfaces of two triangular pixel electrodes.

Further, it is preferable that vertices of two triangular pixel electrodes are adjacent to each other in the double pixel region, or bottom sides of two triangular pixel electrodes are adjacent to each other in the dual pixel region.

Then, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A liquid crystal display according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 2 is a perspective view schematically showing a thin film transistor array panel, vertical and horizontal prism films, and a liquid crystal display according to an exemplary embodiment. 3 is a layout view of a thin film transistor array panel of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along the line IV-IV ′ of FIG. 3.

As shown in FIG. 1, the liquid crystal display 100 according to an exemplary embodiment of the present invention is positioned below the display unit 130 and the display unit 130 to display an image, and supplies light to the display unit 130. The backlight unit 150 is interposed between the backlight unit 150, the display unit 130, and the backlight unit 150, and includes an optical film unit 140 for uniforming the luminance of light generated by the backlight unit 150. In addition, the display unit 130 may include a thin film transistor (TFT) display panel 110, a color filter display panel 210 facing the thin film transistor array panel 110, and a liquid crystal layer injected between the display panels 110 and 210. It consists of (3). Lower and upper polarizers 12 and 22 are disposed outside the thin film transistor array panel 110 and the color filter display panel 210, respectively.

As illustrated in FIG. 2, the thin film transistor array panel 110 includes a plurality of pixel electrodes 190 arranged in a matrix form, and a plurality of thin film transistors for selectively transmitting signals to the pixel electrodes 190 (not shown). ), A plurality of gate lines 121 and a plurality of data lines 171 connected to the thin film transistor are provided.

As illustrated in FIG. 4, the color filter display panel 210 includes a common electrode 270 that generates an electric field together with the pixel electrode 190, and a color filter 230R for displaying colors. When a voltage is applied to the pixel electrode 190 and the common electrode 270, an electric field is formed to change the arrangement of liquid crystal molecules positioned therebetween.

The backlight unit 150 includes a plurality of lamps 151 for generating light and a light guide plate 152 for guiding light from the lamps 151 to the display unit 130. The light guide plate 150 is positioned under the display unit 130 and has a size corresponding to the display unit 130. As shown in FIG. 1, the light guide plate 150 may have a uniform thickness, and the thickness may increase or decrease gradually.

An optical film unit 140 is disposed on the upper part of the light guide plate 150 to uniform the luminance of the light directed toward the display unit 130, and the light reflected from the light guide plate 150 is again disposed below the backlight unit 130. The reflective plate 160 is disposed to reflect toward 150 to improve light efficiency.

The optical film unit 140 is composed of a plurality of optical films. That is, the optical film unit 140 diffuses the light generated by the backlight unit 150 to diffuse the film (diffusion film) 141 to uniform the brightness distribution, the vertical prism film to collect light having a uniform brightness distribution (Vertical Prism film) 143 and Horizontal Prism film (142).

The horizontal prism film 142 is formed on the diffusion film 141, and the vertical prism film 143 is formed on the horizontal prism film 142.

In addition, a protective film may be formed on the vertical prism film 143 to protect the surface shape of the vertical prism film 143.

The horizontal or vertical prism films 142 and 143 improve brightness by about 60% by reusing some of the light diffused through the diffusion film 141. That is, the light incident at a specific angle is partially transmitted by the prism and partially re-incident after reflection or transmission, thereby improving luminance by repeating this process. Therefore, when the horizontal and vertical prism films 142 and 143 are disposed to cross each other at right angles, the luminance is improved by about 120%.

However, when the prisms of the vertical prism film 143 and the data lines 171 of the display portion overlap each other, a moire pattern, which is an interference pattern in the form of a wave pattern, is likely to occur. The same applies to the case where the prisms of the horizontal prism film 142 and the gate lines 121 of the display portion overlap each other, and in the case of overlapping the prisms and the gate lines 121 of the horizontal prism film 142, the moiré ( Moire pattern occurs more prominently.

Moiré patterns occur when one or more structures with spatial periodicity overlap one another or are projected onto one another, and are moiré-shaped interference fringes having a period larger than the original period. This pattern is a kind of intensity interference effect using an incoherent light source.

In order to prevent the moiré pattern from occurring, it is preferable that 1/7 to 1/9 of the interval Lg between the gate lines 171 are larger than the pitch Ph of the horizontal prism film 142. Preferably, 1/8 of the interval Lg between the gate lines 171 is larger than the pitch Ph of the horizontal prism film 142.                     

To this end, in an exemplary embodiment of the present invention, as shown in FIG. 2, two pixel electrodes 190 are disposed between the gate lines 121 so that the distance Lg of the gate lines is larger than that of the related art. In addition, a structure in which one gate line 121 is connected to two pixel electrodes 190 separated based on the gate line 121 is devised. The structure of such a thin film transistor array panel will be described in detail below.

In addition, even when 1/7 to 1/9 of the interval Ld of the data lines 171 are larger than the pitch Pv of the vertical prism film 143, generation of moire fringes is suppressed.

Now, the structure of the thin film transistor array panel 110 of the liquid crystal display according to the exemplary embodiment will be described in detail.

3 and 4, a plurality of gate lines 121 for transmitting a gate signal are formed on the thin film transistor array panel 110 of the liquid crystal display according to the exemplary embodiment of the present invention. . The gate line 121 mainly extends in the horizontal direction, and a part of each gate line 121 forms a plurality of gate electrodes 124. The gate electrode 124 is formed in the form of a protrusion in the gate line 121, and as shown in the present embodiment, the gate line 121 may have a contact portion for transmitting a gate signal from the outside to the gate line 121. In this case, the end portion 129 of the gate line 121 has a wider width than the other portion, but in other cases, the end portion of the gate line 121 of the gate driving circuit is formed directly on the substrate 110. It is directly connected to the output.

On the thin film transistor array panel 110, a storage electrode wiring (not shown) may be formed on the same layer as the gate line 121.                     

The gate line 121 and the sustain electrode wiring (not shown) are made of metal such as Al, Al alloy, Ag, Ag alloy, Cr, Ti, Ta, Mo, or the like. As shown in FIG. 4, the gate line 121 and the sustain electrode wiring (not shown) of the present embodiment are made of a single layer, but have a small resistivity and a low specific resistance to metal layers such as Cr, Mo, Ti, and Ta, which have excellent physical and chemical properties. It may be made of a double layer including an Al-based or Ag-based metal layer. In addition, the gate line 121 and the sustain electrode wiring (not shown) may be made of various metals or conductors. The gate line 121 is inclined at the side and preferably has an inclination angle of 30-80 ° with respect to the horizontal plane.

A gate insulating layer 140 made of silicon nitride (SiNx) or the like is formed on the gate line 121.

A plurality of drain electrodes 175, including a plurality of data lines 171, are formed on the gate insulating layer 140. Each data line 171 extends mainly in a vertical direction and has a source electrode 173 extending from the data line 171 by extending a plurality of branches toward each drain electrode 175. The contact unit 179 located at one end of the data line 171 transfers an image signal from the outside to the data line 171.

Like the gate line 121, the data line 171 and the drain electrode 175 may be made of a material such as chromium and aluminum, and may be formed of a single layer or multiple layers.

Under the data line 171 and the drain electrode 175, a plurality of linear semiconductors 151 that extend mainly vertically along the data line 171 are formed. Each linear semiconductor 151 made of amorphous silicon extends toward each gate electrode 124, the source electrode 173, and the drain electrode 175 to have a channel portion 154.

Between the semiconductor 151, the data line 171, and the drain electrode 175, a plurality of linear ohmic contacts 161 and island-like ohmic contacts 165 for reducing contact resistance therebetween, respectively. Is formed. The ohmic contact 161 is made of amorphous silicon doped with silicide or n-type impurities at a high concentration, and has an ohmic contact 163 extending into a branch, and the island-type ohmic contact 165 has a gate electrode 124. Facing the ohmic contact 163.

On the data line 171 and the drain electrode 175, a-Si: C: O, a-Si formed by plasma enhanced chemical vapor deposition (PECVD), an organic material having excellent planarization characteristics, and photosensitivity. A protective film 180 made of a low dielectric constant insulating material such as: O: F or silicon nitride is formed.

The passivation layer 180 includes a plurality of contact holes 183 and 182 exposing at least a portion of the drain electrode 175 and an end portion 179 of the data line 171, respectively. Meanwhile, the end portion 129 of the gate line 121 also has a contact portion for connecting with an external driving circuit, and the plurality of contact holes 181 pass through the gate insulating layer 140 and the passivation layer 180 to pass through the gate line. Expose the end of (121).

A plurality of contact assistants 82 and 81 are formed on the passivation layer 180 including the plurality of pixel electrodes 190. The pixel electrode 190 and the contact auxiliary members 81 and 82 may use a transparent conductor such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductor having excellent light reflection characteristics such as aluminum (Al). To form.

The gate line 121 is formed so that the distance Lg between the gate lines is twice as large as that of the related art, thereby preventing the moiré phenomenon.

To this end, two pixel electrodes 1901a and 1902a are formed in the dual pixel areas A and B defined by the gate line 121 and the data line 171 crossing each other. The two rectangular pixel electrodes 1901a and 1902a are formed adjacent to each other in the direction of the gate line 121.

The dual pixel regions adjacent to the upper and lower portions of the gate line 121 are defined as the first dual pixel region B and the second dual pixel region A based on the gate line 121.

In this case, the gate line 121 preferably applies a signal to both the pixel electrode 1902b of the first dual pixel region B and the pixel electrode 1901a of the second dual pixel region A.

Therefore, in the case of arranging the gate lines 121 as described above, the number of gate lines is reduced to 1/2 as compared with the conventional art, and the distance Lg between the gate lines is twice as large as that of the conventional art. Moiré phenomenon is prevented.

In addition, since the anti-glare treatment does not need to be applied to the surface of the polarizing plate, and the anti-glare treatment does not need to be performed on the protective film of the prism film, the luminance is not reduced.

Meanwhile, a black matrix 220 is formed on the color filter panel 210 facing the thin film transistor array panel 110 to prevent light leakage at the edge of the pixel. The red, green, and blue color filters 230 are formed on the black matrix 220. The planarization layer 250 is formed on the entire surface of the color filter 230, and the common electrode 270 is formed on the color filter 230. The common electrode 270 is formed of a transparent conductor such as ITO or indium zinc oxide (IZO).

In addition, since the thin film transistors are disposed above and below the gate line 121, the black matrix 220 and the gap are disposed at positions covering both the thin film transistor of the upper pixel electrode 1902b and the thin film transistor of the lower pixel electrode 1901a. By forming the ash 320, the aperture ratio can be improved.

5 is a perspective view schematically illustrating a thin film transistor array panel, vertical and horizontal prism films of a liquid crystal display according to another exemplary embodiment of the present invention. Here, the same reference numerals as in the above-described drawings indicate the same members having the same function.

As shown in FIG. 5, the gate line 121 is formed so that the distance Lg between the gate lines is twice as large as that of the related art, thereby preventing the moiré phenomenon.

To this end, two pixel electrodes are formed in the dual pixel areas A and B defined by the gate line 121 and the data line 171 crossing each other. The two pixel electrodes are formed in a triangular shape.

The two pixel electrodes of the triangular shape formed in the dual pixel region are arranged so that the vertices are adjacent to each other, or the base is adjacent to each other.                     

The dual pixel regions adjacent to the upper and lower portions of the gate line 121 are defined as the first dual pixel region B and the second dual pixel region A based on the gate line 121.

In this case, the gate line 121 preferably applies a signal to both the pixel electrode of the first dual pixel region B and the pixel electrode of the second dual pixel region A. FIG.

Therefore, in the case of arranging the gate lines in this way, the number of gate lines is reduced to 1/2 compared to the conventional one, and the distance Lg between the gate lines is twice as large as the conventional one, thus preventing moiré phenomenon due to interference with the horizontal prism film. .

The data line 171 is bent along the side edges of two triangular pixel electrodes 190. Therefore, generation of moire fringes due to interference between the data lines 171 and the prisms of the vertical prism film 143 is suppressed.

Although the preferred embodiments of the present invention have been described in detail above, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention.

The liquid crystal display according to the present invention has an advantage of preventing the moiré phenomenon caused by the interference between the prism of the horizontal prism film and the plurality of gate lines by widening the distance between the gate lines.

Claims (7)

A plurality of gate lines, a plurality of data lines insulated from and intersecting the gate lines, two pixel electrodes formed adjacent to each other in the gate line direction for each of the dual pixel regions defined by the gate lines and the data lines intersecting, the gate lines, A first display panel having a thin film transistor having three terminals connected to the data line and the pixel electrode; A second display panel on which the common electrode facing the pixel electrode is formed; Liquid crystal layer formed between the first display panel and the second display panel Display unit comprising a, A backlight unit for supplying light to the display unit; An optical film unit positioned between the display unit and the backlight unit and including a diffusion film, horizontal and vertical prism films Including, 1/7 to 1/9 of the interval between the gate line is larger than the pitch of the horizontal prism film. In claim 1, When the dual pixel areas adjacent to the upper and lower portions of the gate line are referred to as a first dual pixel area and a second dual pixel area, respectively, The gate line applies a signal to both the pixel electrode of the first dual pixel region and the pixel electrode of the second dual pixel region. In claim 1, The pixel electrode has a rectangular shape. In claim 1, The pixel electrode has a triangular shape. In claim 4, And the data line is bent along side edges of the two triangular pixel electrodes. In claim 4, A vertex of the two pixel electrodes of the triangular shape adjacent to each other in the dual pixel region. In claim 4, And a bottom side of two triangular pixel electrodes adjacent to each other in the dual pixel region.

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