KR20060017163A - Method for fabricating the array substrate of thin film transistor - Google Patents

Abstract

The present invention provides a method for manufacturing a TFT array substrate to reduce the total number of mask processes by patterning the active layer and the data wiring layer simultaneously without applying a diffraction mask by applying a detachment process and a general mask process. In the present invention, forming a gate wiring and a gate electrode on a substrate, forming a gate insulating film on the entire surface including the gate wiring, laminating an active layer, a metal layer and a resist on the entire surface including the gate insulating film, Forming an active layer, a data line, and a source / drain electrode at the same time by applying a mask process and a detachment process; forming a passivation layer on the entire surface including the data line; and penetrating the passivation layer on the passivation layer. Forming a pixel electrode in contact with the drain electrode; Characterized in that made.

Low mask, detachment process, non-exposure process

Description

Method for Fabricating The Array Substrate Of Thin Film Transistor

1A to 1G are cross-sectional views of a TFT array substrate according to the prior art.

2 is a process flowchart of the TFT array substrate according to the present invention.

3A to 3E are cross-sectional views of a TFT array substrate according to the present invention.

4A to 4E are process cross-sectional views illustrating a detachment process.

* Explanation of symbols on the main parts of the drawings

111 substrate 112a gate electrode

113: gate insulating film 114: active layer

114a: ohmic contact layer 115: data wiring

115a: source electrode 115b: data electrode

116: protective film 117: pixel electrode

120: contact hole 152: resist

170: mold frame

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device (LCD), and more particularly to a method of manufacturing a TFT array substrate for a liquid crystal display device by reducing the number of masks.

Liquid crystal display devices have a high contrast ratio, are suitable for gray scale display and moving image display, and have low power consumption.

The liquid crystal display device forms various patterns such as a driving device or a wiring on a substrate to perform an operation, and photolithography is a common technique used to form a pattern.

The photo-etching technique consists of a series of complex processes as follows. First, a photoresist having a photosensitive property is coated on a substrate on which a pattern forming material is deposited, and then a mask made of a light blocking part and a transmitting part is aligned on the photoresist. It exposes. Then, the light-transmitted portion and the non-transmissive portion of the photoresist have different characteristics. When developing the exposed photoresist, only one portion of the light-transmitted portion and the non-transmissive portion remains selectively. The patterning material is etched using the patterned photoresist as a mask, and the remaining photoresist is completely removed to form a pattern having a desired shape.

Conventional liquid crystal display element array substrates generally use 5 to 7 mask techniques to form a gate wiring layer, a gate insulating film, an active layer, a data wiring layer, a protective film, and a pixel electrode on a substrate. As the number of photo etching techniques increases, the probability of process error and process ratio increase.

In particular, the exposure equipment used in the photo-etching technology has a larger equipment cost than other equipment. Recently, as the substrate size is enlarged and the pattern size is reduced, the equipment price is greatly increased.

In order to overcome this problem, research on "low mask technology" has been actively conducted in order to increase productivity and secure process margin by minimizing the number of application of photolithography technology (the number of times of exposure equipment).

In particular, a four mask process using diffraction exposure has been proposed, and the number of exposure apparatuses is reduced by using diffraction exposure equipment to simultaneously pattern the active layer and the data wiring layer in one process.

Hereinafter, a manufacturing method of a TFT array substrate for a liquid crystal display device according to the prior art will be described with reference to the accompanying drawings.

1A to 1G are cross-sectional views of a TFT array substrate according to the prior art.

First, as shown in FIG. 1A, after depositing a low resistance metal material on the glass substrate 11, a plurality of gate wiring layers, that is, gate wirings (not shown), are formed by using a photoetching technique using a first mask. And the gate electrode 12a.

Next, as shown in FIG. 1B, an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited at a high temperature on the entire surface including the gate electrode 12a to form a gate insulating layer 13.

Subsequently, an amorphous silicon (a-Si) 14a and an ohmic contact layer (n + a-Si) 14b in which impurities are ion-implanted into the amorphous silicon are deposited on the entire surface of the gate insulating layer 13 in sequence, A low resistance metal layer 25, which is a material for data wiring, is deposited thereon.

After applying a photoresist 52, which is a UV curable resin, to the low resistance metal layer 25, a diffraction mask 90 is formed as a second mask on the photoresist 52. ) And then exposed to UV or x-ray wavelength to expose the exposed photoresist 52.

In this case, a diffraction mask 90 is used to cause the pattern of the photoresist 52 to have a double step. The diffraction mask 90 shields light at a portion where data lines and source / drain electrodes are to be formed. And a light transmitting portion 90a, a semi-transmissive portion 90b that transmits only half of the light in the portion (between the source electrode and the drain electrode) where the channel region of the thin film transistor is to be formed, and a transmissive portion that transmits the light in the remaining portion.

Therefore, when exposed and developed using the diffraction mask 90, as shown in FIG. 1C, the photoresist 52 corresponding to the light shielding portion 90a remains, and the photoresist 52 corresponding to the transmission portion. ) Are completely removed, and the photoresist 52 corresponding to the transflective portion 90b remains thinner than that formed in the light shielding portion 90a. That is, the photoresist 52 in the portion corresponding to the channel region has a lower step.

Next, as illustrated in FIG. 1D, the low resistance metal layer 25, the amorphous silicon 14a, and the ohmic contact layer 14b exposed between the photoresist 52 are collectively etched, and then a low stepped photoresist ( The photoresist 52 is ashed until 52 is removed.                         

As shown in FIG. 1E, the low resistance metal layer 25 of the channel region partially exposed between the photoresist 52 and the ohmic contact layer n + a-Si 14b are simultaneously etched.

As a result, the data line 15 defining the unit pixel region crossing the gate line and the active layer 14a and the source / drain electrodes 15a and 15b formed on the gate electrode 12a are completed.

The gate electrode 12a, the gate insulating layer 13, the active layer 14, and the source / drain electrodes 15a and 15b stacked as described above are thin film transistors that control voltage on / off applied to the unit pixel region. To achieve.

Next, as shown in FIG. 1F, a protective film 16 is formed by coating an organic insulating material such as BCB or an inorganic insulating material of SiNx on the entire surface including the data line 15. In addition, a portion of the passivation layer 16 is removed by a photoetching technique using a third mask to form a contact hole through which the drain electrode 15b is exposed.

Next, a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), is deposited on the entire surface including the passivation layer 16, and then, on the drain electrode 15b using a photoetching technique using a fourth mask. The TFT array substrate is completed by forming the pixel electrode 17 in each unit pixel region so as to be electrically connected.

As described above, the array substrate on which the thin film transistor TFT is formed is not shown, but is bonded by a sealant with an opposing substrate and a spacer interposed therebetween. The liquid crystal is injected between the two substrates to form a liquid crystal layer and the liquid crystal inlet is sealed to complete the liquid crystal display device.

As described above, the TFT array substrate for a liquid crystal display device according to the prior art applies a diffraction exposure mask once in order to use a minimum mask. Generally, the diffraction exposure mask has a disadvantage in that the unit price is high and the process control is difficult. have.

Therefore, in order to solve the above problems, the present invention simultaneously forms an active layer and a data wiring layer by a detachment method and a general exposure process, thereby reducing the number of mask processes without using a diffraction exposure mask. It is an object of the present invention to provide a method for manufacturing a TFT array substrate.

A method of manufacturing a TFT array substrate of the present invention for achieving the above object comprises the steps of forming a gate wiring and a gate electrode on the substrate, forming a gate insulating film on the entire surface including the gate wiring, and the gate insulating film Stacking an active layer, a metal layer and a resist on the entire surface of the substrate, and simultaneously forming an active layer, a data line, and a source / drain electrode by applying a mask process and a detachment process; and a protective film on the front surface including the data line. And forming a pixel electrode contacting the drain electrode through the passivation layer on the passivation layer.

That is, unlike the conventional method in which the diffraction exposure mask is used to simultaneously form the active layer and the data wiring layer, the active layer and the data wiring layer are collectively formed using only a general mask process and a detachment process. Therefore, the number of mask steps can be reduced once without using a diffraction exposure mask.

Hereinafter, a method of manufacturing a TFT array substrate for a liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a process flowchart of the TFT array substrate according to the present invention, and FIGS. 3A to 3E are process cross-sectional views of the TFT array substrate according to the present invention, and FIGS. 4A to 4E are process cross-sectional views showing a detachment process.

In order to form an array substrate for a liquid crystal display device according to the present invention, as shown in the flowchart of FIG. 2, after depositing a first metal layer on the prepared substrate and forming a gate wiring and a gate electrode by a first mask process (S1). A gate insulating film is formed on the entire surface including the gate wiring (S2).

Next, an active layer material and a second metal layer are stacked on the gate insulating layer, and a second mask process and a detachment process are sequentially performed to simultaneously form an active layer, a data line, and a source / drain electrode (S3). As described above, the active layer material and the second metal layer are collectively patterned without using a diffraction mask such as a slit mask or a help-tone mask.

Subsequently, a passivation layer is formed on the entire surface including the data line and a contact hole is formed by a third mask process (S4), and then the pixel electrode connected to the drain electrode through the contact hole on the passivation layer is subjected to the fourth mask process. It forms by (S5).

As such, since the four mask process can be performed without using the diffraction mask by applying the detachment process, the difficulty and the cost of the process by using the diffraction mask can be reduced.

Hereinafter, the manufacturing method will be described in detail.

First, as illustrated in FIG. 3A, copper (Cu), aluminum (Al), and aluminum alloy (AlNd) having low resistivity of 15 μΩcm ⁻¹ or less for preventing signal delay on the transparent and excellent heat resistant substrate 111. : A first metal layer such as aluminum neodymium, molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), and molybdenum-tungsten (MoW) is deposited by a sputtering method.

Next, after the first mask is disposed on the first metal layer and exposed, a gate wiring (not shown) and a gate electrode 112a are formed through a developing and etching process.

Specifically, after depositing a metal on a substrate at a high temperature and applying a photoresist thereon, by placing a patterned first mask on the photoresist and selectively irradiating light to the same as the pattern of the first mask After the pattern is formed on the photoresist, the photoresist is patterned by removing the photoresist of the lighted portion using a developer. The metal of the exposed portion is selectively etched from the patterned photoresist to obtain a desired pattern.

Subsequently, an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited on the entire surface including the gate electrode 112a by PECVD to form a gate insulating layer 113.                     

Subsequently, an ohmic contact layer (n + a-Si) in which impurities are ion-implanted into the active layer (a-Si) 114a which is amorphous silicon and the amorphous silicon (a-Si) on the entire surface of the gate insulating layer 113 ( 114b) is sequentially deposited, and a second metal layer 125, which is a data wiring material, is deposited thereon.

After the resist 152 is coated on the second metal layer 125 by a spin method, a roll coating method, or the like, a second mask is disposed on the resist 152. The resist 152 is exposed and developed to be patterned.

Thereafter, as shown in FIG. 3B, the active layer (a-Si) 114a, the ohmic contact layer (n + a-Si) 114b, and the second metal layer 125 exposed to the outside of the patterned resist 152. ) Is patterned in a batch.

Subsequently, the mold frame 170 is disposed on the patterned resist 152 and pressurized, and as shown in FIG. 3C, the resist 152 corresponding to the channel region of the active layer 114a is transferred to the mold frame 170. Remove by adsorbing on the embossed.

On the other hand, since the resist should be applied not only to the detachment process but also to the photoetch process, a material having photosensitivity is used.

The mold frame used in the detachment process is preferably one having an elastic property such as poly dimethyl siloxane (PDMS), poly urethane (PU), or the like, but the type of the mold frame is not limited thereto.

Thereafter, as shown in FIG. 3D, the second metal layer 125 between the resist 152 in which the channel region is opened is removed. As a result, the data line 115 perpendicular to the gate line, the source / drain electrodes 115a and 115b formed on the gate electrode 112a, and the source / drain electrodes 115a and 115b are formed below. The active layer 114 is formed. The thin film transistor may include a stacked layer of the gate electrode 112a, the gate insulating layer 113, the active layer 114, the ohmic contact layer 114b, and the source / drain electrodes 115a and 115b.

At this time, when the second metal layer 125 is etched, the ohmic contact layer 114b is partially etched, and the ohmic contact layer 114b is formed between the source / drain electrodes 115a and 115b and the active layer 114a. Improves contact contact characteristics.

In this case, the detachment process will be described in more detail as follows.

First, as shown in FIG. 4A, the etched layer 212 and the resist 251 are sequentially formed on the substrate 211, and then dried at about 60 to 70 ° C. to remove the solvent of the resist 251. To solidify.

After the resist 251 is solidified to some extent, as shown in FIGS. 4B and 4C, the mold frame 270 is disposed on the resist 251 and then pressed by the pressure roller 280. In this case, by applying heat of about 100 ° C., which is the glass transition temperature of the resist, fluidity is generated in the resist 251 so that the resist 251 in contact with the relief of the mold frame 270 is adsorbed on the mold frame 270. .

Therefore, when the mold frame 270 is removed, as shown in FIG. 4D, the resist 251 adsorbed to the relief of the mold frame 270 is removed, and only the resist 251 of the portion corresponding to the intaglio is removed. It remains. Finally, as shown in FIG. 4E, if the resist 251 is removed using the resist 251 as a mask, a desired pattern is obtained.

The detachment process as described above is to pattern the resist by absorbing and removing the solidified resist on the relief of the mold frame, and the process is simplified and the cost is greatly lowered by not using an exposure apparatus including a mask.

After the active layer 114a, the ohmic contact layer 114b, the source / drain electrodes 115a and 115b and the data wiring 115 are patterned by the second mask process including the detachment process as described above, After completely removing the remaining resist 152, as shown in FIG. 3E, an organic insulating material such as benzocyclobutene (BCB), an acryl resin, or SiNx is applied to the entire surface including the data line 115. , A protective layer 116 is formed by depositing an inorganic insulating material such as SiOx, and selectively removes the protective layer 116 by a third mask process to expose a predetermined portion of the drain electrode 115b. ).

Subsequently, a transparent conductive film such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the entire surface including the passivation layer 116 by a sputtering method, and then patterned by a fourth mask process to drain the drain. The pixel electrode 117 connected to the electrode 115b is formed.

Thus, a total of four mask processes complete the TFT array substrate.

Although not shown, the thin film array substrate has a liquid crystal layer bonded to the opposing substrates and provided between the two substrates, wherein the opposing substrates include a black matrix for preventing leakage of light and an R, between the black matrix. A color filter layer having G and B color resists formed in a predetermined order, an overcoat layer for protecting the color filter layer on the color filter layer and planarizing the surface of the color filter layer, and a pixel on a thin film array substrate formed on the overcoat layer In addition to the electrodes, a common electrode forming an electric field is formed.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

The method of manufacturing a TFT array substrate of the present invention as described above has the following effects.

By applying a detachment process and a mask process to form the active layer and the data wiring layer collectively, a pattern can be formed without using a diffraction mask.

Therefore, the number of photo-etching processes using the mask can be reduced, and the cost increase and the difficulty of the process by using the diffraction exposure equipment can be reduced.

Claims (4)

Forming a gate wiring and a gate electrode on the substrate; Forming a gate insulating film on the entire surface including the gate wiring; Stacking an active layer, a metal layer, and a resist on the entire surface including the gate insulating layer, and simultaneously forming an active layer, a data line, and a source / drain electrode by applying a mask process and a detachment process; Forming a protective film on the entire surface including the data line; And, And forming a pixel electrode contacting the drain electrode through the passivation layer on the passivation layer. The method of claim 1, Forming the active layer, the data wiring and the source / drain electrodes by the mask process and the detachment process may include: Depositing an active layer, a metal layer and a resist on the gate insulating film; Patterning the resist to cover the data line, the source / drain electrodes and the channel region by the mask process; Collectively etching the active layer and the metal layer using the patterned resist as a mask; Removing the resist of the channel region by the detachment process, and then removing the metal layer of the channel region. The method of claim 2, wherein the detachment process, Heating the mold frame while contacting the resist with the resist to adsorb the resist to the relief of the mold frame; Removing the mold frame to remove resist of the portion adsorbed on the relief of the mold frame. The method of claim 1, wherein the resist is formed of a material having photosensitivity.

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