KR20060014438A - Method of designing a reticle and forming a semiconductor device therewith - Google Patents

Abstract

A method of designing and forming a reticle (404), as well as the manufacture of a semiconductor substrate (410) using the reticle, includes defining a first edge of a reticle layout file. The first edge corresponds to a reference feature (12, 14). The method further includes using the reference feature to insert a subresolution assist feature (62, 64) into the reticle layout file. The subresolution assist feature is at an angle (Theta) with respect to a line (82,84) containing the first edge, wherein the angle differs from 90 degrees. In one embodiment, the subresolution assist features can be manually or automatically inserted into the layout file after the locations of the assist features have been determined. The subresolution assist features are not patterned on the substrate, but assist in forming resist features of uniform dimension.

Description

METHODE OF DESIGNING A RETICLE AND FORMING A SEMICONDUCTOR DEVICE THEREWITH}

TECHNICAL FIELD The present invention generally relates to the field of semiconductors and photolithography, and more particularly, to a method of designing a reticle and forming a semiconductor device therewith.

As part of semiconductor device fabrication, photolithography processes are used to form patterns in photoresist layers on semiconductor wafers. The photolithography process includes transferring light through the reticle and the lens onto the photoresist layer. As used herein, the terms mask, photomask, and reticle may be used interchangeably. The pattern on the photoresist layer is then transferred to an underlying layer (eg copper) on the semiconductor wafer to form a semiconductor device feature (eg via). However, photolithography is subject to processing variations such as focal changes. In addition, semiconductor devices require smaller dimensions in forming next generation products.

Often, the pattern on the reticle is not transferred to the photoresist layer without errors due to process variations. In other words, the pattern on the reticle is sent with an error. Often, process variations cause smaller features to be printed than designed. For isolated features (i.e., features without other features nearby), the focus change is more important than for dense features (specifically, features with other features nearby). Thus, there is a need for a photolithography process that enables improved photolithographic patterning of isolated features and increased processing control over the formation of isolated features in semiconductor fabrication processes.

Lower resolution assist features have been used in an effort to improve wafer patterning margins. These lower resolution supplemental features are placed opposite the edges of the isolation design feature. However, this arrangement creates a difficulty in the design position where the first design feature meets another design feature. Such placement is difficult to inspect on the reticle and results in small spaces between auxiliary features that are difficult to implement in software.

Thus, there is a need for improved reticle inspection, improved wafer patterning margins, and ease of implementation of lower resolution auxiliary feature algorithms.

According to one embodiment, a method of forming and designing a reticle, and a method of manufacturing a semiconductor substrate using such a reticle, includes defining a first edge of the reticle layout file. The first edge corresponds to the reference feature. This method includes inserting a lower resolution auxiliary feature into the reticle layout file using the reference feature. The lower resolution auxiliary feature makes an angle [theta] with respect to the line containing the first edge, which is different from 90 [deg.].

Embodiments of the present invention are described by way of example and are not limited by the accompanying drawings, in which like reference characters indicate like elements.

1 illustrates a target design with lower resolution assist features.

2 shows a range of depth of focus of the target design of FIG. 1.

3 illustrates another target design with lower resolution assist features.

4 illustrates another target design with lower resolution assist features.

5 illustrates a target design with an improved lower resolution secondary feature in accordance with an embodiment of the present invention.

FIG. 6 illustrates a range of depth of focus of the target design of FIG. 5. FIG.

7 illustrates the target design of FIG. 5 with an enhanced lower resolution secondary feature formed in accordance with one embodiment of the present invention.

8 illustrates the target design of FIG. 5 with an improved lower resolution auxiliary feature formed in accordance with another embodiment of the present invention.

9 illustrates the target design of FIG. 3 with an improved lower resolution secondary feature formed in accordance with one embodiment of the present invention.

10 illustrates the target design of FIG. 4 with an improved lower resolution auxiliary feature formed in accordance with another embodiment of the present invention.

FIG. 11 illustrates depth of focus of a target design with enhanced lower resolution assist features in accordance with one embodiment of the present invention. FIG.

12 illustrates a target design with an improved lower resolution secondary feature in accordance with another embodiment of the present invention.

13 illustrates a method of designing a reticle having an enhanced lower resolution secondary feature in accordance with an embodiment of the present invention.

FIG. 14 is a block diagram illustrating a system for forming a semiconductor device using a reticle having improved lower resolution auxiliary features according to an embodiment of the present invention. FIG.

Those skilled in the art will understand that the elements of the figures are shown for simplicity and clarity and are not to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to aid a better understanding of embodiments of the present invention.

According to one embodiment of the invention, a lower resolution auxiliary feature is provided in the reticle and is not arranged to face the edge of the design feature. In one embodiment, the lower resolution auxiliary feature is connected to the main feature or placed at an angle to the edge by design as described below. This embodiment allows for improved coverage of secondary features with improved process margins and reduced reticle inspection issues.

As used herein, the resolution limit refers to the resolution limit of the lithography tool used to expose the resist layer. Lower resolutions are below this resolution limit. Auxiliary features are "lower resolution" reticle features when the corresponding images are below the resolution limit when projected onto the resist layer and do not substantially pattern the underlying resist layer. For example, a lithography tool may have a 4x projection system and a resolution limit of 0.2 microns. A secondary feature with a width of 0.60 microns on the reticle is a lower resolution reticle feature since the projected image is 0.15 microns, which is below the resolution limit of 0.2 microns.

Embodiments discussed herein can be used for a wide variety of wavelengths of radiation sources, numerical apertures of lenses, and resist materials used to form semiconductor devices. Examples of wavelengths of use may range up to approximately 436 nanometers (g-line). Other commonly used wavelengths include approximately 365 nanometers (i-line), approximately 248, 193 or 157 nanometers (extreme ultraviolet or DUV) and approximately 13 nanometers (ultra-ultraviolet or EUV). The numerical aperture of the lens is typically in the range of about 0.45 to 0.90. The resist material is typically determined by the radiation source used, since the materials in the resist should be optimally activated at the wavelength used as the radiation source. Other resist materials, light source configurations, numerical apertures and wavelengths can be used. This embodiment may also be used in longer wavelength systems to extend the useful life of the device before replacing the device.

This embodiment can be used during the design and formation of the reticle. During the design, a semiconductor device layout file is generated. A portion of the layout file corresponding to the lower resolution subfeature is created. Lower resolution auxiliary features may be inserted into the layout file manually or automatically after the location of the auxiliary features is determined.

After the layout file is completed, the layout file can be transferred to a reticle manufacturing tool such as an electron beam recorder. Typically, the layout file is downloaded to a computer coupled to the reticle manufacturing tool. The reticle substrate is processed to form a reticle having the desired pattern of target design. The reticle can then be used to form a semiconductor device by exposing and developing a resist layer to provide a resist profile having features that conform to the pattern of the reticle.

1 is a diagram illustrating a target design 10 that includes target device features 12, 14. Target device features 12, 14 may include, for example, vias. Target design 10 may further include a lower resolution assist feature identified by reference numerals 30-30, disposed parallel to the edges of the tablet device features 12,14. Auxiliary features 20 and 22 overlap each end at a traditional 90 degree angle, as indicated at 32. Traditional angles can also include zero. At position 32, there is a risk that overlapping auxiliary features 20, 22 are resolved in the photoresist pattern of the wafer or substrate. Additionally, auxiliary features 28 and 30 are located near each end without overlapping, as indicated at 34. At position 34, there is a risk that the reticle manufacturing capability or reticle inspection capability of the secondary features 28, 30 is reduced. In a typical reticle layout process, one or more auxiliary features 20, 22, 28, and 30 will be removed from the reticle layout to overcome the deficiencies described above.

FIG. 2 is a diagram illustrating a depth of focus range of the target design 10 of FIG. 1. Target design 10 includes target device features 12, 14 and lower resolution assist features 16, 18, 20, 24, 26, 30 disposed parallel to the edges of each target device feature 12, 14; Include. In FIG. 2, note that the secondary features 22, 28 shown in FIG. 1 have been removed. At optimal processing conditions, an optimal focus image of the resulting wafer pattern for each target device feature 12, 14 is indicated by reference numerals 36, 40. In degraded processing conditions, a defocus image of the resulting wafer pattern for each target device feature 12, 14 is indicated by reference numerals 38, 42. Under optimal focus conditions, wafers 36 and 40 are substantially similar in size. However, in defocus conditions, wafer pattern 38 is substantially larger than wafer pattern 42. Large changes in the size of the wafer pattern 42 between these optimal focus conditions and defocus conditions are undesirable and lead to undesirable process and / or circuit failures.

3 illustrates another target design 44 that includes target device features 46 and 48. Target design 44 further includes lower resolution assist features 50, 52, 54 disposed parallel to the edge of each target device feature 46, 48. Secondary feature 50 is located proximate each end of target device feature 46 as indicated by reference numeral 56. Auxiliary features 52, 54 are located proximate without overlapping at each end as indicated by 58. At positions 56 and 58, there is a risk that the reticle manufacturing capability or reticle inspection capability of the associated auxiliary features is reduced.

4 shows a target design 45 that includes a target device feature 47, such as a polysilicon line or gate electrode, for example. Target design 45 further includes lower resolution assist features 49, 51, 53 positioned parallel to the edge of each target device feature 47. Target design 45 may include other target design features not shown. Auxiliary features 49 and 51 contact each other at each end as indicated by 55. At position 55, there is a risk that the overlap of auxiliary features 49, 51 is resolved within the pattern of the photoresist of the wafer or substrate. In addition, auxiliary features 51 and 53 are located proximate at each end without overlapping, as indicated by reference numeral 57. At position 57, there is a risk of reducing the reticle manufacturing capability or reticle inspection capability of the secondary features 51, 53.

5 illustrates a target design 60 with enhanced lower resolution assist features in accordance with one embodiment of the present invention. Target design 60 includes target device features 12, 14, such as, for example, vias. Target design 60 includes lower resolution assist features 16, 18, 24, 26 located parallel to the edge of each target device feature 12, 14. Additionally, target design 60 includes secondary features 62 and 64 positioned at an angle to each edge of each of the two target device features, as shown in FIG. 5 and described in more detail below. . It should be noted that the embodiment of FIG. 5 does not have auxiliary features that overlap or are located close to each other. Thus, target design 60 provides a reticle with improved reticle manufacturing capability and reticle inspection capability.

6 illustrates a range of depth of focus of the target design 60 of FIG. 5. The lower resolution auxiliary features 62, 64 are angled, and under optimal processing conditions, the optimal focus image of the resulting wafer pattern for each target device feature 12, 14 is indicated by reference numerals 66 and 70. Is directed. At degraded processing conditions, defocused images of the resulting wafer pattern for each target device feature 12, 14 are indicated by reference numerals 68 and 72. At optimal focus conditions, wafer patterns 66 and 70 are substantially smaller in size than respective target device features 12 and 14. Additionally, under defocus conditions, wafer patterns 38 and 72 are substantially smaller in size but slightly smaller in size with respective target device features 12 and 14. As a result, the minimum value of the size variation of the wafer patterns 66, 70 or 68, 72 can be obtained, which can achieve the desired process and / or circuit performance.

An advantage of this embodiment is that the lower resolution auxiliary feature achieves a more consistent width of the resist feature developed across the substrate surface, regardless of whether the feature is a dense feature pattern, a semi-dense feature pattern, or a loose feature pattern. It helps. The consistency of the width should still be maintained even if there is a slight change in the lithographic processing conditions.

7 illustrates a target design 80 having an improved lower resolution assist feature formed in accordance with one embodiment of the present invention. Target design 80 includes target device features 12, 14. Target design 80 also includes secondary features 62 and 64 that are angled to the edges of the two target device features 12 and 14. In the method of forming the auxiliary features 62, 64, geometric operations are performed on the edges of the target devices 12, 14 so that angles greater than 0 degrees and less than 90 degrees with respect to each edge of the target devices 12, 14. Produced edges 82 and 84 located at With respect to the induced edges 82, 84, the secondary features 64, 62 are equally arranged in parallel. The secondary feature 62 has a length 94, a width 96, and is located a distance 88 away from the induced edge 84. The secondary feature 64 has a length 90, a width 92, and is located a distance 86 away from the induced edge 82. The specific lengths, widths, and distances of the secondary features 62, 64 may be determined according to the specific design requirements of a given application.

8 illustrates a target design 180 having an improved lower resolution auxiliary feature formed in accordance with one embodiment of the present invention. Target design 180 includes target device features 12, 14. Target design 80 also includes secondary features 62 and 64 positioned at an angle with two target device features 12 and 14. In the method of forming auxiliary features 62 and 64, geometric operations are performed on the edges of target devices 12 and 14 to form derived features 112 and 114. For example, each target device rotates about its center to create each derived feature. The derived features 112, 114 are disposed at an angle greater than 0 degrees and less than 90 degrees with respect to each first edge of the target device 12, 14.

Geometric operations are performed on the edges of the derived features 112, 114 to produce the derived edges 182, 184. Subsequently, additional geometric operations are performed on the derived edges 182, 184 to create the secondary features 62, 64. With respect to the induced edges 182, 184, the secondary features 64, 62 are disposed in parallel. Auxiliary feature 62 has a length 94, a width 96, and is located a predetermined distance from induced edge 184. Auxiliary feature 64 has a length 90, a width 92, and is located a predetermined distance from induced edge 182. The particular length, width and distance of the secondary features 62, 64 can be determined according to the specific design requirements of a given application.

9 illustrates the target design of FIG. 3 with an improved lower resolution auxiliary feature formed in accordance with one embodiment of the present invention. 9 shows a target design 144 that includes target device features 46 and 48. Target design 144 further includes lower resolution assist features 150, 152, 154, 156. Lower resolution assist features 150, 152, 156 are located parallel to the edge of each target device feature 46, 48. Auxiliary feature 150 is also attached to each end of target device feature 46, indicated by reference numeral 162.

As indicated by reference numeral 160, the supplemental feature 154 is located at an angle θ greater than 0 degrees and less than 90 degrees with respect to each edge of the lower resolution target device feature 48. Additionally, lower resolution assist feature 154 overlaps each end of lower resolution assist feature 152, 156. The lower resolution assist feature 154 is at an angle greater than 0 degrees and less than 90 degrees with respect to each edge of the lower resolution assist features 152, 156. In the embodiment of FIG. 9, there are no auxiliary features that are only close to each other.

Thus, target design 144 provides a reticle having improved reticle manufacturing capability and / or reticle inspection capability. Additionally, in the embodiment of FIG. 9, there are no secondary feature edges that overlap or merge with other secondary features at an angle of 90 degrees. Thus, target design 144 lowers the risk that overlapping secondary features 152, 154, 156 resolve to photoresist patterns in a wafer or substrate during the lithographic patterning process.

10 illustrates the target design of FIG. 4 with an improved lower resolution auxiliary feature formed in accordance with another embodiment of the present invention. More specifically, FIG. 10 shows a target design 145 with target device features 47 such as, for example, polysilicon lines or gate electrodes. Target design 145 further includes lower resolution assist features 149, 151, 153 located parallel to each edge of target device feature 147. Additionally, target design 145 further includes lower resolution assist features 159 and 161 positioned at an angle other than 90 degrees with respect to each edge of target device feature 47. Target design 145 may also include other target device features not shown.

As shown, the angular lower resolution auxiliary feature 159 overlaps the auxiliary features 151 and 153 at each end as indicated by reference numeral 157. More specifically, the ends of the lower resolution auxiliary features 159 overlap the ends of the auxiliary features 151 and 153, and the additional lower resolution auxiliary features 159 are positioned at an angle other than 90 degrees with respect to the auxiliary features 151 and 153.

In a similar manner, the angled lower resolution auxiliary feature 161 overlaps the secondary features 149 and 151 with each end as indicated at 155. That is, each end of the secondary feature 161 overlaps with the corresponding end region of the secondary feature 149, 151, and the secondary feature 161 is positioned at an angle other than 90 degrees. Comparing with reference to FIG. 4, the supplemental features 49, 51 are parallel to each other and contact at each end as indicated with reference 55 with respect to each other. As noted above, at location 55 there is a risk that the monopole contacts of auxiliary features 49 and 51 are resolved within the fortiresist pattern of the wafer or substrate during the lithographic process. Referring again to FIG. 10, reference numerals 163 and 165 correspond to portions of resist features 49 and 51 of FIG. 4, which have been modified in accordance with one embodiment of the present invention. That is, according to one embodiment of the invention, the original resist features 49 and 51 of FIG. 4 have also been modified with the placement of the inclined lower resolution auxiliary feature 161.

Thus, the embodiment of FIG. 10 does not have auxiliary features located simply in proximity to each other. Moreover, target design 145 provides a reticle with improved reticle manufacturing capability and / or reticle inspection capability. It should also be noted that in the embodiment of FIG. 10 there are no secondary feature edges that merge or overlap at an angle of 90 degrees. Thus, the target design 145 lowers the risk of overlapping auxiliary features 149, 151, 153, 161 being resolved to the photoresist pattern on the wafer or substrate during the lithography process patterning step.

11 illustrates depth of focus of a target design with improved lower resolution assist features in accordance with one embodiment of the present invention. In particular, FIG. 11 shows a target design 200 that includes a target device feature 202. In the absence of degraded processing conditions and lower resolution assist features located within the target design 200, a defocus image of the resulting wafer pattern will occur for the target device feature 202, as indicated by reference numeral 204. Pattern 204 has a substantially smaller size than target device feature 202. This change in magnitude between the target device patcher 202 and the pattern 204 may indicate a circuit failure at an unwanted process and / or critical circuit location as indicated by reference numeral 216, such as, for example, an active transistor region. It may cause. However, unwanted process and / or circuit failures can be avoided due to the addition of lower resolution assist features in accordance with one embodiment of the present invention.

In the use of lower resolution assist features 206 and 208 located within target design 200 and degraded processing conditions, a defocus image of the resulting wafer for target device feature 202 is possible, as indicated by reference numeral 210. It should be noted that the patterns 202 and 210 are substantially similar in size at the critical circuit location 216. In this embodiment, the lower resolution auxiliary features 206 and 208 are critical circuits to ensure that the size of the defocus image 202 at position 216 is substantially similar to the target device feature 202 at position 216. Located parallel to the edge of position 216. Additionally, one end of each lower resolution assist feature 206, 208 is positioned to contact (or lightly overlap) the target device feature 202 at a location corresponding to that shown. As a result, wafer pattern 210 shows small pattern bumps 212 and 214 at locations where lower resolution assist features 206 and 208 contact target device feature 202, respectively. Since the pattern bumps 212 and 214 are not in the critical circuit position, they do not cause unwanted circuit performance. Thus, the embodiment of FIG. 11 simply does not have auxiliary features located close to each other or close to the target device feature. Moreover, the location of the lower resolution assist features 206 and 208 in the target design 200 results in desired process and / or circuit performance.

12 illustrates a target design 220 with an enhanced lower resolution secondary patcher in accordance with another embodiment of the present invention. Target design 220 includes target device features 222, 224, 226, 228. The target design 220 also includes a lower resolution assist feature 236 located between the target device features 222, 224, 226, 228. In one method of forming the lower resolution secondary feature 236, geometric operations are performed on the edges of the target device features 222, 224, 226, 228 to determine patches of the secondary feature 236 and form the secondary feature 236. For example, the secondary feature 236 can be collectively formed between the edges of the target device 222, 224, 226, 228.

In another method of forming secondary feature 236, geometric operations may be performed on the corner edges of target device 222, 224, 226, 228 to produce derived feature edges 230, 232. The derived feature edges 230, 232 intersect at the points indicated by reference numeral 234. Point 234 provides a central reference point for use in forming lower resolution assist feature 236 and is collectively located between the inner peripheral edges of target device 222, 224, 226, 228. Thereafter, geometric operations are performed on the derived feature edges 230, 232 to produce the lower resolution auxiliary feature 236. As shown, the edge of the lower resolution assist feature 236 does not directly face any edge of the target device feature 222, 224, 226, 228. Additionally, the edges of the secondary feature 236 are located parallel to each edge of the target device features 222, 224, 226, 228.

13 is a flowchart illustrating a method of designing a photomask having an enhanced lower resolution auxiliary feature according to an embodiment of the present invention. The method 300 begins with obtaining target design data at step 302. Thereafter, as shown in step 304, initial placement of the lower resolution assist feature AF is performed. Then, in step 306, one or more locations for the changed lower resolution AF positions are identified, and these positions are appropriately determined to place the changed lower resolution assist feature. The method continues at step 308 to place the modified lower resolution assist feature at the location identified at step 306. In step 310, the method calculates whether the result of step 308 meets the process requirements. If the result in step 310 does not meet the process requirements, the method repeats steps 306 and 308, with later steps collectively indicated by reference 312. If the result in step 310 satisfies the process requirements, then the method ends and ends.

According to one embodiment, a method of designing a reticle for a semiconductor device includes defining a first edge of a reticle layout file, the first edge corresponding to a reference feature. The reference feature is used to insert the lower resolution auxiliary feature into the reticle layout file. The lower resolution auxiliary feature may be inserted into the layout file manually or automatically after the location of the auxiliary feature is determined. The lower resolution auxiliary features are not patterned on the substrate and help to form resist features of uniform dimensions.

The lower resolution auxiliary feature is in principle located at an angle with respect to the line containing the first edge, which angle is not 90 degrees (ie, an angle different from 90 degrees). In one embodiment, the reference feature includes one of a target device feature or a second lower resolution assist feature. Additionally, the method may include examining the reticle layout file to determine a location to be changed prior to defining the first edge.

In another embodiment, inserting the lower resolution secondary feature into the reticle layout file using the reference feature may include rotating the reference feature from an initial layout position, defining an edge derived from the rotated reference feature, Determining an location for the insertion point and the sloped lower resolution auxiliary feature using the edge. In one embodiment, the method further comprises inserting the lower resolution assist feature to be substantially parallel to the line comprising the induced edge.

The method further includes defining a second reference feature of the reticle layout file. In this embodiment, the second reference feature is rotated by a predetermined amount and the guided edge is defined from the rotated second reference feature. Furthermore, the reference feature can include one of a first target device feature or a second lower resolution assist feature, and the second reference feature can include one of a second target device feature or a third lower resolution assist feature.

In another embodiment, the first edge of the reference feature can include a first vertex of the reference feature. Thus, inserting the lower resolution auxiliary feature using the reference feature includes inserting the lower resolution auxiliary feature using the first vertex. Moreover, using the criteria may also include defining an induced edge extending from the first vertex and inserting a lower resolution auxiliary feature using the derived edge. Additionally, the derived edge may extend from the first vertex of the reference feature to the second vertex of the reference feature. In the latter case, the reference feature may comprise one of the first target device feature or the second lower resolution assist feature, and the second reference feature may comprise one of the second target device feature or the third lower resolution aid feature. Can be.

In yet another embodiment, the present invention further includes defining a second edge of the reticle layout file. The second edge corresponds to the second reference feature. In such an embodiment, inserting the lower resolution secondary feature using the reference feature includes inserting the lower resolution secondary feature using the reference feature and the second reference feature. The extraordinary lower resolution auxiliary feature makes a second angle with respect to the liner that includes the second edge, the second angle being different from 90 degrees.

According to another embodiment, a method of designing a reticle for a semiconductor device includes defining a first feature of a reticle layout file, defining a second feature of the reticle layout file, and defining a third feature to define the first feature. Connecting to the second feature. The third feature comprises a lower resolution auxiliary feature positioned at a predetermined angle with respect to the first feature and positioned at a second angle with respect to the second feature, each of the first and second angles being different from 90 degrees. Additionally, the third feature may make a third angle between 0 and 90 degrees with respect to the adjacent target device feature.

In the embodiment described in the preceding paragraph, each of the first and second features may include lower resolution auxiliary features. Additionally, the first feature intersects the second feature at the intersection, and defining the third feature to connect the first feature to the second feature includes replacing the intersection with the third feature. In one example of the intersection, the first feature may be substantially perpendicular to the second feature. Additionally, the line that includes the first feature can be parallel to the line that includes the second feature. In the latter case, the first feature may not be on the same straight line with respect to the second feature.

A reticle for a semiconductor device according to another embodiment of the present invention includes defining a target device feature of a reticle layout file, and inserting a lower resolution auxiliary feature into a resin layout file. In this embodiment, the lower resolution auxiliary feature is attached to the target device feature and has an aspect ratio of at least one. The aspect ratio is defined as the ratio of the length of the lower resolution auxiliary feature to the complex of the lower resolution auxiliary feature.

In yet another embodiment, a method of designing a reticle for a semiconductor device includes inserting a lower resolution auxiliary feature in a reticle layout file into an area covered by at least three target device features. In this embodiment, the lower resolution assist feature is located externally defined by the orthogonal projection of any edge of at least three target devices. Moreover, this area does not include any target device feature. In one example, the derived edge is defined from the vertices of at least three target device features, and the derived edge is used to determine where to insert the lower resolution auxiliary feature.

14 is a block diagram of a system for forming a semiconductor device using a reticle having an improved lower resolution auxiliary feature according to an embodiment of the present invention. System 400 includes a light source 402 that generates radiation. Such radiation may be ultraviolet (UV), extreme ultraviolet (DUV), ultra-ultraviolet (EUV), X-ray, electron beam or ion beam. The light source 402 also leads incident light to the reticle 404. Reticle 404 includes a device layout to be imaged on a semiconductor substrate. Reticle 404 also includes a desired target design layout having the enhanced lower resolution assist feature described above in connection with various embodiments. The optical projector 406 focuses incident light diffracted by the reticle 404. The optical projection also images the radiation pattern on the photoresist layer 408 on the semiconductor substrate 410. The resulting irradiated photoresist layer is then removed from the photolithography tool and processed by known techniques to move the pattern onto the semiconductor substrate 410 to form circuit elements. Additional processing may be performed using known techniques to form one or more semiconductor devices into the semiconductor substrate 410.

The semiconductor device substrate 410 may be a single crystal semiconductor wafer, a semiconductor-on-insulating wafer, or another substrate used to form a semiconductor device. The resist layer 408 is typically coated on the wafer and spin on to obtain a relatively flat top surface. Additionally, reticle 404 includes a transparent substrate composed of quartz, glass, and the like, and has the design features and lower resolution assist features described herein.

Embodiments of the present invention can be used for many different types of patterning layers. For example, instead of patterning the conductive layer to make a gate electrode, this embodiment may be used to pattern the contact level or interconnect level of a semiconductor device. Typically, the greatest advantage of this embodiment stands out in the case of forming a masking level which is considered a threshold. In other words, the critical masking level is designed to have features close to the resolution limit of the lithography tool. Although embodiments of the invention may be used in non-critical layers, such as implant masks, the inventive concept may be extended to implant masks as needed. In addition, embodiments of the present invention may be incorporated to be used in a phase shifting mask. In this example, the phase shifting material may be formed adjacent to the lower resolution assist feature.

In the foregoing, the invention has been described with reference to various embodiments. However, one of ordinary skill in the art appreciates that various changes and modifications can be made without departing from the scope of the present invention as set forth in the claims below. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be within the scope of the present invention.

With regard to specific embodiments, solutions to the advantages, other advantages, and problems of the present invention have been described. However, the advantages, advantages, solutions to problems, and other element (s) that cause or emphasize any advantage, advantage, or solution, are deemed important, required or indispensable in any or all claims, or are not required. do. As used herein, the term "comprising" and variations thereof are not intended to be nonexclusive or include non-exclusive such as processes, methods, objects or devices that include a list of elements unique to such processes, methods, objects and devices. It is intended to cover the inclusion.

Claims (34)

A method of designing a reticle for a semiconductor device, Defining a first edge of a reticle layout file, the first edge corresponding to a reference feature; Inserting a lower resolution auxiliary feature into the reticle layout file using the reference feature, Wherein the lower resolution auxiliary feature is at an angle other than 90 degrees with respect to the line including the first edge. The method of claim 1, Wherein the reference feature comprises one of a target device feature or a second lower resolution auxiliary feature. The method of claim 1, Using the reference feature Rotating the reference feature; Defining an edge derived from the rotated reference feature; Inserting the lower resolution auxiliary feature using the derived edge How to include. The method of claim 3, Using the reference feature further comprises inserting the lower resolution auxiliary feature substantially parallel to a line comprising the derived edge. The method of claim 3, Defining a second reference feature of the reticle layout file; Rotating the second reference feature; The derived edge is further defined from the rotated second reference feature. The method of claim 5, The reference feature comprises one of a first target device feature or a second resolution resolution feature, and the second reference feature comprises one of a second target device feature or a third lower resolution assist feature. The method of claim 1, Wherein the first edge comprises a first vertex, and inserting the lower resolution subfeature using the reference feature comprises inserting the lower resolution subfeature using the first vertex. The method of claim 7, wherein The method using the reference feature, Defining an induced edge extending from the first vertex; Inserting the lower resolution auxiliary feature using the derived edge How to include more. The method of claim 8, The derived edge extends from a fraud first vertex to a second vertex of a second reference feature, wherein the reference feature includes one of a first target device feature or a second lower resolution auxiliary feature, and the second reference feature is And one of the second target device feature or the third lower resolution auxiliary feature. The method of claim 1, Defining a second edge of the reticle layout file, the second edge corresponding to a second reference feature, and inserting the lower resolution auxiliary feature using the reference feature comprises: the reference feature and the Inserting the lower resolution secondary feature using a second baseline feature. The method of claim 10, The lower resolution auxiliary feature attains a second angle that is not 90 degrees with respect to the line including the second edge. The method of claim 1, Examining the reticle layout file to determine a location to be changed prior to defining the first edge. As a method of designing a reticle for a semiconductor device, Defining a first feature of the reticle layout file; Defining a second feature of the reticle layout file; Defining a third feature to connect the first feature to the second feature, The third feature includes a lower resolution subfeature, comprises a first angle with respect to the first feature, a second angle with respect to the second feature, and each of the first and second angles is not 90 degrees. Way. The method of claim 13, Each of the first and second features comprises a lower resolution auxiliary feature. The method of claim 13, The first feature intersecting the second feature at an intersection, and defining the third feature to connect the first feature to the second feature includes replacing the intersection with the third feature. How to. The method of claim 15, The first feature at the intersection is substantially orthogonal to the second feature. The method of claim 13, And the line comprising the first feature is parallel to the line comprising the second feature. The method of claim 17, And the first feature is not co-linear with the second feature. The method of claim 13, At least one of the first and second features includes a target device feature. The method of claim 13, Wherein the third feature forms a third angle with respect to an adjacent target device feature, wherein the third angle is greater than 0 degrees and less than 90 degrees. As a method of designing a reticle for a semiconductor device, Defining a target device feature in the reticle layout file; Inserting subresolution complementary features into the reticle layout file, The lower resolution auxiliary feature is attached to the target device feature and has an aspect ratio of at least one, wherein the aspect ratio is a ratio of the length of the lower resolution auxiliary feature to the width of the lower resolution auxiliary feature. As a method of designing a reticle for a semiconductor device, Inserting a lower resolution secondary feature in the reticle layout file into an area covered by the at least three target device features, The lower resolution auxiliary feature is outside an area defined by orthogonal projection of any edge of the at least three target devices, and the area does not include a target device feature. The method of claim 22, Inserting the lower resolution auxiliary feature Defining edges derived from the at least three target device features; Inserting the lower resolution auxiliary feature using the derived edge. As a method of forming a semiconductor device, Forming a resist layer on the substrate, Exposing the resist layer using a reticle having a first lower resolution auxiliary feature, wherein the first lower resolution auxiliary feature refers to a corresponding one of a target device feature or a second lower resolution auxiliary feature, wherein The resolution assist feature is positioned at an angle other than 90 degrees with respect to the line including the corresponding one first edge of the target device feature or the second lower resolution aid feature; Developing the layer after the exposing step to define at least one device region of the semiconductor device How to include. The method of claim 24, The first lower resolution auxiliary feature is located with reference to the corresponding one of the target device feature or the second lower resolution auxiliary feature and is referenced with a corresponding one of the second target device feature or the third lower resolution auxiliary feature. Way. The method of claim 25, Wherein the first lower resolution subfeature is at a second angle other than 90 degrees with respect to the line comprising the second edge of the second target device feature or the third lower resolution subfeature. As a method of forming a semiconductor device, Forming a resist layer on the substrate, Exposing the resist layer using a reticle having a lower resolution auxiliary feature, wherein the lower resolution auxiliary feature connects a first feature of the reticle to a second feature of the reticle, wherein the lower resolution auxiliary feature is a first feature A first angle with respect to the second feature, a second angle with respect to the second feature, and the first and second angles are each not 90 degrees; Developing the layer after the exposing step to define at least one device region of the semiconductor device How to include. The method of claim 27, Wherein the first feature comprises a second lower resolution sub feature and the second feature comprises a third lower resolution sub feature. The method of claim 27, And the line comprising the first feature is parallel to the line comprising the second feature. The method of claim 29, And the first feature is not collinear with the second feature. The method of claim 27, At least one of the first and second features includes a target device feature. The method of claim 27, Wherein the lower resolution auxiliary feature makes a third angle with respect to an adjacent target device feature, wherein the third angle is greater than 0 degrees and less than 90 degrees. As a method of forming a semiconductor device, Forming a resist layer on the substrate, Exposing the resist layer using a reticle having a lower resolution auxiliary feature, wherein the lower resolution auxiliary feature is attached to a target device feature of the reticle and has an aspect ratio of at least 1, the aspect ratio of the lower resolution auxiliary feature The length and width of the lower resolution subfeatures-and, After the exposing step, developing the layer to define at least one device region of the semiconductor device How to include. As a method of forming a semiconductor device, Forming a resist layer on the substrate, Exposing the resist layer using a reticle having a lower resolution subfeature within an area of the reticle covered by at least three target device features; After the exposing step, developing the layer to define at least one device region of the semiconductor device Including, The lower resolution assist feature is outside an area defined by orthogonal projection of an edge of the at least three target devices, the area not including a target device feature.

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