KR20060013149A - Liquid crystal display - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, which is a liquid crystal display device that compensates a kickback voltage by modifying a gate signal, and includes a gate clock signal and an output enable signal. First and second switching elements outputting an on voltage and a gate signal, a capacitor charging an output voltage from the first switching element, a third switching element outputting a voltage charged to the capacitor according to an output signal of the OR gate, A compensation circuit including a fourth switching element for intermitting the outputs of the second and third switching elements in accordance with a gate signal, and a fifth switching element for outputting a gate-off voltage in accordance with the gate signal. Therefore, the magnitude of the kickback voltage can be reduced by changing the waveform of the gate signal and applying it to the gate line. In addition, since the gate driver includes the compensation circuit, the number of components and the size of the liquid crystal display may be reduced, and the cost may be reduced.

Liquid Crystal Display, Flicker, Kickback Voltage, Gate Drive Circuit, Capacitor, Discharge

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a timing diagram illustrating a gate control signal and a compensation gate signal of a liquid crystal display according to another exemplary embodiment of the present invention.

4 is a kickback voltage compensation circuit of a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 5 is a timing diagram illustrating an operation of the kickback voltage compensation circuit shown in FIG. 4.

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of compensating kickback voltage.

A typical liquid crystal display (LCD) includes two display panels provided with pixel electrodes and a common electrode, and a liquid crystal layer having dielectric anisotropy interposed therebetween. The pixel electrodes are arranged in a matrix and connected to switching elements such as thin film transistors (TFTs) to receive data voltages one by one in sequence. The common electrode is formed over the entire surface of the display panel and receives a common voltage. The pixel electrode, the common electrode, and the liquid crystal layer therebetween form a liquid crystal capacitor, and the liquid crystal capacitor becomes a basic unit that forms a pixel together with a switching element connected thereto. In such a liquid crystal display, a voltage is applied to two electrodes to generate an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image.

However, when the thin film transistor is switched from the on state to the off state, the gate electrode voltage decreases rapidly, which is a voltage applied to the pixel electrode due to a coupling phenomenon caused by parasitic capacitance between the gate electrode and the drain electrode. To bring it down. This phenomenon is called kickback phenomenon, and the voltage drawn down is called kickback voltage.

On the other hand, in order to prevent deterioration caused by the application of an electric field in one direction to the liquid crystal layer for a long time, the polarity of the data voltage with respect to the common voltage is inverted frame by frame, row, or pixel. At this time, due to the influence of the kickback voltage, the positive and negative polarities (-) of the data voltage become asymmetrical, causing flicker.

In order to prevent such flicker, the kickback voltage is compensated by arranging various elements capable of compensating the kickback voltage on a printed circuit board (PCB) of the liquid crystal display panel. As such elements are added, the cost of the liquid crystal display is increased, and the size of the liquid crystal display is increased because the PCB unit requires a space for separately arranging the elements. In addition, the kickback voltage is not compensated by the deviation of the driving IC.

Accordingly, an object of the present invention is to provide a liquid crystal display device which can reduce cost and reduce size by compensating kickback voltage without adding additional devices.

According to an exemplary embodiment of the present invention, a liquid crystal display that compensates a kickback voltage by modifying a gate signal includes an OR gate receiving a gate clock signal and an output enable signal, and an output signal of the OR gate. First and second switching elements outputting a gate on voltage and the gate signal, a capacitor charging an output voltage from the first switching element, and a voltage charged to the capacitor according to an output signal of the OR gate. A compensation circuit including a third switching device configured to control the output of the second and third switching devices according to the gate signal, and a fifth switching device outputting a gate-off voltage according to the gate signal. It includes.

When the output signal of the OR gate is high level, the first and second switching devices are turned on and the third switching device is turned off. When the output signal of the OR gate is low level, the first and second switching devices are May be turned off and the third switching element may be turned on.

If the gate signal is the gate on voltage, the fourth switching device is turned on and the fifth switching device is turned off. If the gate signal is the gate off voltage, the fourth switching device is turned off and the fifth switching is performed. The device can be turned on.

When the gate clock signal and the output enable signal are at a low level, the compensation circuit may output a voltage that is exponentially decreased from the gate on voltage to a predetermined voltage level.

When the gate clock signal is high level and the output enable signal is low level, the compensation circuit may output the gate on voltage.

The compensation circuit may output the gate off voltage when the gate clock signal and the output enable signal are high level, or when the gate clock signal is low level and the output enable signal is high level.

The semiconductor device may further include a gate driver including an IC chip and including the compensation circuit.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A liquid crystal display according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels connected to the plurality of display signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. .

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a data line D for transmitting a data signal. ₁ -D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _n , D ₁ -D _m , and a liquid crystal capacitor C _LC and a storage capacitor C _ST connected thereto. It includes. The holding capacitor C _ST can be omitted as necessary.

The switching element Q, such as a thin film transistor, is provided in the lower panel 100, and the control terminal and the input terminal are three-terminal elements, respectively, with gate lines G ₁ -G _n and data lines D ₁ -D _m . The output terminal is connected to a liquid crystal capacitor (C _LC ) and a holding capacitor (C _ST ).

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST , which serves as an auxiliary part of the liquid crystal capacitor C _LC , is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage V _com is applied to this separate signal line. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

On the other hand, to implement color display, each pixel uniquely displays one of the three primary colors (spatial division) or each pixel alternately displays the three primary colors over time (time division) so that the desired color can be selected by the spatial and temporal sum of these three primary colors. To be recognized. 2 shows that each pixel includes a red, green, or blue color filter 230 in a region corresponding to the pixel electrode 190 as an example of spatial division. Unlike FIG. 2, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the two display panels 100 and 200 of the liquid crystal panel assembly 300.

The gray voltage generator 800 generates two sets of gray voltages related to the transmittance of the pixel. One of the two sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to receive a gate signal formed by a combination of a gate on voltage V _on and a gate off voltage V _off from the outside. It is applied to the gate lines G ₁ -G _n and may be formed of a plurality of integrated circuits.

The data driver 500 is connected to the data lines D ₁ -Dm of the liquid crystal panel assembly 300, selects a gray voltage from the gray voltage generator 800, and applies the gray voltage to the pixel as a data signal. It may be made of.

The plurality of gate driving integrated circuits or data driving integrated circuits may be mounted in a chip carrier package (TCP) (not shown) in the form of a chip to attach the TCP to the liquid crystal panel assembly 300, or may not use TCP. These integrated circuit chips may be directly attached onto a glass substrate (chip on glass, COG mounting method), and these integrated circuits may be directly formed on the liquid crystal panel assembly 300 together with the thin film transistors of the pixel.

The signal controller 600 controls operations of the gate driver 400 and the data driver 500.

Next, the display operation of the liquid crystal display will be described in more detail.

The signal controller 600 may control the input image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 properly processes the image signals R, G, and B according to the operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate control signal. After generating the CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are processed by the data driver 500. Export to

The gate control signal (CONT1) includes a gate-on voltage vertical synchronization start signal (STV) for instructing the start of output of the (V _on), the gate-on voltage gated clock signal that controls the output timing of the (V _on) (CPV) and the gate-on An output enable signal OE or the like that defines the duration of the voltage V _on .

The data control signal CONT2 includes a horizontal synchronization start signal STH indicating the start of input of the image data DAT, a load signal LOAD for applying a corresponding data voltage to the data lines D ₁ -D _m , and a common voltage. The inversion signal RVS and the data clock signal HCLK for inverting the polarity of the data voltage with respect to (V _com ) (hereinafter referred to as the "polarity of the data voltage by reducing the polarity of the data voltage with respect to the common voltage"). Include.

The data driver 500 sequentially receives and shifts the image data DAT for one row of pixels according to the data control signal CONT2 from the signal controller 600, and the gray voltage from the gray voltage generator 800. By selecting the gray scale voltage corresponding to each of the image data DAT, the image data DAT is converted into the corresponding data voltage and then applied to the corresponding data line D ₁ -D _m .

The gate driver 400 applies a high level signal of the gate signal V _gn to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600. The switching element Q connected to (G ₁ -G _n ) is turned on, and accordingly, a data voltage applied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

The difference between the data voltage applied to the pixel and the common voltage V _com is shown as the charging voltage of the liquid crystal capacitor C _LC , that is, the pixel voltage. The arrangement of the liquid crystal molecules varies according to the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

After one horizontal period (or “1H”) (one period of the horizontal sync signal H _sync , the data enable signal DE, and the gate clock CPV), the data driver 500 and the gate driver 400 are next. The same operation is repeated for the pixels in the row. In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data voltages to all the pixels. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame ("frame inversion). "). In this case, the polarity of the data voltage flowing through one data line may be changed (“line inversion”) within one frame or the polarity of the data voltage applied to one pixel row may be different according to the characteristics of the inversion signal RVS ( "Dot reversal").

Next, a liquid crystal display according to another exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 to 5.

3 is a timing diagram illustrating a gate control signal and a compensation gate signal of a liquid crystal display according to another exemplary embodiment of the present invention, and FIG. 4 is a kickback voltage compensation circuit of the liquid crystal display according to another exemplary embodiment of the present invention. FIG. 5 is a timing diagram illustrating an operation of the kickback voltage compensation circuit shown in FIG. 4.

Since the liquid crystal display according to another exemplary embodiment of the present invention is substantially the same as the liquid crystal display shown in FIG. 1, detailed description thereof will be omitted, and the same reference numerals are assigned to the same elements.

The gate driver 400 of the liquid crystal display according to the exemplary embodiment of the present invention includes the kickback voltage compensation circuit 450 shown in FIG. 4. The kickback voltage compensation circuit 450 generates a compensation gate signal capable of reducing the magnitude of the kickback voltage based on the gate signal including the gate on voltage V _on , the gate off voltage V _off , and a combination thereof. Applied to the gate line. Hereinafter, for convenience of explanation, the compensation gate signal applied to the n-th gate line G _n is referred to as V _gn ', and the n-th gate signal corresponding thereto is referred to as V _gn .

As shown in FIG. 3, the compensation gate signal V _g1 '-V _gn ' of the liquid crystal display according to another exemplary embodiment of the present invention has a high gate clock signal CPV and an output enable signal OE. At the low level, the gate-on voltage (V _on ) is maintained. When the gate clock signal CPV and the output enable signal OE are both at the low level, the compensation gate signal V _g1 '-V _gn ' is _adjusted from the gate on voltage V _on to the predetermined voltage V _c1 . After the voltage level decreases exponentially, the voltage level drops to the gate-off voltage V _off when the output enable signal OE becomes high. When the compensation gate signals V _g1 '-V _gn ' are applied to the gate lines G ₁ -G _n , the variation range from the predetermined voltage V _c1 to the gate off voltage V _off is changed to the gate on voltage V. _on ), which is less than the variation from gate off voltage (V _off ) to reduce the magnitude of the kickback voltage.

This kickback voltage compensation circuit 450 will be described in detail with reference to FIG. 4.

As shown in FIG. 4, the kickback voltage compensation circuit 450 includes an OR gate OR, two NOT gates NOT1 and NOT2, six transistors TR1, TR2, TR3, TR4, TR5, and TR6. Resistors (R1, R2) and capacitor (C).

The OR gate OR is connected to the output enable signal OE and the gate clock signal CPV, and receives them as an input signal to perform an OR operation.

The control terminals of the transistors TR1 and TR3 are connected to the OR gate OR, the output terminal is connected to the transistor TR2, and the input terminals are the gate on voltage V _on and the gate signal V _gn, respectively. Is connected to. The control terminal of the transistor TR2 is connected to the OR gate OR through the NOT gate NOT1, and the input terminal and the output terminal are connected to the transistors TR1 and TR2, respectively.

The control terminal of the transistor TR4 is connected to the high level voltage VCC, the input terminal is connected to the gate signal V _gn through the resistor R1, and the output terminal is connected through the resistor R2. It is grounded. Transistor TR4 forms a voltage divider together with resistors R1 and R2.

The control terminal of the transistor TR5 is connected to the output terminal of the transistor TR4, the input terminal is connected to the output terminal of the transistors TR2 and TR3, and the compensation gate signal V _gn 'is supplied through the output terminal. Output The control terminal of the transistor TR6 is connected to the output terminal of the transistor TR4 through the NOT gate NOT2, the input terminal is connected to the gate off voltage V _off , and the compensation gate signal ( Outputs V _gn ')

The transistors TR1, TR2, TR3, TR4, TR5, and TR6 function as switching elements for connecting the input terminal and the output terminal in accordance with the voltage level applied to the control terminal.

One end of the capacitor C is connected between the transistors TR1 and TR2, and the other end is grounded. The capacitor C is charged through the transistor TR1 to charge the gate-on voltage V _on , and is charged through the transistor TR2. Discharge the voltage V _c .

Next, the operation of the kickback voltage compensation circuit 450 will be described in detail with reference to FIG. 5.

The kickback voltage compensation circuit 450 is divided into four sections T1, T2, T3, and T4 according to the gate clock signal CPV and the output enable signal OE.                     

First, when the gate clock signal CPV and the output enable signal OE are both at a high level, the period T1 starts. In this section T1, since the OR gate OR outputs a high level voltage, the transistors TR1 and TR3 are turned on and the transistor TR2 is turned off. As a result, the capacitor C is charged with the gate-on voltage V _on . On the other hand, since the gate signal V _gn is the gate-off voltage V _off in this period T1, the transistor TR4 outputs a low level voltage. Accordingly, transistor TR5 is turned off and transistor TR6 is turned on. Therefore, the gate off voltage V _off is output as the compensation gate signal V _gn 'through the transistor TR6.

Then, the output enable signal OE becomes low level, and the period T2 starts. In this section T2, the OR gate OR outputs a high level voltage, so that the transistors TR1 and TR3 remain turned on, and the transistor TR2 remains turned off. Capacitor C also continues to charge gate-on voltage V _on . In this period T2, the gate signal V _gn is the gate-on voltage V _on , so the transistor TR4 outputs a high level voltage. Accordingly, transistor TR5 is turned on and transistor TR6 is turned off. Therefore, the gate-on voltage V _on is output as the compensation gate signal V _gn 'through the transistors TR3 and TR5.

Thereafter, the gate clock signal CPV goes low and the period T3 starts.

In this period T3, the OR gate OR outputs a low level voltage, so the transistors TR1 and TR3 are turned off and the transistor TR2 is turned on. In this period T3, the gate signal V _gn maintains the gate-on voltage V _on , so that the transistor TR4 continues to output a high level voltage, and accordingly, the transistor TR5 remains turned on. The transistor TR6 remains turned off. Therefore, the voltage V _c charged in the capacitor C is discharged through the transistors TR2 and TR5 and output as the compensation gate signal V _gn '. The voltage V _c charged in the capacitor C has a gate-on voltage Von as an initial voltage and decreases exponentially to reach a predetermined voltage level V _c1 at the end of the period T3. This voltage level V _c1 is determined according to the capacitance of the capacitor C.

If the output enable signal OE reaches a high level after a predetermined time elapses after the discharge starts, the section T4 starts. In this period T4, the OR gate OR outputs a high level voltage so that the transistors TR1 and TR3 are turned on and the transistor TR2 is turned off. Accordingly, the capacitor C is again charged with the gate-on voltage V _on . On the other hand, since the gate signal V _gn changes to the gate-off voltage V _off in this period T4, the transistor TR4 outputs a low level voltage. Accordingly, transistor TR5 is turned off and transistor TR6 is turned on. Therefore, the gate off voltage V _off is output as the compensation gate signal V _gn 'through the transistor TR6.

According to the compensation gate signal V _gn ′ of the liquid crystal display according to another exemplary embodiment of the present invention, the voltage applied to the gate line varies from the predetermined voltage level V _c1 to the gate off voltage V _off . Relatively small differences reduce the amount of kickback voltage.

As described above, the kickback voltage compensation circuit according to an exemplary embodiment of the present invention can reduce the magnitude of the kickback voltage by modifying the waveform of the gate signal and applying it to the gate line.

In addition, the gate driver includes the kickback voltage compensation circuit, thereby reducing the number of components and the size of the liquid crystal display and reducing the cost.

 Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (7)

A liquid crystal display device that compensates a kickback voltage by modifying a gate signal. OR gate receiving the gate clock signal and the output enable signal, First and second switching devices configured to output a gate on voltage and the gate signal according to an output signal of the OR gate, A capacitor for charging an output voltage from the first switching element, A third switching device for outputting a voltage charged in the capacitor according to the output signal of the OR gate, A fourth switching device intermittently outputting the second and third switching devices according to the gate signal, and A compensation circuit including a fifth switching device configured to output a gate off voltage according to the gate signal Liquid crystal display comprising a. In claim 1, When the output signal of the OR gate is high level, the first and second switching devices are turned on and the third switching device is turned off, and the output signal of the OR gate is low level and the first and second switching devices are Is turned off and the third switching element is turned on. In claim 2, If the gate signal is the gate on voltage, the fourth switching device is turned on and the fifth switching device is turned off. If the gate signal is the gate off voltage, the fourth switching device is turned off and the fifth switching is performed. The device is turned on. In claim 1, And the compensation circuit outputs a voltage that decreases exponentially from the gate on voltage to a predetermined voltage level when the gate clock signal and the output enable signal are at a low level. In claim 4, And the compensation circuit outputs the gate on voltage when the gate clock signal is high level and the output enable signal is low level. In claim 5, And the compensation circuit outputs the gate off voltage when the gate clock signal and the output enable signal are high level, or when the gate clock signal is low level and the output enable signal is high level. In claim 1, And a gate driver including an IC chip and including the compensation circuit.

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