KR20060012847A - Semiconductor memory device and arrangement method of the same - Google Patents

Abstract

The present invention discloses a semiconductor memory device and a method of arranging the device. The apparatus includes a memory cell array having a plurality of memory cells accessed in response to a plurality of word line selection signals and a plurality of column selection signals, a row decoder for decoding a row address and generating a plurality of word line selection signals; And a column decoder for decoding a column address to generate a plurality of column select signals, the row and column decoders having a plurality of inverters and a plurality of NAND gates, each of the plurality of inverters having at least one first pull-up. A transistor and a first pull-down transistor, each of the plurality of NAND gates having at least two or more second pull-up transistors and at least two or more second pull-down transistors, the first and second pull-up transistors and the first And second pull-down transistors stacked on at least two layers. It is characterized by. Therefore, it is possible to reduce the layout area of the peripheral circuit by reducing the layout area of the memory cell array, thereby reducing the overall layout area.

Description

Semiconductor memory device and arrangement method of the same

1 is a block diagram showing the configuration of a general static semiconductor memory device.

FIG. 2 is a block diagram showing the configuration of an embodiment of the row decoder or column decoder shown in FIG.

3A to 3D show an example circuit diagram of a static memory cell, an inverter constituting a peripheral circuit, a NAND gate, and a NOR gate, respectively.

4A to 4D conceptually show an arrangement of an example of an inverter, a NAND gate, and transistors constituting a NOR gate that constitute a static memory cell and a peripheral circuit of a conventional semiconductor memory device in FIG. 3A, respectively.

5A to 5D conceptually show arrangements of other examples of transistors constituting an inverter, a NAND gate, and a NOR gate of a static memory cell and a peripheral circuit of a conventional semiconductor memory device, respectively.

6A to 6D conceptually show arrangements of still another example of transistors constituting an inverter, a NAND gate, and a NOR gate of a static memory cell and a peripheral circuit of a conventional semiconductor memory device, respectively.

7A to 7D conceptually show an arrangement of a first embodiment of transistors constituting an inverter, a NAND gate, and a NOR gate of a static memory cell and a peripheral circuit of the semiconductor memory device of the present invention, respectively.

8A to 8D conceptually show an arrangement of a second embodiment of transistors constituting an inverter, a NAND gate, and a NOR gate of a static memory cell and a peripheral circuit of the semiconductor memory device of the present invention, respectively.

9A to 9D conceptually show an arrangement of a third embodiment of transistors constituting an inverter, a NAND gate, and a NOR gate of a static memory cell and a peripheral circuit of the semiconductor memory device of the present invention, respectively.

10A to 16A and 10D to 16D are plan views illustrating arrangements of memory cells, inverters, NAND gates, and NOR gates according to embodiments of the present invention.

17A and 17B are cross-sectional views showing the structure of the memory cell of the embodiment of the present invention in accordance with the lines II ′ and II-II ′ of FIGS. 10A to 16A.

18 to 20 are cross-sectional views showing the structure of the memory cell of the embodiment of the present invention, taken along the line X-X 'in FIGS. 10B to 16B, 10C to 16C, and 10D to 16D.

21A and 21B show the stacked structure of the first embodiment of the memory cell array and the peripheral circuit of the present invention.

22A and 22 show the stacked structure of the second embodiment of the memory cell array and the peripheral circuit of the present invention.

23A and 23 show a stacked structure of a third embodiment of a memory cell array and a peripheral circuit of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device capable of reducing layout area and a method of arranging the device.

In general, a semiconductor memory device is composed of a memory cell array having a plurality of memory cells for storing data, and a peripheral circuit for controlling data input / output to / from the memory cell array.

The static memory cell is composed of a plurality of transistors, and the dynamic memory cell is composed of one transistor and one capacitor. The peripheral circuit includes an inverter, a NAND gate, and a NOR gate, and each of these gates includes transistors.

A typical memory cell and a peripheral circuit place all of a plurality of transistors in the same layer on a semiconductor substrate. Therefore, the layout area increases as the capacity of the memory cell array, that is, the number of memory cells, increases, thereby increasing the chip size.

Therefore, even if the capacity of the memory cell array is increased, efforts are being made not to increase the layout area.As a part of such efforts, transistors constituting one memory cell are stacked to reduce the layout area of the memory cell array. The way came out.

However, reducing the layout area of the memory cell array does not reduce the overall layout area of the semiconductor memory device. Therefore, as the layout area of the memory cell array is reduced, the layout area of the peripheral circuit must also be reduced to reduce the layout area. .

An object of the present invention is to provide a semiconductor memory device that can reduce the overall layout area of the device by reducing the layout area of the peripheral circuit in accordance with the reduction of the layout area of the memory cell array.

Another object of the present invention is to provide a method of arranging a semiconductor memory device for achieving the above object.

A first aspect of the semiconductor device of the present invention comprises a plurality of inverters having at least one first pull-up transistor and a first pull-down transistor and inverting and outputting an input signal, respectively, and at least two or more second pull-up transistors and A plurality of NAND gates each having two pull-down transistors, each of which generates an output signal of a “high” level if at least one of the at least two input signals is at a “low” level; The first pull-up and first pull-down transistors and the at least two or more second pull-up and second pull-down transistors are stacked on at least two layers.

A second aspect of the semiconductor device of the present invention includes a plurality of inverters having at least one first pull-up transistor and a first pull-down transistor, each of which inverts an input signal and outputs at least two second pull-up transistors and a second one. A plurality of NAND gates having pull-down transistors, each of which generates an output signal of a “high” level if at least one of the at least two input signals is at a “low” level, and at least two or more thirds A plurality of NOR gates having pull-up transistors and third pull-down transistors, each of which generates an output signal of a “high” level if at least two or more input signals are all “low” level; Pull-up and pull-down transistors, said at least two or more second pull-up and second pull-down transistors, and said at least At least two third pull-up transistors and third pull-down characterized in that the stacking arrangement to the at least two or more layers.

The pull-up and first, second, and third pull-up transistors of the first and second types of semiconductor devices are PMOS transistors, and the pull-down and first, second, and third pull-down transistors are NMOS transistors. It is done.

The transistors arranged in one layer of at least two or more layers of the first and second aspects are bulk transistors, and the transistors arranged in two or more layers are thin film transistors.

The first layer of the first and second types mixes the pull-up, first, second, and third pull-up transistors with transistors of some of the pull-down, first, second, and third pull-down transistors. And the pull-up, first, second, and third pull-up transistors are disposed only on the second or more layers, or only the pull-down, first, second, and third pull-down transistors are disposed. Characterized in that.                         

A first aspect of the semiconductor memory device of the present invention for achieving the above object is a memory cell array having a plurality of memory cells that are accessed in response to a plurality of word line select signals and a plurality of column select signals, row address A row decoder that decodes the plurality of word line selection signals to generate the plurality of word line selection signals, and a column decoder that decodes a column address to generate the plurality of column selection signals, wherein the row decoder includes a plurality of inverters, Each of the plurality of inverters includes at least one pull-up transistor and a pull-down transistor, and the pull-up and pull-down transistors are stacked on at least two layers.

The column (row) decoder includes a plurality of inverters, each of the plurality of inverters includes at least one pull-up transistor and a pull-down transistor, and the pull-up and pull-down transistors are stacked on at least two layers. It is done.

The plurality of memory cells includes a plurality of MOS transistors, wherein the plurality of MOS transistors are stacked on the at least two layers, wherein the pull-up transistor is a PMOS transistor, and the pull-down transistors are NMOS transistors. It is characterized by. The transistors disposed on one layer of the at least two layers are bulk transistors, and the transistors disposed on two or more layers are thin film transistors.

It is possible to mix and arrange some transistors of the pull-up and pull-down transistors in the first layer, and only the pull-up transistors or only the pull-down transistors are arranged in each of the two or more layers.

A second aspect of the semiconductor memory device of the present invention for achieving the above object is a memory cell array having a plurality of memory cells that are accessed in response to a plurality of word line select signals and a plurality of column select signals, row address A row decoder that decodes and generates the plurality of word line selection signals, and a column decoder that decodes a column address and generates the plurality of column selection signals, wherein the row (column) decoder includes a plurality of inverters and a plurality of inverters; And NAND gates, each of the plurality of inverters having at least one first pull-up transistor and a first pull-down transistor, each of the plurality of NAND gates having at least two second pull-up transistors and at least two Second and second pull-down transistors, and the first and second pull-ups The transistors and the first and second pull-down transistors are stacked on at least two layers.

The column decoder has a plurality of inverters and a plurality of NAND gates, each of the plurality of inverters having at least one first pull-up transistor and a first pull-down transistor, each of the plurality of NAND gates. Has at least two or more second pull-up transistors and at least two or more second pull-down transistors, wherein the first and second pull-up transistors and the first and second pull-down transistors are stacked on at least two layers. It is characterized by.

The plurality of memory cells may include a plurality of MOS transistors, and the plurality of MOS transistors may be stacked on the at least two layers, and the first and second pull-up transistors may be PMOS transistors. The first and second pulldown transistors are characterized in that they are NMOS transistors. The transistors disposed on one layer of the at least two layers are bulk transistors, and the transistors disposed on two or more layers are thin film transistors.

It is possible to mix and arrange the transistors of the first pull-up and the first pull-down transistors and a part of the second pull-up and the second pull-down transistors in the first layer, and the first pull-up and the second layer in each of the two or more layers. Only pull-up transistors are disposed, or only the first pull-down and second pull-down transistors are disposed.

A third aspect of the semiconductor memory device of the present invention for achieving the above object is a memory cell array having a plurality of memory cells that are accessed in response to a plurality of word line select signals and a plurality of column select signals, and a row address A row decoder that decodes the plurality of word line selection signals to generate the plurality of word line selection signals, a column decoder which decodes a column address to generate the plurality of column selection signals, and a controller for controlling input and output of data to the memory cell array. A peripheral circuit, the peripheral circuit having a plurality of inverters, a plurality of NAND gates, and a plurality of NOR gates, each of the plurality of inverters having at least one first pull-up transistor and a first pull-down transistor; And at least two of the plurality of NAND gates. Second pull-up transistors and at least two or more second pull-down transistors on the substrate, each of the plurality of NOR gates having at least three or more third pull-up transistors and at least three or more third pull-down transistors; The first, second, and third pull-up transistors and the first, second, and third pull-down transistors are stacked on at least two layers.

The plurality of memory cells may include a plurality of MOS transistors, and the plurality of MOS transistors may be stacked on the at least two layers, and the first, second, and third pull-up transistors may be PMOS transistors. The first, second, and third pull-down transistors are NMOS transistors. The transistors disposed on one layer of the at least two layers are bulk transistors, and the transistors disposed on two or more layers are thin film transistors.

In the first layer, it is possible to mix and arrange the transistors of the first pull-up and the first pull-down transistors, the second pull-up and the second pull-down transistors, and some of the third pull-up and the third pull-down transistors. Each of the above layers may include only the first pull-up, second pull-up, and third pull-up transistors, or only the first pull-down, second pull-down, and third pull-down transistors.

A first aspect of the method of disposing a semiconductor memory device of the present invention for achieving the above another object is two transfer transistors, two first pull-up transistors, and two that constitute each of a plurality of memory cells of a memory cell array. The first pull-down transistors are stacked on at least two layers, and each of the at least one second pull-up transistors, the second pull-down transistors, and the plurality of NAND gates configuring each of the plurality of inverters of the peripheral circuit. At least two or more third pull-up transistors and third pull-down transistors are stacked on the at least two layers.

The first, second and third pull-up transistors are PMOS transistors, and the transfer, first, second and third pull-down transistors are NMOS transistors, and are disposed in one layer of the at least two layers. The transistor is a bulk transistor, and the transistors arranged on two or more layers are thin film transistors.

Transistors disposed on one layer of the at least two layers of the peripheral circuit may include the second pull-up and third pull-up transistors, the second pull-down and the third pull-up transistors, regardless of the type of the transistor disposed on the first layer of the memory cell. It is possible to mix and arrange some of the pull-down transistors, the second pull-up and the third having the same shape as that of the transistor disposed in each of the two or more layers of the at least two or more layers of the peripheral circuit. Only the pull-up transistors are disposed or only the second pull-down and third pull-down transistors are disposed.

A second aspect of the method of disposing a semiconductor memory device of the present invention for achieving the above another object is two transfer transistors, two first pull-up transistors, and two that constitute each of a plurality of memory cells of a memory cell array. The first pull-down transistors are stacked on at least two layers, and each of the at least one second pull-up transistors, the second pull-down transistors, and the plurality of NAND gates, which constitute each of the plurality of inverters of the peripheral circuit, are disposed. At least two or more third pull-up transistors and third pull-down transistors, and at least two or more fourth pull-up transistors and fourth pull-down transistors constituting each of the plurality of NOR gates are stacked on the at least two layers. Characterized in that.

Wherein the first, second, third, and fourth pull-up transistors are PMOS transistors, and the transfer, first, second, third, and fourth pull-down transistors are NMOS transistors. The transistors arranged in one layer of the above layers are bulk transistors, and the transistors arranged in two or more layers are thin film transistors.

Transistors disposed on one layer of the at least two layers of the peripheral circuit may include the second pull-up, third pull-up, and fourth pull-up transistors and the second pull-up transistors irrespective of the type of the transistor disposed on the first layer of the memory cell. It is possible to mix and arrange some of the pull-down, third pull-down and fourth pull-down transistors, and the same shape as that of the transistor disposed in each of two or more layers of the at least two or more layers of the peripheral circuit. Only the second pull-up, the third pull-up and the fourth pull-up transistors having a second pull-down, the third pull-down and the fourth pull-down transistors are arranged.

Hereinafter, referring to the accompanying drawings, a conventional semiconductor memory device will be described before describing the semiconductor memory device of the present invention and a method of arranging the device.

1 is a block diagram showing a configuration of a general static semiconductor memory device, which includes a memory cell array 10, a row decoder 12, a data input / output gate 14, a column decoder 16, a data input / output circuit 18, and The control unit 20 is configured.

1, wl1 to wlm represent word line select signals, y1 to yn represent column select signals, respectively, WL1 to WLm represent word lines, and (BL1, BL1B) to (BLn, BLnB) represent bit line pairs. Represent each.

The function of each of the blocks shown in FIG. 1 will be described below.

The memory cell array 10 includes a plurality of static memory cells MC11 to MCmn connected between each of the word lines WL1 to WLm and each of the bit line pairs BL1 and BL1B to BLn and BLnB. And write data to the selected memory cell at the time of writing, read data stored in the selected memory cell at the time of reading, and output data dout. The row decoder 12 decodes the row address RA in response to the active command ACT to generate word line select signals wl1 to wlm. The data input / output gate 14 transmits data Din as data din at the time of writing and data dout as data Dout at the time of writing in response to the column selection signals y1 to yn. . The column decoder 16 decodes the column address CA in response to the read and write commands RD and WR to generate column select signals y1 to yn. The data input / output circuit 18 inputs the data DIN in response to the write command WR to output the data Din, and inputs the data Dout in response to the read command RD to receive the data DOUT. Output The controller 20 inputs a command COM to generate active, read, and write commands ACT, RD, and WR.

FIG. 2 is a block diagram showing the configuration of the embodiment of the row decoder or column decoder shown in FIG. 1, and is composed of two pre decoders 30 and 32 and a main decoder 34. As shown in FIG. Each of the two pre decoders 30 and 32 and the main decoder 34 has a two input NAND gate NA and an inverter INV.

The decoder of the embodiment shown in Fig. 2 is a circuit arrangement for generating 16 decoded signals DRA1 to DRA16 by inputting 4-bit addresses A1 to A4.

The function of each of the blocks shown in FIG. 2 will be described below.

Each of the pre decoders 30 and 32 predecodes the address ((A1, A2), (A3, A4) by 2 bits to predecode the signals ((DRA1B2B to DRA12) and (DRA3B4B to DRA34)). Outputs The main decoder 34 decodes the pre-decoded signals DRA1B2B to DRA12 and DRA3B4B to DRA34 to generate the decoded signals DRA1 to DRA16.

As a result, the static memory cell of the memory cell array of the semiconductor memory device is composed of six transistors, and the column or row decoder is composed of a logic gate such as an inverter and a NAND gate. The inverter consists of two transistors, and the NAND gate consists of four or more transistors.

The column and row decoders of the embodiment of FIG. 2 described above are composed of four transistors because they are composed of two-input NAND gates, but six or eight transistors in the case of three-input NAND gates or four-input NAND gates. It is composed.

In the data input / output circuit 18 and the control unit 20, an NOR gate is additionally provided in addition to the inverter and the NAND gate.

As a result, the logic gate constituting the peripheral circuit of the semiconductor memory device may include an inverter, a NAND gate, and a NOR gate.

FIG. 3A is a circuit diagram of an example of a static memory cell of the memory cell array shown in FIG. 1, and FIGS. 3B, c, and D are circuit diagrams of an example of an inverter, a NAND gate, and a NOR gate, respectively, which constitute a peripheral circuit.

As shown in Fig. 3A, the static memory cell is composed of PMOS transistors PU1 and PU2 and NMOS transistors PD1, PD2, T1, and T2. PMOS transistors PU1 and PU2 are pull-up transistors, NMOS transistors PD1 and PD2 are pull-down transistors, and NMOS transistors T1 and T2 are transfer transistors.

The operation of the memory cell shown in FIG. 3A will be described below.

When the word line WL is selected and the NMOS transistors T1 and T2 are turned on, data is transferred between the bit line BL and the storage node a and between the inverted bit line BLB and the storage node b. The data is sent to. The NMOS transistor PD1 makes the storage node a a "low" level if the data of the storage node b is at the "high" level, and the PMOS transistor PU1 is the "low" level of data at the storage node b. Then put storage node (a) at the "high" level. Similarly, the NMOS transistor PD2 makes the storage node b a "low" level if the data of the storage node a is at the "high" level, and the PMOS transistor PU2 has the data of the storage node a be "low". Level, makes storage node b a high level. That is, the two PMOS transistors PU1 and PU2 and the two NMOS transistors PD1 and PD2 are latches and latch data of the storage nodes a and b.

As shown in Fig. 3B, the inverter is composed of a PMOS transistor P1 and an NMOS transistor N1.

In FIG. 3B, the PMOS transistor P1 is a pull-up transistor and the NMOS transistor N1 is a pull-down transistor.

The operation of the inverter shown in FIG. 3B is as follows.

When the input signal IN of the "high" level is applied, the NMOS transistor N1 is turned on to bring the output signal OUT to the "low" level, that is, the ground voltage VSS level. On the other hand, when the input signal IN of the "low" level is applied, the PMOS transistor P1 is turned on to make the output signal OUT to the "high" level, that is, the power supply voltage VCC level.

That is, the inverter shown in FIG. 3B is composed of one pull-up transistor and one pull-down transistor, and inverts the input signal IN to generate the output signal OUT.

As shown in Fig. 3C, the NAND gate is composed of PMOS transistors P2 and P3 and NMOS transistors N2 and N3.

In FIG. 3C, the PMOS transistors P2 and P3 are pull-up transistors, and the NMOS transistors N2 and N3 are pull-down transistors.

The operation of the NAND gate shown in FIG. 3C is as follows.

When at least one input signal IN1 or IN2 having a "low" level is applied, the PMOS transistor P2 or / and the PMOS transistor P3 are turned on to turn the output signal OUT to a "high" level, that is, a power supply voltage. To the (VCC) level. On the other hand, when the input signals IN1 and IN2 of the "high" level are applied, all of the NMOS transistors N2 and N3 are turned on to make the output signal OUT to the "low" level.

As shown in FIG. 3D, the NOR gate is composed of PMOS transistors P4 and P5 and NMOS transistors N4 and N5.

In FIG. 3D, the PMOS transistors P4 and P5 are pull-up transistors, and the NMOS transistors N4 and N5 are pull-down transistors.

The operation of the NOR gate shown in FIG. 3D is as follows.

When at least one input signal IN1 or IN2 of the “high” level is applied, the NMOS transistor N4 or / and the NMOS transistor N5 are turned on to turn the output signal OUT to a “low” level, that is, a ground voltage. To the (VSS) level. On the other hand, when the input signals IN1 and IN2 of the "low" level are applied, all of the PMOS transistors P4 and P5 are turned on to make the output signal OUT to the "high" level.

FIG. 4A conceptually illustrates an arrangement of transistors constituting the static memory cells of the memory cell array shown in FIG. 3A, and FIGS. 4B, c, and d show the inverters, NAND gates, and NORs shown in FIGS. The arrangement of one example of the transistors constituting each is conceptually shown.

4A to 4D, the bit line pairs BL and BLB, the word line WL, the power supply voltage line VCCL, and the ground voltage line VSSL each appear to be disposed on different layers, but are different from each other. It is not meant to be arranged in layers.

As shown in FIG. 4A, the transistors PD1, PD2, PU1, PU2, T1, and T2 shown in FIG. 3A are disposed on the same layer 1F. Then, the source of the NMOS transistor T1 and the drain of the NMOS transistor PD1 are connected, the source of the NMOS transistor PD1 and the source of the NMOS transistor PD2 are connected, the drain of the NMOS transistor PD2 and the NMOS transistor The source of (T2) is linked. The drain of the NMOS transistor T1 is connected to the bit line BL, the drain of the NMOS transistor T2 is connected to the inverting bit line BLB, and the gates of the NMOS transistors T1 and T2 are connected to the word line (B). WL), and the sources of the NMOS transistors PD1 and PD2 are connected to the ground voltage line VSSL. The drain of the PMOS transistor PU1 is connected to the source of the NMOS transistor PD1, the source is connected to the power supply voltage line VCCL, and the gate of the PMOS transistor PU1 is drained from the gate of the NMOS transistor PD1 and the drain of the NMOS transistor PD2. Is connected to. In addition, the drain of the PMOS transistor PU2 is connected to the drain of the NMOS transistor PD2, the source is connected to the power supply voltage line VCCL, and the gate is connected to the gate of the NMOS transistor PD2.

As shown in Fig. 4B, the transistors P1 and N1 shown in Fig. 3B are disposed on the same layer 1F. The source of the PMOS transistor P1 is connected to the power supply voltage line VCCL, the drain is connected to the output signal line OUTL, and the gate is connected to the input signal line INL. A source of the NMOS transistor N1 is connected to the ground voltage line VSSL, a drain is connected to the output signal line OUTL, and a gate is connected to the input signal line INL.

As shown in FIG. 4C, the transistors P3, P2, N2, and N3 shown in FIG. 3C are disposed in the same layer 1F. The source of the PMOS transistor P3 and the source of the PMOS transistor P2 are connected, and the drain of the PMOS transistor P3 is connected to the output signal line OUTL. The gates of the PMOS transistor P3 and the NMOS transistor N3 are connected to the input signal line IN1L, the gates of the PMOS transistor P2 and the NMOS transistor N2 are connected to the input signal line IN2L, and the PMOS transistors are connected to the input signal line IN2L. P2 and the drain of the NMOS transistor N2 are connected, the source of the NMOS transistors N2 and N3 are connected, and the drain of the NMOS transistor N3 is connected to the ground voltage line VSSL.

As shown in FIG. 4D, the transistors P4, P5, N4, and N5 shown in FIG. 3D are disposed in the same layer 1F. The drain of the PMOS transistor P4 and the source of the PMOS transistor P5 are connected, the drain of the PMOS transistor P5 and the drain of the NMOS transistor N5 are connected, and the source and gate of the PMOS transistor P4 are connected. The gate of the PMOS transistor P5 is connected to the input signal line IN1L, and the drains of the PMOS transistor P5 and the NMOS transistor N5 are respectively connected to the power supply voltage line VCCL and the input signal line IN2L. The drain, gate, and source of the NMOS transistor N4 are connected to the output signal line OUTL, the input signal line IN2L, and the ground voltage line VSSL.

That is, as shown in Figs. 4A to 4D, since the transistors constituting the memory cell and the peripheral circuit of the semiconductor memory device of the present invention are all disposed on the same layer 1F, the layout area increases when the capacity of the memory cell increases. Done.

In order to reduce the layout area of the memory cell of the semiconductor memory device, a method of stacking two or three layers of transistors constituting the memory cell has emerged.

5A to 5D conceptually show arrangements of other examples of transistors constituting an inverter, a NAND gate, and a NOR gate of a static memory cell and a peripheral circuit of a conventional semiconductor memory device, respectively. It is the stacking of layers.

As shown in FIG. 5A, the NMOS transistors PD1, PD2, T1, and T2 are disposed on the first layer 1F, and the PMOS transistors PU1, PU2 are disposed on the second layer 2F. The connections between the transistors PD1, PD2, PU1, PU2, T1, and T2 are the same as those of the transistors of FIG. 4A.

In the arrangement of FIGS. 5B to 5D, the transistors P1 to P5 and N1 to N5 constituting the inverter, the NAND gate, and the NOR gate are disposed on the first layer 1F in the same manner as the arrangement of FIGS. 4B to 4D.

Therefore, as shown in FIG. 5A, when the transistors constituting the static memory cell of the semiconductor memory device are stacked in two layers and the transistors constituting the peripheral circuit are arranged in one layer, the layout area of the memory cell array is reduced. As a result, the layout area of the peripheral circuit is not reduced, and as a result, the overall layout area is not reduced.

6A through 6D conceptually illustrate another example arrangement of transistors constituting an inverter, a NAND gate, and a NOR gate of a static memory cell and a peripheral circuit of a conventional semiconductor memory device, wherein three layers of transistors constituting a memory cell are illustrated. It indicates that they are stacked and arranged.

As shown in FIG. 6A, the NMOS transistors PD1 and PD2 are disposed on the first layer 1F, the PMOS transistors PU1 and PU2 are disposed on the second layer 2F, and the NMOS transistors T1 and T2. ) Is placed on the third floor (3F). The connections between the transistors PD1, PD2, PU1, PU2, T1, and T2 are the same as those of the transistors of FIG. 4A.

6B to 6D arrange the transistors P1 to P5 and N1 to N5 constituting the inverter, the NAND gate, and the NOR gate in the same manner as the arrangement of FIGS. 4B to 4D.

Therefore, as shown in FIG. 6A, when the transistors constituting the static memory cell of the semiconductor memory device are stacked in three layers and the transistors constituting the peripheral circuit are arranged in one layer, the layout area of the memory cell array may be reduced. As a result, the layout area of the peripheral circuit is not reduced, and as a result, the overall layout area is not reduced.

That is, by stacking two or three layers of static memory cells of a memory cell array of a conventional semiconductor memory device, the layout area of the memory cell array is reduced, but the transistors constituting the peripheral circuit are arranged in one layer. The layout area is not reduced.

7A to 7D conceptually illustrate an arrangement of a first embodiment of transistors constituting an inverter, a NAND gate, and a NOR gate of a static memory cell and a peripheral circuit of the semiconductor memory device of the present invention. The arrangement of the transistors constituting the peripheral circuit when stacked in two layers is shown.

In the arrangement of FIG. 7A, the transistors PU1, PU2, PD1, PD2, T1, and T2 constituting the static memory cell are stacked and arranged in two layers, similarly to the arrangement of FIG. 5A.

As shown in Fig. 7B, the NMOS transistor N1 is disposed in the first layer 1F, and the PMOS transistor P1 is disposed in the second layer 2F. The connections between the transistors N1 and P1 constituting the inverter are connected in the same manner as shown in FIG. 4B.

As shown in Fig. 7C, the NMOS transistors N2 and N3 are arranged in the first layer 1F, and the PMOS transistors P2 and P3 are arranged in the second layer 2F. The connections between the transistors N2, N3, P2, and P3 constituting the NAND gate are connected as shown in FIG. 4C.

As shown in Fig. 7D, the NMOS transistors N4 and N5 are disposed in the first layer 1F, and the PMOS transistors P4 and P5 are disposed in the second layer 2F. Then, the connections between the transistors N4, N5, P4, and P5 constituting the NOR gate are connected as shown in FIG. 4D.

As shown in Figs. 7A to 7D, the semiconductor memory device of the present invention is stacked with two layers of transistors constituting a memory cell, and the transistors constituting a peripheral circuit are also stacked with two layers, so that the overall layout of the semiconductor memory device is arranged. Area can be reduced.

The transistors shown in FIGS. 7B to 7D may be interchanged with each other, and are not necessarily disposed on the first layer 1F and the second layer 2F, and the first layer 1F, the third layer 3F, or the second layer ( It may be arranged on 2F) and 3F (3F).

However, although the PMOS transistor and the NMOS transistor may be disposed in the first layer 1F, the transistors of the same type as the transistors disposed in the second layer 2F of the memory cell may be disposed in the second layer 2F for process convenience. It is preferable to arrange. That is, if the transistors arranged in the second layer 2F of the memory cell are NMOS transistors, the transistors arranged in the second layer 2F of the peripheral circuit are also preferably arranged as NMOS transistors, and are arranged in the second layer 2F of the memory cell. If the transistors to be formed are PMOS transistors, it is preferable to arrange them as transistors or PMOS transistors arranged in the second layer 2F of the peripheral circuit.

8A to 8D conceptually illustrate an arrangement of a second embodiment of transistors constituting an inverter, a NAND gate, and a NOR gate of a static memory cell and a peripheral circuit of the semiconductor memory device of the present invention. The arrangement of the transistors constituting the peripheral circuit in the case of three layers is shown.

In the arrangement of FIG. 8A, the pull-down transistors PD1 and PD2 constituting the static memory cell are arranged in the first layer 1F and the pull-up transistors PU1 and PU2 are arranged in the same manner as the arrangement of FIG. 6A. The transfer transistors T1 and T2 are disposed in the third layer 3F.

As shown in Fig. 8B, the NMOS transistors N1-1 and N1-2 having the channel width 1/2 of the channel width of the NMOS transistor N1 shown in Fig. 3B are constituted, and the NMOS transistor N1-2. ) Is disposed on the first layer 1F, the PMOS transistor P1 is disposed on the second layer 2F, and the NMOS transistor N1-1 is disposed on the third layer 3F. The gate, drain, and source of the NMOS transistors N1-1 and N1-2 are connected in common, and the connection between the NMOS transistors N1-1 and N1-2 and the PMOS transistor P1 is illustrated in FIG. Connect as shown in 4b.

As shown in Fig. 8C, the PMOS transistor P2 and the NMOS transistor N2 are disposed on the first layer 1F, the PMOS transistor P3 is disposed on the second layer 2F, and the NMOS transistor N3 is three. It is placed in the layer 3F. The PMOS transistors P2 and P3 and the NMOS transistors N2 and N3 are connected as shown in FIG. 4C.

As shown in FIG. 8D, the NMOS transistors N4-1, N4-2, N5-1, N5- having a channel width 1/2 of the channel width of each of the NMOS transistors N4, N5 shown in FIG. 3D. 2), the NMOS transistors N4-1 and N5-1 are disposed on the first layer 1F, the PMOS transistors P4 and P5 are disposed on the second layer 2F, and the NMOS transistors N5-1 and N5-2 are arrange | positioned at 3F (3F). The gates, sources and drains of the NMOS transistors N4-1 and N4-1 are connected in common, and the gates, sources and drains of the NMOS transistors N5-1 and N5-2 are connected in common. The connection between the PMOS transistors P4 and P5 and the NMOS transistors N4 and N5 is connected as shown in FIG. 4D.

As shown in Figs. 8A to 8D, the semiconductor memory device of the present invention is stacked with three layers of transistors constituting a memory cell, and the transistors constituting peripheral circuits are also stacked with three layers, so that the overall layout of the semiconductor memory device is arranged. Area can be reduced.

9A to 9D conceptually illustrate an arrangement of a third embodiment of transistors constituting an inverter, a NAND gate, and a NOR gate of a static memory cell and a peripheral circuit of the semiconductor memory device of the present invention. The arrangement of the transistors constituting the peripheral circuit in the case of three layers is shown.

In the arrangement of FIG. 9A, transistors constituting the static memory cell are stacked in three layers in the same manner as the arrangement of FIG. 8A.

As shown in Fig. 9B, the PMOS transistors P1-1 and P1-2 having the channel width 1/2 of the channel width of each of the PMOS transistors P1 constituting the inverter are constructed, and the PMOS transistor P1 is formed. -1) is placed on one layer 1F, PMOS transistors P1-2 are placed on two layers 2F, and NMOS transistors N1 are placed on three layers 3F. In addition, the gate, the drain, and the source of the PMOS transistors P1-1 and P1-2 are connected in common, and the connection between the PMOS transistors P1-1 and P1-2 and the NMOS transistor N1 is illustrated in FIG. Connect as shown in 4b.

As shown in FIG. 9C, PMOS transistors P2-1, P2-2, P3-1, and P3 each having a channel width 1/2 of the channel width of each of the PMOS transistors P2 and P3 constituting the NAND gate. -2), the PMOS transistors P2-2 and P3-2 are disposed on the first layer 1F, and the PMOS transistors P2-1 and P3-1 are disposed on the second layer 2F. NMOS transistors N2 and N3 are arranged in the third layer 3F. The gate, drain, and source of the PMOS transistors P2-1 and P2-2 are connected in common, and the gate, drain, and source of the PMOS transistors P3-1 and P3-2 are connected in common. The PMOS transistors P2-1, P2-2, P3-1, and P3-2 are connected to the NMOS transistors N2 and N3 as shown in FIG. 4C.

As shown in FIG. 9D, PMOS transistors P4-1, P4-2, P5-1, and P5 each having a channel width 1/2 of the channel width of each of the PMOS transistors P4 and P5 constituting the NOR gate. -2), the PMOS transistors P4-1 and P5-1 are disposed on the first layer 1F, and the PMOS transistors P4-2 and P5-2 are disposed on the second layer 2F. NMOS transistors N4 and N5 are disposed on the third layer 3F. The gate, drain, and source of the PMOS transistors P4-1 and P4-2 are connected in common, and the gate, drain, and source of the PMOS transistors P5-1 and P5-2 are connected in common. The PMOS transistors P4-1, P4-2, P5-1, and P5-2 are connected to the NMOS transistors N4 and N5 as shown in FIG. 4D.

Although not shown, NMOS transistors N2-1, N2-2, N3-1, and N3- having a channel width 1/2 of the channel width of each of the NMOS transistors N2 and N3 constituting the NAND gate. 2), two PMOS transistors P2 and P3 and two NMOS transistors N2-1, N2-2, N3-1, and N3-2 may be arranged in three different layers.

In addition, the transistors constituting the inverter, the NAND gate, and the NOR gate of the above-described embodiments only need to be disposed on different layers, and do not necessarily need to be disposed on the same layer as shown.

However, although a PMOS transistor and an NMOS transistor may be disposed in the first layer 1F, a transistor having the same type as a transistor disposed in the second layer 2F of the memory cell is disposed in the second layer 2F for process convenience. It is preferable. That is, if the transistors arranged on the second layer 2F of the memory cell are PMOS transistors, the transistors arranged on the second layer 2F of the peripheral circuit are also preferably arranged as PMOS transistors, and are arranged on the third layer 3F of the memory cell. If the transistors to be used are NMOS transistors, it is preferable to arrange them as transistors or NMOS transistors arranged in three layers 3F of the peripheral circuit.

Now, the arrangement and structure of an embodiment of an inverter, a NAND gate, and a NOR gate constituting a static memory cell and a peripheral circuit of the semiconductor memory device described above will be described.

10A to 16A and 10D to 16D are plan views illustrating arrangements of memory cells, inverters, NAND gates, and NOR gates according to embodiments of the present invention, and FIGS. 17A and 16B are FIGS. 10A to 16A. Is a cross-sectional view showing the structure of a memory cell of an embodiment of the present invention according to I-I ', II-II', and FIGS. 18 to 20 are X in FIGS. 10B to 16B, 10C to 16C, and 10D to 16D. -Sectional drawing which shows the structure of the memory cell of the Example of this invention by X '.

10A, 17A, and B, a first active region 1b ′ and a second active region 1a ′ are disposed on the semiconductor substrate SUB so as to be parallel to the y-axis and face each other. One end of 1a ') extends parallel to the x-axis. In addition, the third active region 1b ″ and the fourth active region 1a ″ are disposed on the semiconductor substrate SUB so as to be parallel to the y axis, and one end of the fourth active region 1a ″ is disposed on the x axis. Extend parallel. do. The gate pattern 1c 'is disposed in the x-axis direction to intersect the upper portions of the first active region 1b' and the second active region 1a 'disposed in parallel in the y-axis direction, and the gate pattern 1c ″. ) Is disposed in the x-axis direction so as to cross the upper portions of the third active region 1b ″ and the fourth active region 1a ″ arranged in parallel in the y-axis direction. The drain region PD1D is provided on the surface of the first active region 1b 'located on one side of the gate pattern 1c', and the source region PD1S is formed on the surface of the second active region 1a 'located on the other side. Is provided. Similarly, the drain region PD1D is provided on the surface of the third active region 1b ″ positioned on one side of the gate pattern 1c ″, and the source region PD2S is provided on the surface of the fourth active region 1a ″ positioned on the other side thereof. ) Is provided. Each of the gate patterns 1c 'and 1c ″ has a gate electrode PD1G, a capping insulating film 2a', and a gate electrode PD2G and a capping insulating film 2a ”of the NMOS transistor PD1 stacked in turn. ) And gate insulating films 2b 'and 2b' are interposed between each of the gate patterns 1c 'and 1c' and the semiconductor substrate SUB. In addition, a spacer 2c may be provided on sidewalls of the gate patterns 1c 'and 1c ″, and the interlayer insulating layer 2e is formed on the entire surface of the semiconductor substrate SUB having the NMOS transistors PD1 and PD2. ) Are stacked. An etch stop layer 2d may be further interposed between the semiconductor substrate SUB having the NMOS transistors PD1 and PD2 and the interlayer insulating layer 2e. In this manner, NMOS transistors PD1 and PD2 which are bulk transistors are formed on the semiconductor substrate SUB.

10B and 18, the first and second active regions 20a 'and 20b' are disposed to face each other on the semiconductor substrate SUB, and the gate pattern 20c 'is disposed in the first and second active regions. It is disposed in the y direction on top of the fields 20a 'and 20b', and one end thereof extends in parallel in the x direction on the side where the first active region 20a 'is located. The drain region N1D of the NMOS transistor N1 is provided on the surface of the first active region 20a ', and the source region N1S of the NMOS transistor N1 is provided on the surface of the second active region 20b'. do. The gate pattern 20c 'of the NMOS transistor N1 may include the gate electrode N1G and the capping insulating layer 21a of the NMOS transistor N1 stacked in turn, and the gate pattern 20c' and the semiconductor substrate. The gate insulating film 21b is interposed between the SUBs. The spacer 21c may be provided on the sidewalls of the gate pattern 20c ′, and the interlayer insulating layer 21e is stacked on the entire surface of the semiconductor substrate SUB having the NMOS transistor N1. An etch stop layer 21d may be additionally interposed between the semiconductor substrate SUB having the NMOS transistor N1 and the interlayer insulating layer 21e. Therefore, the NMOS transistor N1 which is a bulk transistor constituting the inverter is formed on the semiconductor substrate SUB.

10C and 19, first, second, and third active regions 40a ', 40b', and 40a 'are provided in the semiconductor substrate SUB. The gate pattern 40c 'is disposed in the y direction on the first and second active regions 40a' and 40b ', and one end thereof is disposed in the x direction on the side where the first active region 40a' is located. The gate pattern 40c ″ is disposed in the y-direction above the second and third active regions 40b 'and 40a ″, and one end of the gate pattern 40c ″ is disposed in the y-direction. It is arranged to be parallel to the x direction. In addition, one end of the gate pattern 40c 'and one end of the gate pattern 40c' are arranged in a diagonal direction. The gate pattern 40c 'of the NMOS transistor N2 may include a gate electrode N2G and a capping insulating layer 41a' of the NMOS transistor N2 that are sequentially stacked, and the gate pattern 40c 'and the semiconductor substrate ( A gate insulating film 41b 'is interposed between the SUBs. The drain region N2D of the NMOS transistor N2 is provided on the surface of the first active region 40a 'of the semiconductor substrate SUB, and the NMOS transistors N2 are provided on the surface of the second active region 40b'. , Source and drain regions N2S and N3D of N3 are provided, and a source region N3S of the NMOS transistor N3 is provided on the surface of the third active region 40a ″. A spacer 41c may be provided on sidewalls of the gate pattern 40c ', and an interlayer insulating layer 41e is stacked on the entire surface of the semiconductor substrate SUB having the NMOS transistor N2. An etch stop layer 41d may be further interposed between the semiconductor substrate SUB having the NMOS transistor N2 and the interlayer insulating layer 41e. Similarly, the gate pattern 40c ″ of the NMOS transistor N3 is also provided in the same form as the gate pattern 40c ′ of the NMOS transistor N2. Therefore, NMOS transistors N2 and N3, which are bulk transistors constituting a NAND gate, are formed on the semiconductor substrate SUB.

10D and 20, an N well N WELL is formed in a semiconductor substrate SUB, and first, second, and third active regions 60a ', 60b' are formed in the N well N WELL. 60a ”) is provided. Each of the gate patterns 60c 'and 60c' is provided in the same form as the gate patterns 40c 'and 40c' of FIG. 10C. As shown in FIG. 20, PMOS transistors P4 and P5 which are bulk transistors are formed on the semiconductor substrate SUB. The PMOS transistors P4 and P5 have the same form as the NMOS transistors N2 and N3 shown in FIG.

11A, 17A, and B, the drain region PD1D of the NMOS transistor PD1 is electrically connected to the lower node semiconductor plug 3a 'passing through the interlayer insulating film 2e and the etch stop film 2d. The drain region PD2D of the NMOS transistor PD2 is electrically connected to the lower node semiconductor plug 3a ″ penetrating through the interlayer insulating film 2e and the etch stop film 2d. Lower body patterns 3b 'and 3b' are disposed on the interlayer insulating film 2e and are disposed to cover each of the lower node semiconductor plugs 3a 'and 3a'.

11B and 18, the drain region N1D of the NMOS transistor N1 is electrically connected to the node semiconductor plug 22b penetrating through the interlayer insulating film 21e and the etch stop film 21d, and having a lower body. The pattern 22a is disposed on the interlayer insulating film 21e and is disposed to cover the node semiconductor plug 22b.

11C and 19, the drain region N2D of the NMOS transistor N2 is electrically connected to the node semiconductor plug 42b penetrating through the interlayer insulating film 41e and the etch stop film 41d, and having a lower body. The pattern 42a is disposed on the interlayer insulating film 41e and is disposed to cover the node semiconductor plug 42b.

When memory cells, inverters, and NAND gates are arranged as shown in Figs. 11A and 11C, the arrangement of the NOR gate shown in Fig. 11D has the same arrangement as that in Fig. 10D.

12A, 17A, and B, the gate pattern 4b 'of the PMOS transistor PU1 is disposed to cross the upper portion of the lower body pattern 3b', and the upper portion of the lower body pattern 3b 'is disposed. The gate pattern 4b ″ of the PMOS transistors PU2 is disposed to intersect. The upper node semiconductor plug 4a 'is disposed at a position where the lower node semiconductor plug 3a' is disposed on the lower body pattern 3b ', and the lower node semiconductor is positioned on the lower body pattern 3b'. The upper node semiconductor plug 4a "is disposed at the position where the plug 3a" is disposed. Gate electrodes PU1G and PU2G of each of the PMOS transistors PU1 and PU2 are provided on each of the lower body patterns 3b 'and 3b ″. The source region PU1S and the drain region PU1D of the PMOS transistor PU1 are provided in the lower body pattern 3b ', and the source region PU2S and the drain of the PMOS transistor PU2 in the lower body pattern 3b ″. The area PU2D is provided. Therefore, PMOS transistors PU1 and PU2 which are thin film transistors are stacked on the NMOS transistors PD1 and PD2.

12B and 18, the gate pattern 23a is disposed on the lower body pattern 22a in the same form as the gate pattern 20c ′. The gate electrode P1G of the PMOS transistor P1 is disposed on the lower body pattern 22a, and the drain region P1D and the source region P1S of the PMOS transistor P1 are provided in the lower body pattern 22a. do. A capping insulating film 24a is interposed between the gate electrode P1G and a gate insulating film 24b is interposed therebetween. The spacer 24c may be provided on the sidewall of the gate pattern 23a, and the interlayer insulating layer 24e is stacked on the entire surface of the lower body pattern 22a having the PMOS transistor P1. An etch stop layer 21d may be further interposed between the lower body pattern 22a having the PMOS transistor P1 and the interlayer insulating layer 21e. Therefore, a PMOS transistor P1, which is a thin film transistor, is stacked on the NMOS transistor N1.

12C and 19, the gate patterns 43a ′ and 43a ″ are disposed to overlap the gate patterns 40c ′ and 40c ″ on the lower body pattern 42a. Gate electrodes P2G and P3G of the PMOS transistors P2 and P3 are disposed on the lower body pattern 42a, and drain regions P2D and PMOS of the PMOS transistor P2 are disposed in the lower body pattern 42a. A source region P2S and a drain region P3S of the transistors P2 and P3 and a drain region P3D of the PMOS transistor P3 are provided. A capping insulating film 44a 'is interposed in the upper portion of the gate electrode P2G, a gate insulating film 44b' is interposed in the lower portion of the gate electrode P2G, and a capping insulating film 44a 'is interposed in the upper portion of the gate electrode P3G. A gate insulating film 44b ″ is interposed therebetween, and spacers 44c ′ and 44c ″ are provided on sidewalls of the gate patterns 43a ′ and 43a ″. An interlayer insulating film 44e is stacked on the entire surface of the lower body pattern 42a having the PMOS transistors P2 and P3. An etch stop layer 44d may be further interposed between the lower body pattern 42a having the PMOS transistors P2 and P3 and the interlayer insulating layer 44e. Therefore, PMOS transistors P2 and P3 which are thin film transistors are stacked on the NMOS transistors N2 and N3.

When the memory cell, the inverter, and the NAND gate are arranged as shown in Figs. 11A and 11C, the arrangement of the NOR gate shown in Fig. 12D has the same arrangement as that in Fig. 11D.

13A, 17A, and B, upper body patterns 6a 'and 6a' are disposed on the interlayer insulating film 5e. The upper body patterns 6a 'and 6a' are disposed to cover the upper node semiconductor plugs 4a 'and 4a', respectively, and overlap the lower body patterns 3b 'and 3b'. A word line pattern 6b is provided to cross over the upper body patterns 6a 'and 6a', and the word line pattern 6b is disposed so as to overlap the gate patterns 1c 'and 1c'. The word lines T1G and T2G are provided on the upper body patterns 6a 'and 6a', respectively, and the drain region T1D and the source region of the transfer transistor T1 are provided inside the upper body pattern 6a '. T1S is provided, and a drain region T2D and a source region T2S of the transfer transistor T2 are provided inside the upper body pattern 6a ″. A capping insulating film 7a is interposed between the word lines T1G and T2G, a gate insulating film 7b is interposed below, and a spacer 7c is provided on the sidewall of the word line pattern 6b. An interlayer insulating film 7e is deposited on the entire surface of the upper body patterns 6a 'and 6a "having the transfer transistors T1 and T2. An etch stop layer 7d may be further interposed between the upper body patterns 6a ′ and 6a ″ having the transfer transistors T1 and T2 and the interlayer insulating layer 7e. Therefore, transfer transistors T1 and T2 that are thin film transistors are stacked on top of the pull-up transistors PU1 and PU2.

In the case where the memory cells are arranged as shown in Fig. 13A, the arrangement of the inverter and the NAND gate shown in Figs. 13B and 13C has the same arrangement as that of Figs. 12B and 12C.

13D and 20, the drain region P5D of the PMOS transistor P5 is electrically connected to the node semiconductor plug 65b passing through the interlayer insulating films 64e and 61e and the etch stop layer 41d. The upper body pattern 65a is disposed to cover the interlayer insulating layer 64e and the node semiconductor plug 65b.

14A, 17A, and B, the lower node semiconductor plug 3a ', the upper node semiconductor plug 4a', the drain region PD1S of the pull-down transistor PD1, and the drain region of the pull-up transistor PU1. (PU1S), source region T1S of transfer transistor T1, gate electrode PD2G of pull-down transistor PD2, and gate electrode PU2G of pull-up transistor PU2 are connected via node plug 8a '. Electrically connected. The lower node semiconductor plug 3a ″, the upper node semiconductor plug 4a ″, the drain region PD2D of the pull-down transistor PD2, the drain region PU2D of the pull-up transistor PU2, and the transfer transistor T2. The source region T2S, the gate electrode PD1G of the pull-down transistor PD1, and the gate electrode PU1G of the pull-up transistor PU1 are electrically connected through the node plug 8a ″.

In the case where the memory cells are arranged as shown in Fig. 14A, the arrangement of the inverter and the NAND gate shown in Figs. 14B and 14C has the same arrangement as that of Figs. 13B and 13C.

14D and 20, the gate patterns 66a ′ and 66a ″ are disposed to overlap the gate patterns 60c ′ and 60c ″ on the upper body pattern 65a. As shown in FIG. 20, gate electrodes N4G and N5G of the NMOS transistors N4 and N5 are disposed on the upper body pattern 65a, and a drain region of the NMOS transistor N5 is disposed in the upper body pattern 65a. (N5D), source region (N5S) and drain region (N4D) of NMOS transistors (N4, N5), and source region (N4S) of NMOS transistor (N4). A capping insulating film 67a 'is interposed on the upper portion of the gate electrode N5G, a gate insulating film 67b' is interposed on the lower portion of the gate electrode N5G, and a capping insulating film 67a 'is interposed on the upper portion of the gate electrode N4G. A gate insulating layer 67b ″ is interposed therebetween, and spacers 67c ′ and 67c ″ are provided on sidewalls of the gate patterns 66a ′ and 66a ″. Then, an interlayer insulating film 67e is stacked on the entire surface of the upper body pattern 65a having the NMOS transistors N4 and N5. An etch stop layer 67d may be further interposed between the upper body pattern 65a having the NMOS transistors N4 and N5 and the interlayer insulating layer 67e. Therefore, NMOS transistors N4 and N5 which are thin film transistors are stacked on the PMOS transistors P4 and P5.

15A, 17A, and B, an interlayer insulating film 9c is laminated on the node plugs 8a ', 8a' and the interlayer insulating film 7e. The source region PU1S of the pullup transistor PU1 is electrically connected to the power supply line contact plug 9a ', and the source region PU2S of the pullup transistor PU2 is electrically connected to the power supply line contact plug 9a ". do. The source region PD1S of the pull-down transistor PD1 is electrically connected to the ground line contact plug 9b ', and electrically connected to the ground line contact plug 9b "of the source region PD2S of the pull-down transistor PD2. Is connected.

15B and 18, an interlayer insulating film 26 is laminated on the interlayer insulating film 24e. The node semiconductor plug 22b, the drain region N1D of the NMOS transistor N1 and the drain region P1D of the PMOS transistor P1 are electrically connected to the output signal line contact plug 25a, and the PMOS transistor P1 is connected. The source region P1S of is electrically connected to the power supply line contact plug 25b, and the source region N1S of the NMOS transistor N1 is electrically connected to the ground line contact plug 25c. Although not shown, the gate electrodes P1G and N1G of the PMOS transistor P1 and the NMOS transistor N1 are electrically connected to the input signal line contact plug 25d.

15C and 19, an interlayer insulating film 46 is laminated on the interlayer insulating film 44e. The node contact plug 42b, the drain region N2D of the NMOS transistor N2 and the drain region P2D of the PMOS transistor P2 are electrically connected to the output signal line contact plug 45a, and the PMOS transistors P2. Source regions P2S and P3S of P3 are electrically connected to the power supply line contact plug 45b, and the drain region P3D of the PMOS transistor P3 is electrically connected to the output signal line contact plug 45c. The source region N3S of the NMOS transistor N3 is electrically connected to the ground line contact plug 45d. Gate electrodes N2G and P2G of the NMOS transistor N2 and the PMOS transistor P2 are electrically connected to the first input signal line contact plug 45e, and the gates of the NMOS transistor N3 and the PMOS transistor P3 are connected to each other. The electrodes P2G and P3G are electrically connected to the second input signal line contact plug 45f.

15D and 20, an interlayer insulating film 69 is disposed on the interlayer insulating film 67e. The node contact plug 65b, the drain region P5D of the PMOS transistor P5 and the drain region N5S of the NMOS transistor N5 are electrically connected to the output signal line contact plug 68a, and the NMOS transistor N5. The source region N5S and the drain region N4D of the NMOS transistor N4 are electrically connected to the ground line contact plug 68b, and the source region N4S of the NMOS transistor N4 is an output signal line contact. It is electrically connected to the plug 68c, and the source region P4S of the PMOS transistor P4 is electrically connected to the power supply line contact plug 68d. Gate electrodes P5G and N5G of the PMOS transistor P5 and the NMOS transistor N5 are electrically connected to the first input signal line contact plug 68c, and the gates of the PMOS transistor P4 and the NMOS transistor N4. The electrodes P4G and N4G are electrically connected to the second input signal line contact plug 68d.

16A, 17A, and B, an interlayer insulating film 11 is disposed on the interlayer insulating film 9c. The power supply voltage line 10b is covered on the power supply line contact plug 9a ', and the ground voltage line 10a is covered on the ground line contact plug 9b'. Then, the power supply voltage line 10b is covered on the power supply line contact plug 9a ″, and the ground voltage line 10b is covered on the ground line contact plug 9b ″. An interlayer insulating film 12 is disposed on the interlayer insulating film 11, and each of the drain regions T1D and T2D of the transfer transistors T1 and T2 is electrically connected to the bit line contact plugs 13a 'and 13a'. Connected. The bit line 14 is covered on the bit line contact plugs 13a 'and 13a'.

16B and 18, the interlayer insulating film 28 is disposed on the interlayer insulating film 26, the output signal line 27a is covered on the output signal line contact plug 25a, and the ground line contact plug 25b. ) Is covered with ground voltage line 27b, and power supply line contact plug 25c is covered with power supply voltage line 27c. Then, the input signal line 27d is covered on the input signal line contact plug 25d.

16C and 19, the interlayer insulating film 48 is disposed on the interlayer insulating film 46, the output signal line 47a is covered on the output signal line contact plug 45a, and the power line contact plug ( The power supply voltage line 47b is covered over 45b, the output signal line 47c is covered over the output signal line contact plug 45c, and the ground voltage line 47d is covered over the ground line contact plug 45d. The first input signal line 47e is covered on the first input signal line contact plug 45e, and the second input signal line 47f is covered on the second input signal line contact plug 45f.

16D and 20, an interlayer insulating film 71 is disposed on the interlayer insulating film 69, the output signal line 70a is covered on the output signal line contact plug 68a, and the ground line contact plug 68b. ), The ground voltage line 70b is covered, the output signal line 70a is covered on the output signal line contact plug 68c, and the power supply voltage line 70d is covered on the power supply line contact plug 68d. The first input signal line 70e is covered on the first input signal line contact plug 68e, and the second input signal line 70f is covered on the second input signal line contact plug 68e.

The node contact plugs and the upper and lower body patterns of the above-described embodiment may be single crystal silicon substrates. And, the upper and lower body patterns may be polycrystalline silicon substrates, in which case no node contact plugs are needed.

Like the memory cell of the above-described embodiment, in the case where the bulk transistor is disposed on one layer of the memory cell and the thin film transistor is disposed on the two and three layers, the bulk transistor is disposed on the two and three layers of the peripheral circuit for the convenience of the process. The thin film transistor preferably has the same shape as that of the thin film transistor disposed on the second and third layers of the memory cell.

21A and 21B show the stacked structure of the first embodiment of the memory cell array and the peripheral circuit of the present invention. As shown in Fig. 21A, bulk NMOS transistors are respectively provided on the first, second and third layers of the memory cell array. In the case where the thin film PMOS transistor and the thin film NMOS transistor are stacked, it is preferable for the convenience of the process to be laminated on the first, second and third layers of the peripheral circuit as shown in Fig. 21B. That is, a bulk NMOS transistor or / and a bulk PMOS transistor may be disposed on one layer, and thin film PMOS transistors and thin film NMOS transistors having the same shape as transistors disposed on layers 2 and 3 of a memory cell array in layers 2 and 3, respectively. It is preferable that each be laminated.

22A and 22B show a stacked structure of the second embodiment of the memory cell array and the peripheral circuit of the present invention. As shown in FIG. 22A, bulk NMOS transistors are provided on one, two, and three layers of the memory cell array, respectively. In the case where the thin film NMOS transistors and the thin film PMOS transistors are stacked, it is preferable for the convenience of the process to be laminated on the first, second and third layers of the peripheral circuit as shown in Fig. 22B. That is, a bulk NMOS transistor or / and a bulk PMOS transistor can be disposed on one layer, and thin film NMOS transistors and thin film PMOS transistors of the same type as transistors disposed on two and three layers of a memory cell array on two and three layers. It is preferable that each be laminated.

23A and 23B show the stacked structure of the third embodiment of the memory cell array and the peripheral circuit of the present invention. As shown in FIG. 23A, bulk PMOS transistors are provided on one, two, and three layers of the memory cell array, respectively. In the case where the thin film NMOS transistors and the thin film NMOS transistors are stacked, it is preferable for the convenience of the process to be laminated on the first, second and third layers of the peripheral circuit as shown in Fig. 23B. That is, a bulk NMOS transistor or / and a bulk PMOS transistor may be disposed on one layer, and thin film NMOS transistors and thin film NMOS transistors of the same type as transistors disposed on layers 2 and 3 of a memory cell array in layers 2 and 3, respectively. It is preferable that each be laminated.

Of course, the thin film transistors arranged on the second and third layers of the peripheral circuit can be arranged differently from the thin film transistors arranged on the second and third layers of the memory cell array, but the process becomes complicated.

Since the semiconductor memory device of the present invention can reduce not only the layout area of the memory cell but also the layout area of the peripheral circuit, it is possible to reduce the overall layout area of the semiconductor memory device.

Although the above-described embodiment has described stacking transistors constituting an inverter, a NAND gate, and a NOR gate, it is of course possible to stack transistors constituting other logic circuits as well as logic gates such as an AND gate and an OR gate. .

In addition, the peripheral circuit of the present invention does not stack transistors constituting all the functional blocks of the peripheral circuit, and stacks only the transistors constituting some functional blocks, for example, row and / or column decoders, Only transistors constituting a driver (generally composed of an inverter) of the output terminal of the column decoder may be stacked and arranged.

The method of arranging the inverter, the NAND gate, and the NOR gate constituting the peripheral circuit of the above-described embodiment can be usefully used for other semiconductor devices.

In the above-described embodiment, the static semiconductor memory device has been described as an example, but the layout area can be reduced by using the peripheral circuit of the present invention not only for the static semiconductor memory device but also for the dynamic semiconductor memory device.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

The semiconductor memory device and the method of arranging the device of the present invention can stack and arrange not only a memory cell array but also transistors constituting a peripheral circuit, thereby reducing the overall layout area of the device.

Claims (64)

A plurality of inverters each having at least one first pull-up transistor and a first pull-down transistor and inverting and outputting an input signal; And A plurality of second pull-up transistors and second pull-down transistors, each of which generates an output signal of a “high” level when at least one of the at least two input signals is at a “low” level; Having NAND gates, And the at least one first pull-up and first pull-down transistors and the at least two or more second pull-up and second pull-down transistors stacked on at least two layers. The method of claim 1, wherein the first and second pull-up transistors are PMOS transistors, And the first and second pull-down transistors are NMOS transistors. The semiconductor device according to claim 2, wherein the transistors arranged in one layer of at least two layers are bulk transistors, and the transistors arranged in two or more layers are thin film transistors. 4. The semiconductor device according to claim 3, wherein the first layer is capable of mixing and arranging some of the first and second pull-up transistors and some of the first and second pull-down transistors. The semiconductor device of claim 4, wherein only the first and second pull-up transistors are disposed on the second or more layer, or only the first and second pull-down transistors are disposed. A plurality of inverters each having at least one first pull-up transistor and a first pull-down transistor and inverting and outputting an input signal; A plurality of second pull-up transistors and second pull-down transistors, each of which generates an output signal of a “high” level when at least one of the at least two input signals is at a “low” level; NAND gates; And A plurality of NOR gates each having at least two third pull-up transistors and third pull-down transistors, each generating at least a "high" level output signal if at least two input signals are all at "low" levels; Stacking the at least one first pull-up and pull-down transistors, the at least two or more second pull-up and second pull-down transistors, and the at least two or more third pull-up and third pull-down transistors on the at least two layers It arrange | positioned, The semiconductor device characterized by the above-mentioned. The method of claim 6, wherein the first, second, and third pull-up transistors are PMOS transistors, And the first, second, and third pull-down transistors are NMOS transistors. The semiconductor device according to claim 7, wherein the transistors arranged in one layer of at least two layers are bulk transistors, and the transistors arranged in two or more layers are thin film transistors. The method of claim 8, wherein the first layer is capable of mixing and arranging some of the first, second, and third pull-up transistors and some of the first, second, and third pull-down transistors. A semiconductor device characterized by the above-mentioned. The semiconductor of claim 9, wherein only the first, second, and third pull-up transistors are disposed on the second or more layer, or only the first, second, and third pull-down transistors are disposed. Device. A memory cell array having a plurality of memory cells accessed in response to a plurality of word line selection signals and a plurality of column selection signals; A row decoder to decode a row address to generate the plurality of word line select signals; And A column decoder which decodes a column address to generate the plurality of column selection signals, The row (column) decoder has a plurality of inverters, Each of the plurality of inverters includes at least one pull-up transistor and pull-down transistor, And the pull-up and pull-down transistors are stacked on at least two layers. The method of claim 11, wherein the plurality of memory cells include a plurality of MOS transistors. And the plurality of MOS transistors are stacked on the at least two layers. The method of claim 12, wherein the pull-up transistor is a PMOS transistor, And the pull-down transistors are NMOS transistors. The semiconductor memory device according to claim 13, wherein the transistors arranged in one layer of at least two layers are bulk transistors, and the transistors arranged in two or more layers are thin film transistors. 15. The semiconductor memory device according to claim 14, wherein the first layer is capable of mixing and arranging some of the pull-up and pull-down transistors. 16. The semiconductor memory device according to claim 15, wherein only the pull-up transistors or only the pull-down transistors are disposed in each of the two or more layers. 17. The semiconductor memory device according to claim 16, wherein the channel width of each of the pull-up transistors is divided into two or more pull-up transistors, and the two or more pull-up transistors are arranged in different layers. 18. The semiconductor memory device according to claim 17, wherein the channel width of each of the pull-down transistors is divided into two or more pull-down transistors, and the two or more pull-down transistors are arranged in different layers. The method of claim 11, wherein the column (row) decoder has a plurality of inverters, Each of the plurality of inverters includes at least one pull-up transistor and pull-down transistor, And the pull-up and pull-down transistors are stacked on at least two layers. 20. The method of claim 19, wherein the plurality of memory cells have a plurality of MOS transistors, And the plurality of MOS transistors are stacked on the at least two layers. 21. The method of claim 20, wherein the pull-up transistor is a PMOS transistor, And the pull-down transistors are NMOS transistors. 22. The semiconductor memory device according to claim 21, wherein the transistors arranged in one layer of at least two layers are bulk transistors, and the transistors arranged in two or more layers are thin film transistors. 23. The semiconductor memory device according to claim 22, wherein the first layer is capable of mixing and arranging transistors of some of the pull-up and pull-down transistors. 24. The semiconductor memory device according to claim 23, wherein only the pull-up transistors or only the pull-down transistors are disposed in each of the two or more layers. 25. The semiconductor memory device according to claim 24, wherein the channel width of each of the pull-up transistors is divided into two or more pull-up transistors, and the two or more pull-up transistors are arranged in different layers. 25. The semiconductor memory device according to claim 24, wherein the channel width of each of the pull-down transistors is divided into two or more pull-down transistors, and the two or more pull-down transistors are arranged in different layers. A memory cell array having a plurality of memory cells accessed in response to a plurality of word line selection signals and a plurality of column selection signals; A row decoder to decode a row address to generate the plurality of word line select signals; And A column decoder which decodes a column address to generate the plurality of column selection signals, The row (column) decoder has a plurality of inverters and a plurality of NAND gates, Each of the plurality of inverters includes at least one first pull-up transistor and a first pull-down transistor, and each of the plurality of NAND gates includes at least two or more second pull-up transistors and at least two or more second pull-down transistors. Equipped, And the first and second pull-up transistors and the first and second pull-down transistors are stacked on at least two layers. The memory device of claim 27, wherein the plurality of memory cells include a plurality of MOS transistors. And the plurality of MOS transistors are stacked on the at least two layers. 29. The method of claim 28, wherein the first and second pullup transistors are PMOS transistors, And the first and second pull-down transistors are NMOS transistors. 30. The semiconductor memory device according to claim 29, wherein the transistors arranged in one layer of at least two layers are bulk transistors, and the transistors arranged in two or more layers are thin film transistors. 31. The semiconductor memory device according to claim 30, wherein the first layer is capable of mixing and arranging transistors of the first pull-up and first pull-down transistors and some of the second pull-up and second pull-down transistors. 32. The semiconductor memory device of claim 31, wherein only the first pull-up and second pull-up transistors are disposed in each of the two or more layers, or only the first pull-down and second pull-down transistors are disposed. 33. The method of claim 32, wherein the channel width of each of the first and second pull-up transistors is divided into two or more first and second pull-up transistors, and the two or more first and second pull-up transistors are formed in different layers. The semiconductor memory device, characterized in that disposed in. 33. The method of claim 32, wherein the channel width of each of the first and second pull-down transistors is divided into two or more first and second pull-down transistors, and the two or more first and second pull-down transistors are formed in different layers. The semiconductor memory device, characterized in that disposed in. The method of claim 27, wherein the column (row) decoder has a plurality of inverters and a plurality of NAND gates, Each of the plurality of inverters includes at least one first pull-up transistor and a first pull-down transistor, and each of the plurality of NAND gates includes at least two or more second pull-up transistors and at least two or more second pull-down transistors. Equipped, And the first and second pull-up transistors and the first and second pull-down transistors are stacked on at least two layers. 36. The method of claim 35, wherein the plurality of memory cells comprise a plurality of MOS transistors, And the plurality of MOS transistors are stacked on the at least two layers. 37. The method of claim 36, wherein the first and second pullup transistors are PMOS transistors, And the first and second pull-down transistors are NMOS transistors. 38. The semiconductor memory device according to claim 37, wherein the transistors arranged in one layer of at least two or more layers are bulk transistors, and the transistors arranged in two or more layers are thin film transistors. 39. The semiconductor memory device of claim 38, wherein the first layer is capable of mixing and arranging transistors of the first pull-up and first pull-down transistors and a portion of the second pull-up and second pull-down transistors. 40. The semiconductor memory device of claim 39, wherein only the first pull-up and second pull-up transistors are disposed in each of the two or more layers, or only the first pull-down and second pull-down transistors are disposed. 41. The method of claim 40, wherein the channel widths of the first and second pull-up transistors are divided into two or more first and second pull-up transistors, and the two or more first and second pull-up transistors are formed on different layers. A semiconductor memory device, characterized in that disposed. 41. The method of claim 40, wherein the channel widths of the first and second pull-down transistors are divided into two or more first and second pull-down transistors, and the two or more first and second pull-down transistors are formed on different layers. A semiconductor memory device, characterized in that disposed. A memory cell array having a plurality of memory cells accessed in response to a plurality of word line selection signals and a plurality of column selection signals; And A row decoder to decode a row address to generate the plurality of word line selection signals, a column decoder to decode a column address to generate the plurality of column selection signals, and a controller to control input / output of data to the memory cell array With a peripheral circuit having a The peripheral circuit includes a plurality of inverters, a plurality of NAND gates, and a plurality of NOR gates, Each of the plurality of inverters includes at least one first pull-up transistor and a first pull-down transistor, and each of the plurality of NAND gates includes at least two or more second pull-up transistors and at least two or more second pull-down transistors. Each of the plurality of NOR gates includes at least three third pull-up transistors and at least three third pull-down transistors, And the first, second, and third pull-up transistors and the first, second, and third pull-down transistors are stacked on at least two layers. 44. The method of claim 43, wherein the plurality of memory cells comprise a plurality of MOS transistors, And the plurality of MOS transistors are stacked on the at least two layers. 45. The method of claim 44, wherein the first, second, and third pull-up transistors are PMOS transistors, And the first, second, and third pull-down transistors are NMOS transistors. 46. The semiconductor memory device according to claim 45, wherein the transistors arranged in one layer of at least two or more layers are bulk transistors, and the transistors arranged in two or more layers are thin film transistors. 47. The method of claim 46, wherein in the first layer, transistors of the first pull-up and the first pull-down transistors, the second pull-up and the second pull-down transistors, and a portion of the third pull-up and the third pull-down transistors are mixed. A semiconductor memory device, characterized in that possible. 48. The method of claim 47, wherein only the first pull-up, second pull-up, and third pull-up transistors are disposed in each of the two or more layers, or only the first pull-down, second pull-down, and third pull-down transistors are disposed. A semiconductor memory device. 49. The method of claim 48, wherein the channel widths of the first, second, and third pull-up transistors are divided into two or more first, second, and third pull-up transistors. And second and third pull-up transistors on different layers. 49. The apparatus of claim 48, wherein the channel widths of the first, second, and second pull-down transistors are divided into two or more first and second pull-down transistors, and the two or more first, second, and second And 3 pull-down transistors on different layers. Two transfer transistors, two first pull-up transistors, and two first pull-down transistors constituting each of the plurality of memory cells of the memory cell array are stacked on at least two layers, At least one second pull-up transistor and at least two third pull-up transistors and third pull-down transistors constituting each of the plurality of inverters of the peripheral circuit and the plurality of NAND gates And arranging the semiconductor memory device in a stack of at least two layers. The method of claim 51, wherein the first, second and third pull-up transistors are PMOS transistors, And the transfer, first, second and third pull-down transistors are NMOS transistors. 53. The method of claim 52, wherein the transistors arranged on one layer of at least two layers are bulk transistors, and the transistors disposed on two or more layers are thin film transistors. 55. The transistor of claim 53, wherein the transistors disposed on one layer of the at least two layers of the peripheral circuit are connected to the second pull-up and third pull-up transistors irrespective of the shape of the transistors disposed on one layer of the memory cell. And disposing transistors of some of the second pull-down and third pull-down transistors. 55. The method of claim 54, wherein only the second pull-up and third pull-up transistors having the same shape as that of the transistor disposed in each of the two or more layers of the at least two or more layers of the peripheral circuit are disposed or the second pull-down and the second pull-up transistors. A method of arranging a semiconductor memory device, characterized in that only three pull-down transistors are arranged. 57. The method of claim 55, wherein the channel widths of the second pull-up and third pull-up transistors are divided into two or more second pull-up and third pull-up transistors, and the two or more second pull-up and third pull-up transistors are configured. Arrangement method of a semiconductor memory device, characterized in that arranged in different layers. 56. The method of claim 55, wherein the channel widths of the second pulldown and third pulldown transistors are divided into two or more second pulldown and third pulldown transistors, and the two or more second pulldown and third pulldown transistors are separated from each other. Arrangement method of a semiconductor memory device, characterized in that arranged in a different layer. Two transfer transistors, two first pull-up transistors, and two first pull-down transistors constituting each of the plurality of memory cells of the memory cell array are stacked on at least two layers, At least one second pull-up transistor and second pull-down transistors constituting each of the plurality of inverters of the peripheral circuit, at least two or more third pull-up transistors and third pull-down transistors constituting each of the plurality of NAND gates. And arranging at least two or more fourth pull-up transistors and fourth pull-down transistors constituting each of a plurality of NOR gates in the at least two layers. 59. The method of claim 58, wherein the first, second, third, and fourth pull-up transistors are PMOS transistors, And the transfer, first, second, third, and fourth pull-down transistors are NMOS transistors. 60. The method of claim 59, wherein the transistors disposed in one layer of at least two layers are bulk transistors, and the transistors disposed in two or more layers are thin film transistors. 61. The method of claim 60, wherein the transistors disposed on one layer of the at least two layers of the peripheral circuit are second pull-ups, third pull-ups, and fourths irrespective of the type of transistors disposed on one layer of the memory cell. 12. A method of arranging a semiconductor memory device, characterized in that it is possible to mix and arrange pull-up transistors and some of the second pull-down, third pull-down and fourth pull-down transistors. 61. The method of claim 60, wherein only second pull-up, third pull-up, and fourth pull-up transistors having the same shape as that of a transistor disposed in each of the two or more layers of the at least two or more layers of the peripheral circuit are disposed or made. And arranging only second pull-down, third pull-down, and fourth pull-down transistors. 63. The method of claim 62, wherein the channel widths of the second pull-up, third pull-up, and fourth pull-up transistors are divided into two or more second, third, and fourth pull-up transistors, wherein the two or more second pull-ups, And arranging third and fourth pull-up transistors on different layers. 63. The method of claim 62, wherein the channel widths of the second pulldown, third pulldown, and fourth pulldown transistors are divided into two or more second pulldown, third pulldown, and fourth pulldown transistors. A pull down, a third pull down and a fourth pull down transistor are disposed in different layers.

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