CN1779979A

CN1779979A - Semiconductor device and methods of arranging and manufacturing same

Info

Publication number: CN1779979A
Application number: CNA2005101165515A
Authority: CN
Inventors: 韩公钦; 南孝润; 任普托
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2004-08-04
Filing date: 2005-08-04
Publication date: 2006-05-31
Anticipated expiration: 2025-08-04
Also published as: KR20060012847A; CN100530656C; KR100653699B1

Abstract

The invention discloses a semiconductor device and method for arranging and preparation. The semiconductor device comprises a plurality of inverters and a plurality of NAND doors, wherein the inverters comprise at least a first pull-up transistor and a first pull-down transistor which are respectively transformed and output input signals, the NAND doors comprise at least two second pull-up transistors and two pull-down transistors. If at least one of the two input singles is equipped with a low level, output signals with high lever are respectively produced, and at least a first pull-up transistor, a first pull-down transistor and at least two second pull-up transistors and two pull-down transistors are stacked and arranged on at least two layers.

Description

Semiconductor memory and layout thereof and manufacture method

Technical field

The present invention relates to integrated circuit (IC)-components, relate more specifically to the manufacture method of integrated circuit memory devices and integrated circuit memory devices.

Background technology

Traditional semiconductor memory comprises that the memory cell array of a plurality of memory cells with storage data and control are input to memory cell array/from the peripheral circuit of the data of memory cell array output.Static memory cell (for example, sram cell) comprises a plurality of transistors, and dynamic storage unit (for example, DRAM unit) comprises a transistor and a capacitor.Peripheral circuit comprises inverter, NAND door and NOR door, and wherein each door all comprises transistor.In typical memory cell and peripheral circuit, all a plurality of transistors all are arranged on same one deck of Semiconductor substrate top.Thereby when the capacity (that is, the quantity of memory cell) of memory cell array increased, the layout area size had also increased, and it causes big chip size.

For above-mentioned reason, studied to reduce the layout area size, even when the capacity of memory cell array increases.For example, introduced a kind of by the method (for example, referring to Fig. 5 A and 6A) of stacked transistors in memory cell with the layout area size that reduces memory cell array.

Yet,, can similarly reduce the total area size of semiconductor memory if reduce the layout area size of peripheral circuit and the layout area size of memory cell array.In addition, pile up, should have different structures so form the transistor of memory cell owing to will form the transistor of memory cell.

Summary of the invention

An object of the present invention is to provide a kind of semiconductor memory, it has the peripheral circuit of the memory cell array that is suitable for having stacked transistors.

Another object of the present invention provides a kind of method that is used to arrange and make semiconductor memory, and this semiconductor memory has the peripheral circuit of the memory cell array that is suitable for having stacked transistors.

The first embodiment of the present invention comprise comprise respectively at least one first pull up transistor and pull-down transistor and anti-phase and output input signal a plurality of inverters; If comprise that respectively at least two second pull up transistor and at least one of second pull-down transistor and two input signals has a plurality of NAND doors that low level just produces the output signal with high level at least, wherein at least one first pull up transistor and first pull-down transistor and at least two second pull up transistor and second pull-down stack of transistors be arranged in two-layer at least on.

Second embodiment of semiconductor device of the present invention comprise comprise respectively at least one first pull up transistor and first pull-down transistor and anti-phase and output input signal a plurality of inverters; If comprise that respectively at least two second pull up transistor and at least one of second pull-down transistor and two input signals has a plurality of NAND doors that low level just produces the output signal with high level at least; If comprise that respectively at least two the 3rd pull up transistor and the 3rd pull-down transistor and two input signals whole have a plurality of NOR doors that low level just produces the output signal with high level at least, wherein at least one first pull up transistor and first pull-down transistor, at least two second pull up transistor and second pull-down transistor and at least two the 3rd pull up transistor and the 3rd pull-down stack of transistors and be arranged in two-layer at least on.

This semiconductor memory first and second aspect in, first to the 3rd pulls up transistor is the PMOS transistor, first to the 3rd pull-down transistor is a nmos pass transistor.This semiconductor memory first and second aspect in, the transistor of waiting to be arranged on the ground floor is a body transistor, wait to be arranged in second or more multi-layered on transistor be thin-film transistor.This semiconductor memory first and second aspect in, some of first to the 3rd some that pull up transistor and first to the 3rd pull-down transistor are arranged on the ground floor jointly.Only first to the 3rd pull up transistor or only first to the 3rd pull-down transistor be arranged in second or more multi-layered on.

The 3rd embodiment of semiconductor memory of the present invention comprises: memory cell array, and it comprises response a plurality of word line selection signals and a plurality of array selecting signal and a plurality of memory cells of carrying out access; Row decoder is used for the decoded row address to produce a plurality of word line selection signals; And column decoder, the column address that is used to decode is to produce a plurality of array selecting signals; (row) decoder of wherein going comprises a plurality of inverters, and each of a plurality of inverters all comprises at least one and pulls up transistor and pull-down transistor, draws on this to pile up with pull-down transistor and be arranged at least two layers.

Row (row) decoder comprises a plurality of inverters, and each of a plurality of inverters all comprises at least one and pulls up transistor and pull-down transistor, draws with pull-down transistor accumulation on this and is arranged at least two layers.

A plurality of memory cells comprise a plurality of nmos pass transistors, and these a plurality of nmos pass transistors are piled up and are arranged at least two layers.Pulling up transistor is the PMOS transistor, and pull-down transistor is a nmos pass transistor.The transistor of waiting to be arranged on the ground floor is a body transistor, wait to be arranged in second or more multi-layered on transistor be thin-film transistor.Some of some that pull up transistor and pull-down transistor are arranged on the ground floor jointly.Only pull up transistor or only pull-down transistor be arranged in second or more multi-layered on.

The 4th embodiment of semiconductor memory of the present invention comprises memory cell array, and it comprises response a plurality of word line selection signals and a plurality of array selecting signal and a plurality of memory cells of carrying out access; Row decoder is used for the decoded row address to produce a plurality of word line selection signals; And column decoder, the column address that is used to decode is to produce a plurality of array selecting signals; (row) decoder of wherein going comprises a plurality of inverters and a plurality of NAND door, each of these a plurality of inverters all comprises at least one and first pulls up transistor and first pull-down transistor, each of these a plurality of NAND doors comprises at least two second and pulls up transistor and second pull-down transistor, and first and second pull up transistor and first and second pull-down transistors are piled up and are arranged at least two layers.

Row (row) decoder comprises a plurality of inverters and a plurality of NAND door, each of a plurality of inverters all comprises at least one and first pulls up transistor and first pull-down transistor, each of a plurality of NAND doors comprises at least two second and pulls up transistor and second pull-down transistor, and first and second pull up transistor and first and second pull-down transistors are piled up and are arranged at least two layers.

A plurality of memory cells comprise a plurality of nmos pass transistors, and these a plurality of nmos pass transistors are piled up and are arranged at least two layers.First and second pull up transistor is the PMOS transistor, and first and second pull-down transistors are nmos pass transistors.The transistor of waiting to be arranged on the ground floor is a body transistor, wait to be arranged in second or more multi-layered on transistor be thin-film transistor.Some of first and second some that pull up transistor and first and second pull-down transistors are arranged on the ground floor jointly.Only first and second pull up transistor or only first and second pull-down transistors be arranged in second or more multi-layered on.

The 5th embodiment of semiconductor memory of the present invention comprises; Memory cell array, it comprises response a plurality of word line selection signals and a plurality of array selecting signal and a plurality of memory cells of carrying out access; And peripheral circuit, it comprises and is used for the decoded row address to produce the row decoder of a plurality of word line selection signals, be used to decode column address to produce the column decoder of a plurality of array selecting signals, be input to memory cell array/with being used to control from the controller of memory cell array output, wherein peripheral circuit comprises a plurality of inverters, a plurality of NAND doors, with a plurality of NOR doors, each of these a plurality of inverters comprises at least one and first pulls up transistor and first pull-down transistor, each of these a plurality of NAND doors all comprises at least two second and pulls up transistor and second pull-down transistor, each of these a plurality of NOR doors all comprises at least three the 3rd and pulls up transistor and the 3rd pull-down transistor, and first to the 3rd pulls up transistor and first to the 3rd pull-down transistor is piled up and is arranged at least two layers.

A plurality of memory cells comprise a plurality of nmos pass transistors, and these a plurality of nmos pass transistors are piled up and are arranged at least two layers.First to the 3rd pulls up transistor is the PMOS transistor, and first to the 3rd pull-down transistor is a nmos pass transistor.The transistor of waiting to be arranged on the ground floor is a body transistor, wait to be arranged in second or more multi-layered on transistor be thin-film transistor.Some of first to the 3rd some that pull up transistor and first to the 3rd pull-down transistor are arranged on the ground floor jointly.Only first to the 3rd pull up transistor or only first to the 3rd pull-down transistor be arranged in second or more multi-layered on.

The 6th embodiment of semiconductor device comprises the Semiconductor substrate with unit area and peripheral circuit region, is arranged in the transistor on the Semiconductor substrate of unit area; Be arranged in the unit area with the transistorized interlevel insulator pattern of nappe; Be arranged in the thin-film transistor on the interlevel insulator pattern; Layout is with the peripheral main body pattern of the Semiconductor substrate of contact peripheral circuit region; With the periphery transistor that is arranged in the peripheral main body pattern, arrange the periphery transistor that is positioned at the Virtual water horizontal line substantially the same with the unit area thin-film transistor.Peripheral main body pattern is a single crystalline semiconductor structure.Thin-film transistor is the monocrystal thin films transistor.Body transistor and thin-film transistor are the transistor units of SRAM memory cell.

Body transistor comprises first and second body transistors, and thin-film transistor comprises first and second thin-film transistors, arranges that first and second thin-film transistors are with overlapping first and second body transistors of difference.Semiconductor device also comprises first and second times thin-film transistors that are arranged between first and second body transistor and first and second thin-film transistor, arranges that wherein first and second times thin-film transistors are with overlapping first and second body transistors of difference.

Semiconductor device also comprises by interlevel insulator and is electrically connected first ion doped region of first ion doped region of first body transistor, first time thin-film transistor and the first node connector of transistorized first ion doped region of first upper film; With first ion doped region of first ion doped region that is electrically connected second body transistor by interlevel insulator, second time thin-film transistor and the second node connector of transistorized first ion doped region of second upper film.First and second body transistors are respectively the first and second n channel driver transistors, and first ion doped region of first and second body transistors is drain regions.The gate electrode of first driving transistors is electrically connected to the second node connector, and the grid of second driving transistors is electrically connected to the first node connector.

First and second times thin-film transistors are respectively the first and second p raceway groove load transistors, first and second thin-film transistors are first and second n type channel pass transistor, first ion doped region of first and second times thin-film transistors is drain regions, and first ion doped region of first and second thin-film transistors is source areas.Arrange the gate electrode of the gate electrode of first and second load transistors with overlapping first and second driving transistorss, the gate electrode of first load transistor is electrically connected to the second node connector, and the gate electrode of second load transistor is electrically connected to the first node connector.The gate electrode of first and second thin-film transistors is electrically connected mutually to form word line.At least periphery transistor comprises the lip-deep metal silicide layer that is arranged in the peripheral gate electrode.At least periphery transistor comprises the lip-deep metal silicide layer that is arranged in peripheral source area and drain region.

First aspect according to the method for arranging of semiconductor memory of the present invention comprises: pile up on two-layer at least and each two transmission transistors, two first of arranging a plurality of memory cells of forming memory cell array pull up transistor, two first pull-down transistors; And pile up on two-layer at least and arrange that each at least one of a plurality of inverters of forming peripheral circuit second pulls up transistor and second pull-down transistor and each two the 3rd that form a plurality of NAND doors pull up transistor and the 3rd pull-down transistor at least.

First to the 3rd pulls up transistor is the PMOS transistor, and first to the 3rd pull-down transistor is a nmos pass transistor.The transistor of waiting to be arranged on the ground floor is a body transistor, wait to be arranged in second or more multi-layered on transistor be thin-film transistor.

No matter wait to be arranged on the ground floor of memory cell array transistorized type how, wait to be arranged in transistor on the ground floor among peripheral circuit two-layer at least and be and can pull up transistor and some one of arranging of the second and the 3rd pull-down transistor with the second and the 3rd.Only arrange have be arranged in peripheral circuit two-layer at least second or more multi-layered on the second and the 3rd the pulling up transistor or the second and the 3rd pull-down transistor of the identical type of transistor.

Second aspect according to the method for arranging of semiconductor memory of the present invention comprises: pile up on two-layer at least and each two transmission transistors, two first of arranging a plurality of memory cells of forming memory cell array pull up transistor, two first pull-down transistors; Pile up on two-layer at least and arrange that each at least one of a plurality of inverters of forming peripheral circuit second pulls up transistor and second pull-down transistor, each two the 3rd that form a plurality of NAND doors pull up transistor and the 3rd pull-down transistor, each two the 4th that form a plurality of NOR doors pull up transistor and the 4th pull-down transistor at least at least.

First to fourth pulls up transistor is the PMOS transistor, and first to fourth pull-down transistor is a nmos pass transistor.The transistor of waiting to be arranged on the ground floor is a body transistor, wait to be arranged in second or more multi-layered on transistor be thin-film transistor.

Wait to be arranged in transistor on the ground floor among peripheral circuit two-layer at least and be and can pull up transistor and some one of arranging of second to the 4th pull-down transistor with second to the 4th, and no matter wait to be arranged on the ground floor of memory cell array transistorized type how.Only arrange have be arranged in peripheral circuit two-layer at least second or more multi-layered on second to the 4th the pulling up transistor or second to the 4th pull-down transistor of the identical type of transistor.

The first aspect of the manufacture method of semiconductor device comprises: prepare to have the Semiconductor substrate of unit area and peripheral circuit region; Organizator transistor on the Semiconductor substrate of cellular zone; Has the interlevel insulator pattern that forms the Semiconductor substrate that exposes peripheral circuit region on the Semiconductor substrate of body transistor; On the expose portion of Semiconductor substrate and interlevel insulator pattern, form unit main body pattern and peripheral main body pattern, the expose portion of wherein peripheral main body pattern contact semiconductor substrate; In unit main body pattern and peripheral main body pattern, form unit film transistor and periphery transistor respectively.

The step that forms unit main body pattern and peripheral main body pattern is included on the Semiconductor substrate with interlevel insulator pattern and forms semiconductor layer; With the described semiconductor layer of planarization on the Semiconductor substrate of interlevel insulator pattern and peripheral circuit region, to form elemental semiconductor layer and peripheral semiconductor layer, wherein peripheral semiconductor layer is than described semiconductor bed thickness.Described semiconductor layer is formed by non-single crystal semiconductor layer.

The method of first aspect comprises that also use used the solid phase epitaxy layer crystalline semiconductor layer of Semiconductor substrate as inculating crystal layer before or after the planarization semiconductor layer.The step of insulator pattern is included on the Semiconductor substrate with body transistor and forms interlevel insulator between cambium layer; With the contact hole of patterning interlevel insulator with the fate of the Semiconductor substrate of the Semiconductor substrate that form to expose peripheral circuit region and cellular zone.

The step that forms unit main body pattern and peripheral main body pattern is included on the expose portion of Semiconductor substrate of peripheral circuit region and the interlevel insulator pattern and forms single crystalline semiconductor structure; With this single crystalline semiconductor structure of planarization.

Semiconductor substrate by utilize using the exposure that is touched Semiconductor substrate that the hole exposes and peripheral circuit region forms single crystalline semiconductor structure as the selective epitaxial growth technology of inculating crystal layer.The step that forms unit film transistor and periphery transistor comprises: form respectively unit gate electrode and peripheral gate electrode across unit main body pattern and peripheral main body pattern; Use gate electrode to come ion doping unit main body pattern and peripheral main body pattern, in the unit main body pattern, to form source, unit and drain region and in peripheral main body pattern, to form peripheral source and drain region as the ion doping mask.The method of first aspect also is included on the surface of peripheral gate electrode and/or peripheral source and drain region and forms metal silicide layer selectively.

The second aspect of the manufacture method of semiconductor device comprises: prepare to have the Semiconductor substrate of unit area and peripheral circuit region; Organizator transistor on the Semiconductor substrate of cellular zone; Have insulator pattern between the ground floor that forms the Semiconductor substrate that exposes peripheral circuit region on the Semiconductor substrate of body transistor, insulator pattern has first contact hole of the fate of the ion doped region that exposes body transistor between this ground floor; Be formed for covering main body under the unit of first contact hole on the insulator pattern between ground floor; Under the unit, form thin-film transistor under the unit in the main body pattern; Form insulator pattern between the second layer, be used to cover between ground floor thin-film transistor under the unit on the insulator pattern, insulator pattern has second contact hole of the fate of the ion doped region of thin-film transistor under the exposure unit between this second layer; Be formed for covering main body pattern on the unit of second contact hole on the peripheral main body pattern between the second layer in insulator pattern and the peripheral circuit region; With form unit upper film transistor in the main body pattern on the unit and in peripheral main body pattern, form periphery transistor.

The method of second aspect also comprises the peripheral main body pattern in unit that forms following main body pattern and be used to cover the Semiconductor substrate of peripheral circuit region.Forming main body pattern and the peripheral step of main body pattern down under the unit comprises and forms first single crystalline semiconductor structure of filling first contact hole and covering the Semiconductor substrate of insulator pattern and peripheral circuit region between ground floor; With this first single crystalline semiconductor structure of planarization.

The step of main body pattern and peripheral main body pattern comprises on the formation unit: second single crystalline semiconductor structure of the Semiconductor substrate of insulator pattern and peripheral circuit region between formation filling second contact hole and the covering second layer; This second single crystalline semiconductor structure of planarization; Place the main body pattern with patterning second single crystalline semiconductor structure with main body pattern on the formation unit in cellular zone with outside in peripheral circuit region, forming, thereby form the peripheral main body pattern that has peripheral main body pattern down and place the main body pattern outward.By using epitaxy technology to form single crystalline semiconductor structure.

The step that forms main body pattern under the unit comprises: first single crystalline semiconductor structure of the Semiconductor substrate of insulator pattern and peripheral circuit region between formation filling first contact hole and covering ground floor; With the Semiconductor substrate of patterning first single crystalline semiconductor structure with the exposure peripheral circuit region.

Form the step of main body pattern and peripheral main body pattern on the unit and comprise and form second single crystalline semiconductor structure of filling second contact hole and covering the Semiconductor substrate of insulator pattern and peripheral circuit region between the second layer that this this second single crystalline semiconductor structure has flat upper surfaces; With patterning second single crystalline semiconductor structure, in cellular zone, to form on the unit main body pattern and in peripheral circuit region, to form peripheral main body pattern.By using epitaxy technology to form single crystalline semiconductor structure.

Body transistor is the n channel driver transistors, and thin-film transistor is a p raceway groove load transistor under the unit, and unit upper film transistor is the n channel pass transistor.The step that forms unit upper film transistor and periphery transistor comprises that formation is respectively across gate electrode on the unit of main body pattern on the unit and peripheral main body pattern with place gate electrode outward; With use gate electrode as main body pattern and peripheral main body pattern on the ion doping mask ion doping unit to form cell source district and drain region in the main body pattern on the unit and in peripheral main body pattern, to form peripheral source area and drain region.The method of second aspect also is included on the surface of peripheral gate electrode and/or peripheral source area and drain region and forms metal silicide layer selectively.

Description of drawings

Fig. 1 is the block diagram of the typical semiconductor memory of explanation;

Fig. 2 is the row decoder of semiconductor memory of key diagram 1 or the block diagram of column decoder;

Fig. 3 A to 3D is the static storage cell of explanation memory cell array and the circuit diagram of forming inverter, NAND door and the NOR door of peripheral circuit in the semiconductor memory of routine;

Fig. 4 A to 4D is that the transistor of static storage cell and the view of the transistorized layout of forming inverter, NAND door and NOR door are formed in explanation in conventional semiconductor memory;

Fig. 5 A to 5D illustrates the transistor of static storage cell and the view of the transistorized different layouts of inverter, NAND door and the NOR door of forming peripheral circuit respectively in conventional semiconductor memory;

Fig. 6 A to 6D illustrates the transistor of static storage cell and the view of transistorized another different layouts of inverter, NAND door and the NOR door of forming peripheral circuit respectively in conventional semiconductor memory;

Fig. 7 A to 7D illustrates according to the transistor of the static storage cell of first embodiment of the invention respectively and forms the view of transistorized layout of inverter, NAND door and NOR door of the peripheral circuit of semiconductor memory;

Fig. 8 A to 8D illustrates according to the transistor of the static storage cell of second embodiment of the invention respectively and forms the view of transistorized layout of inverter, NAND door and NOR door of the peripheral circuit of semiconductor memory;

Fig. 9 A to 9D illustrates according to the transistor of the static storage cell of third embodiment of the invention respectively and forms the view of transistorized layout of inverter, NAND door and NOR door of the peripheral circuit of semiconductor memory;

Figure 10 A to 16D is the plane graph of explanation according to the memory cell of the embodiment of the invention, inverter, NAND door, NOR door layout separately;

Figure 17 A and 17B are that edge explanation respectively is according to the line I-I ' of Figure 16 A of the memory cell structure of the embodiment of the invention and the profile of II-II;

Figure 18 to 20 is along the profile of explanation according to the line X-X ' of Figure 10 B to 16B, Figure 10 C to 16C of the structure of the memory cell of the embodiment of the invention and Figure 10 D to 16D;

Figure 21 A and 21B are the view of explanation according to the stacked structure of the memory cell array of first embodiment of the invention and peripheral circuit;

Figure 22 A and 22B are the view of explanation according to the stacked structure of the memory cell array of second embodiment of the invention and peripheral circuit;

Figure 23 A and 23B are the view of explanation according to the stacked structure of the memory cell array of third embodiment of the invention and peripheral circuit;

Figure 24 A and 24B illustrate according to the transistor of the static storage cell of fourth embodiment of the invention respectively and form the view of transistorized layout of inverter of the peripheral circuit of semiconductor memory;

Figure 25 is the plane graph of inverter of the peripheral circuit of key diagram 24B; With

Figure 26 A and 26B to Figure 34 A and 34B are the profiles of the manufacture method of explanation memory cell and inverter.

Embodiment

Now, will more fully describe the present invention with reference to the accompanying drawings hereinafter, the preferred embodiments of the present invention have been shown in the accompanying drawing.Yet the present invention can embody with different form, and should not be interpreted as is restriction to embodiment set forth herein.On the contrary, provide this embodiment, and scope of the present invention is conveyed to those skilled in the art fully so that comprehensively also intactly openly.In the accompanying drawings, for the sake of clarity, the thickness of having exaggerated floor and having distinguished.Identical numeral components identical in whole specification.

Fig. 1 is the block diagram of explanation typical semiconductor storage component part.The semiconductor memory of Fig. 1 comprises memory cell array 10, row decoder 12, data I/O door 14, column decoder 16, data I/O circuit 18 and controller 20.In Fig. 1, wl1 to wlm represents word line selection signal, and y1 to yn represents array selecting signal, and WL1 to WLm represents word line, and BL1, BL1B to BLn, BLnB represent that bit line is right.The functions of components of the semiconductor memory of Fig. 1 will be described below.

Memory cell array 10 comprises and is connected to each word line WL1 to WLm and each bit line to a plurality of static storage cell MC11 to MCmn between BL1, BL1B to BLn, the BLnB, during write operation, receive data din and write in the memory cell of selection, and during read operation, read data and the dateout dout that is stored in the selected memory cell.Row decoder 12 decode line address RA produce word line selection signal wl1 to wlm with response proactive command ACT.Data I/O door 14 response array selecting signal y1 to yn transmission during the write operation as the data Din of data din and during read operation transmission as the data dout of data Dout.Column decoder 16 decoding column address CA produce array selecting signal y1 to yn with response read and write order RD, WR.Data I/O circuit 18 receives data DIN and responds write order WR dateout Din and receive data Dout and respond read command RD dateout DOUT.Controller 20 receives order COM to produce proactive command ACT, read command RD and write order WR.

Fig. 2 is the row decoder of semiconductor memory of key diagram 1 or the block diagram of column decoder.The decoder of Fig. 2 comprises two pre-decode devices 30 and 32 and main decoder 34.Two pre-decode devices 30 and 32 and main decoder 34 comprise two input NAND door NA and inverter INV respectively.The decoder of Fig. 2 disposed receive 4 bit address A1 to A4, to produce 16 decoded signal DRA1 to DRA16.Below with the functions of components of the decoder of key diagram 2.

Each pre-decode device 30 and 32 decodings two 2 bit address A1, A2 and A3.A4 are with output pre-decode signal DRA1B2B to DRA12 and DRA3B4B to DRA34.Main decoder 34 decoding pre-decode signal DRA1B2B to DRA12 and DRA3B4B to DRA34 are to produce decoded signal DRA1 to DRA16.The static storage cell of the memory cell array of this semiconductor memory comprises six (6) individual transistors, and row or row decoder comprise gate, for example inverter and NAND door.Inverter comprises two transistors, and the NAND door comprises at least 4 transistors.The row of Fig. 2 or row decoder comprise two input NAND doors, thereby are made up of four transistors, but comprise that at the decoder of Fig. 2 three inputs or four import the situation of NAND doors, and it is made up of 6 or 8 transistors.Data I/O circuit 18 and controller 20 also comprise the NOR door except that inverter and NAND door.

Fig. 3 A is the circuit diagram of static storage cell of the memory cell array of key diagram 1.Fig. 3 B to 3D is the circuit diagram that inverter, NAND door and the NOR door of forming peripheral circuit are described respectively.As shown in Figure 3A, static storage cell comprises PMOS transistor PU1 and PU2 and nmos pass transistor PD1, PD2, T1 and T2.PMOS transistor PU1 and PU2 pull up transistor, and nmos pass transistor is a pull-down transistor, and nmos pass transistor T1 and T2 are transmission transistors.The operation of the static storage cell of Fig. 3 A will be described below.

If select word line WL to make nmos pass transistor T1 and T2 conducting, then data are transmitted between bit line BL and storage node a, and data are transmitted between anti-phase bit line BLB and storage node b.If the data of storage node b have high level, then nmos pass transistor PD1 makes storage node a have low level, if the data of storage node b have low level, then PMOS transistor PU1 makes storage node have high level.Similarly, if the data of storage node a have high level, then nmos pass transistor PD2 makes storage node b have low level, if the data of storage node a have low level, then PMOS transistor PU2 makes storage node b have high level.That is to say the data that two PMOS transistor PU1 and PU2 and two nmos pass transistor PD1 and PD2 serve as latch and latch stores node a and b.

Shown in Fig. 3 B, inverter comprises PMOS transistor P1 and nmos pass transistor N1.In Fig. 3 B, PMOS transistor P1 pulls up transistor, and nmos pass transistor N1 is a pull-down transistor.The operation of the inverter of Fig. 3 B is as follows.If input has the input signal IN of high level, then make nmos pass transistor N1 conducting so that output signal OUT has low level, that is, and earthed voltage Vcc level.On the other hand,, then make the P1 conducting of PMOS transistor so that output signal OUT has high level if input has low level input signal IN, that is, and supply voltage Vss level.That is to say that the inverter of Fig. 3 B pulls up transistor by one and a pull-down transistor is formed, and rp input signal IN is to produce output signal OUT.

Shown in Fig. 3 C, the NAND door comprises PMOS transistor P2 and P3 and nmos pass transistor N2 and N3.In Fig. 3 C, PMOS transistor P2 and P3 pull up transistor, and nmos pass transistor N2 and N3 are pull-down transistors.The operation of the NAND door of Fig. 3 C is as follows.If apply at least one that has among low level input signal IN1 and the IN2, then make PMOS transistor P2 and/or the P3 conducting of PMOS transistor so that output signal OUT has high level, i.e. the power source voltage Vcc level.On the other hand, if apply input signal IN1 and IN2, then make nmos pass transistor N2 and N3 conducting so that output signal OUT has low level with high level.

Shown in Fig. 3 D, the NOR door comprises PMOS transistor P4 and P5 and nmos pass transistor N4 and N5.In Fig. 3 D, PMOS transistor P3 and P4 pull up transistor, and nmos pass transistor is a pull-down transistor.The operation of the NOR door of Fig. 3 D is as follows.If apply input signal IN1 with high level and at least one among the IN2, then make nmos pass transistor N4 and/or nmos pass transistor N5 conducting so that output signal OUT has low level, i.e. earthed voltage Vss level.On the other hand, have low level input signal IN1 and IN2, then make PMOS transistor P4 and P5 conducting so that output signal OUT has high level if apply.

Fig. 4 A is the view of transistorized layout of the static storage cell of explanation composition diagram 3A.Fig. 4 B to 4D is the view that the transistorized layout of the inverter shown in the composition diagram 3B to 3D, NAND door and NOR door is described respectively.In Fig. 4 A to 4D, bit line seems to be arranged on the different layers to BL and BLB, word line WL, power voltage line VCCL and ground voltage line VSSL, but they always are not arranged on the different layers.

Shown in Fig. 4 A, transistor PD1, PD2, PU1, PU2, T1 and the T2 of Fig. 3 A is arranged on the identical layer 1F.The source electrode of nmos pass transistor T1 is connected in the drain electrode of nmos pass transistor PD1, and the source electrode of nmos pass transistor PD1 is connected on the source electrode of nmos pass transistor PD2, and the drain electrode of nmos pass transistor PD2 is connected to the source electrode of nmos pass transistor T2.The drain electrode of nmos pass transistor T1 connects bit line BL, and the drain electrode of nmos pass transistor T2 connects anti-phase bit line BLB, and the grid of nmos pass transistor T1 and T2 is connected word line, and the source electrode of nmos pass transistor PD1 and PD2 is connected ground voltage line VSSL.The drain electrode of PMOS transistor PU1 connects the source electrode of nmos pass transistor PD1, and the source electrode of PMOS transistor PU1 connects power voltage line VCCL, and the grid of PMOS transistor PU1 connects the grid of nmos pass transistor PD1 and the drain electrode of nmos pass transistor PD2.The drain electrode of PMOS transistor PU2 connects the drain electrode of nmos pass transistor PD2, and the source electrode of PMOS transistor PU2 connects power voltage line VCCL, and the grid of PMOS transistor PU2 connects the grid of nmos pass transistor PD2.

Shown in Fig. 4 B, transistor P1 and the N1 of Fig. 3 B is arranged on the identical layer 1F.PMOS transistor P1 has the source electrode that is connected to power voltage line VCCL, be connected to the drain electrode of output signal line OUTL and be connected to the grid of input signal cable INL.Nmos pass transistor N1 has the source electrode that is connected to ground voltage line VSSL, be connected to the drain electrode of output signal line OUTL and be connected to the grid of input signal cable INL.

Shown in Fig. 4 C, transistor P2, P3, N2 and the N3 of Fig. 3 C is arranged on the identical layer 1F.The source electrode of PMOS transistor P3 connects the source electrode of PMOS transistor P2, and the drain electrode of PMOS transistor P3 connects output signal line OUTL.The grid of PMOS transistor P3 and nmos pass transistor N3 is connected input signal cable IN1L, the grid of PMOS transistor P2 and nmos pass transistor N2 is connected input signal cable IN2L, the drain electrode of PMOS transistor P2 and nmos pass transistor N2 is connected, the source electrode of nmos pass transistor N2 and N3 is connected, and the drain electrode of nmos pass transistor N3 connects ground voltage line VSSL.

Shown in Fig. 4 D, transistor P4, P5, N4 and the N5 of Fig. 3 D is arranged on the identical layer 1F.The drain electrode of PMOS transistor P4 connects the source electrode of PMOS transistor P5, the drain electrode of PMOS transistor P5 connects the drain electrode of nmos pass transistor N5, the source electrode of PMOS transistor P4 and grid are connected respectively on power voltage line VCCL and the input signal cable IN2L, the grid of PMOS transistor P5 connects input signal cable IN1L, the drain electrode of PMOS transistor P5 and nmos pass transistor N5 is connected output signal line OUTL, and the drain electrode of nmos pass transistor N4, grid and source electrode are connected respectively to output signal line OUTL, input signal cable IN2L and ground voltage line VSSL.

Shown in Fig. 4 A to 4D, form the memory cell of conventional semiconductor memory and all transistors of peripheral circuit and all be arranged on the identical layer 1F, thereby under the situation of the capacity that increases memory cell, also increased the layout area size.

For the layout area size of the memory cell that reduces semiconductor memory, introduced two-layer or three layers on form the transistorized method of layout of memory cell.Fig. 5 A to 5D is the view of transistorized different layouts that the transistor of the static storage cell in conventional semiconductor memory has been described respectively and has formed inverter, NAND door and the NOR door of peripheral circuit, and the transistor layout of wherein forming memory cell is on two-layer.

Shown in Fig. 5 A, nmos pass transistor PD1, PD2, T1 and T2 are arranged on the ground floor 1F, and PMOS transistor PU1 and PU2 are arranged on the second layer 2F.Connection between transistor PD1, PD2, PU1, PU2, T1 and the T2 is consistent with Fig. 4 A's.The layout of similar Fig. 4 B to 4D, the transistor P1 to P5 and the N1 to N5 that form Fig. 5 B to 5D of inverter, NAND door and NOR door are arranged on the ground floor 1F.Therefore, shown in Fig. 5 A, if the transistor layout of forming memory cell on two-layer, the transistor layout of forming peripheral circuit has then reduced the cloth layout area size of memory cell array, but has not reduced the layout area size of peripheral circuit on one deck.

Fig. 6 A to 6D has illustrated the transistor of the static storage cell in conventional semiconductor memory and the view of transistorized another different layouts of inverter, NAND door and the NOR door of forming peripheral circuit respectively, and the transistor layout of wherein forming memory cell is on three layers.

As shown in Figure 6A, nmos pass transistor PD1 and PD2 are arranged on the ground floor 1F, and PMOS transistor PU1 and PU2 are arranged on the second layer 2F, and access transistor T1 and T2 are arranged on the 3rd layer of 3F.Connection between transistor PD1, PD2, PU1, PU2, T1 and the T2 is consistent with Fig. 4 A's.

The layout of similar Fig. 4 B to 4D, the transistor P1 to P5 and the N1 to N5 that form Fig. 6 B to 6D of inverter, NAND door and NOR door are arranged on the ground floor 1F.Therefore, as shown in Figure 6A, if the transistor layout of forming memory cell on three layers, and the crystal deployment tube of forming peripheral circuit is on one deck, then reduce the layout area size of memory cell array, but do not reduced the layout area size of peripheral circuit.In the routine of semiconductor memory is arranged, by two-layer or three layers on arrange to form static storage cell transistor reduce the layout area size of memory cell array, but because the transistor layout of composition peripheral circuit is on one deck, so do not reduce the layout area size of peripheral circuit.

Fig. 7 A to 7D illustrates according to the transistor of the static storage cell of first embodiment of the invention respectively and forms the figure of transistorized layout of inverter, NAND door and NOR door of the peripheral circuit of semiconductor memory.Especially, Fig. 7 A to 7D shows the transistorized layout of forming peripheral circuit under the situation of the transistor layout of forming memory cell on two-layer.

The layout of similar Fig. 5 A, transistor PD1, PD2, PU1PU2, T1 and the T2 that forms Fig. 7 A of static storage cell be arranged in two-layer on.Shown in Fig. 7 B, nmos pass transistor N1 is arranged on the ground floor 1F, and PMOS transistor P1 is arranged on the second layer 2F.The transistor N1 of composition inverter and the connection between the P1 and Fig. 4 B's is consistent.Shown in Fig. 7 C, nmos pass transistor N2 and N3 are arranged on the ground floor 1F, and PMOS transistor P2 and P3 are arranged on the second layer 2F.Connection between transistor N2, N3, P2 and the P3 of composition NAND door and Fig. 4 C's is consistent.Shown in Fig. 7 D, nmos pass transistor N4 and N4 are arranged on the ground floor 1F, and PMOS transistor P4 and P5 are arranged on the second layer 2F.Connection between transistor N4, N5, P4 and the P5 of composition NOR door and Fig. 4 D's is consistent.Shown in Fig. 7 A to 7D, semiconductor memory of the present invention is by arranging the transistor of forming memory cell and arrange that the transistor of forming peripheral circuit has reduced the layout area size on two-layer on two-layer.The transistor layout of Fig. 7 B to 7D is being different from the layer shown in Fig. 7 A to 7D.For example, transistor needn't always be arranged on first and second layers, and can be arranged on first and the 3rd layer or second and the 3rd layer.

Yet PMOS transistor and nmos pass transistor are arranged on the ground floor, but for the ease of manufacturing process, preferably arrange on the second layer 2F with the second layer that is arranged in memory cell on the transistor of transistor same type.For example, if the transistor of waiting to be arranged on the second layer 2F of memory cell is a nmos pass transistor, then preferred arrangements waits to be arranged in the nmos pass transistor on the second layer 2F of peripheral circuit, if the transistor of waiting to be arranged on the second layer 2F of memory cell is the PMOS transistor, then preferred arrangements waits to be arranged in the PMOS transistor on the second layer 2F of peripheral circuit.

Fig. 8 A to 8D illustrates according to the transistor of the static storage cell of second embodiment of the invention respectively and forms the figure of transistorized layout of inverter, NAND door and NOR door of the peripheral circuit of semiconductor memory.Especially, Fig. 8 A to 8D shows the transistorized layout of forming peripheral circuit in the transistor layout of forming memory cell under the situation on three layers.The layout of similar Fig. 6 A arranges that the transistor of Fig. 8 A that forms static storage cell makes pull-down transistor PD1 and PD2 be arranged on the ground floor 1F, and pull up transistor PU1 and PU2 are arranged on the second layer 2F, and transmission transistor T1 and T2 are arranged on the 3rd layer.Shown in Fig. 8 B, arrange the nmos pass transistor N1-1 and the N1-2 of 1/2 channel width of the channel width of the nmos pass transistor N1 with Fig. 3 B.Nmos pass transistor N1-2 is arranged on the ground floor 1F, and PMOS transistor P1 is arranged on the second layer 2F, and nmos pass transistor N1-1 is arranged on the 3rd layer of 3F.The grid of nmos pass transistor N1-1 and N1-2, drain electrode and source electrode are connected jointly, and the connection between nmos pass transistor N1-1 and N1-2 and the PMOS transistor P1 and Fig. 4 B's is consistent.

Shown in Fig. 8 C, PMOS transistor P2 and nmos pass transistor N2 are arranged on the ground floor 1F, and PMOS transistor P3 is arranged on the second layer 2F, and nmos pass transistor N3 is arranged on the 3rd layer of 3F.Connection between PMOS transistor P2 and P3 and nmos pass transistor N2 and the N3 and Fig. 4 C's is consistent.

Shown in Fig. 8 D, the nmos pass transistor N5-1 and the N5-2 of 1/2 channel width that has arranged the nmos pass transistor N4-1 of 1/2 channel width and the N4-2 of channel width and had the channel width of nmos pass transistor N5 with nmos pass transistor N4.Nmos pass transistor N4-1 and N4-2 are arranged on the ground floor 1F, and PMOS transistor P4 and P5 are arranged on the second layer 2F, and nmos pass transistor N5-1 and N5-2 are arranged on the 3rd layer of 3F.The grid of nmos pass transistor N4-1 and N4-2, source electrode and drain electrode are connected jointly, and grid, source electrode and the drain electrode of nmos pass transistor N5-1 and N5-2 are connected jointly.Connection between PMOS transistor P4 and P5 and nmos pass transistor N4 and the N5 and Fig. 4 D's is consistent.

Shown in Fig. 8 A to 8D, semiconductor memory of the present invention is by arranging the transistor of forming memory cell and arranging that on three layers the transistor of forming peripheral circuit reduces the layout area size on three layers.

Fig. 9 A to 9D illustrates according to the transistor of the static storage cell of third embodiment of the invention respectively and forms the figure of transistorized layout of inverter, NAND door and NOR door of the peripheral circuit of semiconductor memory.Especially, Fig. 9 A to 9D shows the transistorized layout of forming peripheral circuit in the transistor layout of forming memory cell under the situation on three layers.The layout of similar Fig. 8 A, the transistor layout of Fig. 9 A of composition static storage cell is on three layers.

Shown in Fig. 9 B, arrange the PMOS transistor P1-1 and the P1-2 of 1/2 channel width of channel width with the PMOS transistor P1 that forms inverter.PMOS transistor P1-1 is arranged on the ground floor 1F, and PMOS transistor P1-2 is arranged on the second layer 2F, and nmos pass transistor N1 is arranged on the 3rd layer of 3F.Grid, drain electrode and the source electrode of PMOS transistor P1-1 and P1-2 are connected jointly, and the connection between PMOS transistor P1-1 and P1-2 and the nmos pass transistor N1 and Fig. 4 B's is consistent.

Shown in Fig. 9 C, arranged PMOS transistor P2-1 and P2-2 and the PMOS transistor P3-1 and the P3-2 of 1/2 channel width of the channel width separately that has the PMOS transistor P2 that forms the NAND door and P3 respectively.PMOS transistor P2-2 and P3-2 are arranged on the ground floor 1F, and PMOS transistor P2-1 and P3-1 are arranged on the second layer 2F, and nmos pass transistor N2 and N3 are arranged on the 3rd layer of 3F.Grid, drain electrode and the source electrode of PMOS transistor P2-1 and P2-2 are connected jointly, grid, drain electrode and the source electrode of PMOS transistor P3-1 and P3-2 are connected jointly, and the connection between PMOS transistor P2-1, P2-2P3-1 and P3-2 and nmos pass transistor N2 and the N3 and Fig. 4 C's is consistent.

Shown in Fig. 9 D, arranged PMOS transistor P4-1 and P4-2 and the PMOS transistor P5-1 and the P5-2 of 1/2 channel width of the channel width separately that has the PMOS transistor P4 that forms the NOR door and P5 respectively.PMOS transistor P4-1 and P5-1 are arranged on the ground floor 1F, and PMOS transistor P4-2 and P5-2 are arranged on the second layer 2F, and nmos pass transistor N4 and N5 are arranged on the 3rd layer of 3F.Grid, drain electrode and the source electrode of PMOS transistor P4-1 and P4-2 are connected jointly, grid, drain electrode and the source electrode of PMOS transistor P5-1 and P5-2 are connected jointly, and the connection between PMOS transistor P4-1, P4-2, P5-1 and P5-2 and nmos pass transistor N4 and the N5 and Fig. 4 D's is consistent.

PMOS transistor and nmos pass transistor are arranged on the ground floor, but for the ease of manufacturing process, preferably arrange on the second layer 2F with the second layer that is arranged in memory cell on the transistor of transistor same type.For example, if the transistor of waiting to be arranged on the second layer 2F of memory cell is the PMOS transistor, then preferred arrangements waits to be arranged in the PMOS transistor on the second layer 2F of peripheral circuit, if the transistor of waiting to be arranged on the 3rd layer of 3F of memory cell is a nmos pass transistor, then preferred arrangements waits to be arranged in the nmos pass transistor on the 3rd layer of 3F of peripheral circuit.

To illustrate below according to the static storage cell of the embodiment of the invention and the layout and the structure of inverter, NAND door and the NOR door of forming peripheral circuit.

Figure 10 A to 16D is the plane graph of explanation according to the memory cell of the embodiment of the invention, inverter, NAND door, NOR door layout separately.Figure 17 A and 17B are that edge explanation respectively is according to the line I-1 ' of Figure 16 A of the structure of the memory cell of the embodiment of the invention and the profile of II-II '.Figure 18 to 20 is along the profile of explanation according to the line X-X ' of Figure 10 B to 16B, the 10C to 16C of the memory unit of the embodiment of the invention and 10D to 16D.

With reference to Figure 10 A, 17A and 17B, first has source region 1b ' and second to have source region 1a ' to be arranged on the Semiconductor substrate SUB in the parallel direction of y axle relative to one another, and second has the end of source region 1a ' to be parallel to the extension of x axle.The 3rd has source region 1b " and having ideals, morality, culture, and discipline source region 1a " being arranged on the Semiconductor substrate SUB on the parallel direction of y axle relative to one another, and having ideals, morality, culture, and discipline source region 1a " an end be parallel to the x axle and extend.Gate pattern 1c ' is arranged on the x direction of principal axis with what leap was parallel to that the y axle arranges first and second has source region 1b ' and 1a ', and gate pattern 1c " be arranged in x direction of principal axis be parallel to third and fourth of y axle layout with leap source region 1b is arranged " and 1a ".Drain region PD1D is set in place in first of the side of gate pattern 1c ' to be had on the surface of source region 1b ', and source area PD1S is set in place in second of the another side of gate pattern 1c ' to be had on the surface of source region 1a '.Similarly, drain region PD2D is set in place on the surface of gate pattern 1c " one side the 3rd source region 1b is arranged ", and source area PD2S is set in place on the surface of the gate pattern 1c having ideals, morality, culture, and discipline source region 1a of another side " ".Gate pattern 1c ' and 1c " comprise the gate electrode PD1G of the nmos pass transistor PD1 that piles up in turn respectively and cover insulating barrier 2a ' and the gate electrode PD2G of the nmos pass transistor PD2 that piles up in turn and cover insulating barrier 2a ", and between gate insulator 2b ' and 2b " respectively between separately gate pattern 1c ' and 1c " and the Semiconductor substrate SUB.Sept 2c can be arranged in gate pattern 1c ' and 1c " sidewall on, interlevel insulator 2e is arranged in the whole surface of the Semiconductor substrate SUB with nmos pass transistor PD1 and PD2.Etching stop layer 2d is additionally between interlevel insulator 2e with have between the Semiconductor substrate SUB of nmos pass transistor PD1 and PD2.Therefore, nmos pass transistor PD1 and the PD2 as body transistor is formed on the Semiconductor substrate SUB.

With reference to Figure 10 B and Figure 18, first and second have source region 20a ' and 20b ' to be arranged on the Semiconductor substrate SUB respect to one another, gate pattern 20c ' is arranged in the y direction of principal axis has source region 20a ' and 20b ' to cross over first and second, and the end of gate pattern 20c ' has on the x direction of principal axis of 20a ' position, source region first and extends.The drain region N1D of nmos pass transistor N1 is arranged on first to be had on the surface of source region 20a ', and the source area N1S of nmos pass transistor N1 is arranged on second to be had on the surface of source region 20b '.The gate pattern 20c ' of nmos pass transistor N1 can comprise the gate electrode N1G of the nmos pass transistor N1 that piles up in turn and cover insulating barrier 21a, and gate insulator 21b is between gate pattern 20c ' and Semiconductor substrate SUB.Sept 21c can be arranged on the sidewall of gate pattern 20c ', and interlevel insulator 21e is arranged in the whole surface of the Semiconductor substrate SUB with nmos pass transistor N1.Etching stop layer 21d is additionally between interlevel insulator 21e with have between the Semiconductor substrate SUB of nmos pass transistor N1.Therefore, the nmos pass transistor N1 as the body transistor of forming inverter is formed on the Semiconductor substrate SUB.

With reference to Figure 10 C and Figure 19, first to the 3rd has source region 40a ', 40b ' and 40a " is arranged on the Semiconductor substrate SUB.Gate pattern 40c ' is arranged in first and second to be had on the y direction of principal axis of source region 40a ' and 40b ' top, and the end of gate pattern 40c ' is arranged in first and has on the x direction of principal axis of 40a ' position, source region.Gate pattern 40c " is arranged in the second and the 3rd source region 40b ' and 40a is arranged " on the y direction of principal axis of top, and on the x direction of principal axis of gate pattern 40c " an end be arranged in the 3rd source region 40a is arranged " position.The end of gate pattern 40c ' and gate pattern 40c " an end on diagonal, be arranged opposite to each other.The gate pattern 40c ' of nmos pass transistor N2 can comprise the gate electrode N2G of nmos pass transistor N2 and cover insulating barrier 41a ', and gate insulator 41b ' is between gate pattern 40c ' and Semiconductor substrate SUB.The drain region N2D of nmos pass transistor N2 is arranged on first of Semiconductor substrate SUB to be had on the surface of source region 40a ', and the source area N2S of nmos pass transistor N2 and the drain region N3D of nmos pass transistor N3 are arranged on second to be had on the surface of source region 40b '.Sept 41c is arranged on the sidewall of gate pattern 40c ', and interlevel insulator 41e is arranged in the whole surface of the Semiconductor substrate SUB with nmos pass transistor N2.Etching stop layer 41d is additionally between interlevel insulator 41e with have between the Semiconductor substrate SUB of nmos pass transistor N2.The gate pattern 40c of nmos pass transistor N3 similarly, is set " with the form identical with the gate pattern 40c ' of nmos pass transistor N2.Therefore, nmos pass transistor N2 and the N3 as the body transistor of forming the NAND door is formed on the Semiconductor substrate SUB.

With reference to Figure 10 D and Figure 20, N trap NWELL is formed on the Semiconductor substrate SUB, and providing in N trap NWELL first to the 3rd has source region 60a ', 60b ' and 60a ".Gate pattern 60c ' and 60c to be set " with the identical form of Figure 10 C.As shown in figure 20, on Semiconductor substrate SUB, form PMOS transistor P4 and P5 as body transistor.PMOS transistor P4 has the form identical with N3 with the nmos pass transistor N2 of Figure 19 with P5.

With reference to Figure 11 A, 17A and 17B, the drain region PD1D of nmos pass transistor PD1 is electrically connected on the following node semiconductor plug 3a ' that penetrates interlevel insulator 2e and etching stop layer 2d, and the drain region PD2D of nmos pass transistor PD2 is electrically connected to the following node semiconductor plug 3a that penetrates interlevel insulator 2e and etching stop layer 2d " on.Following main body pattern 3b ' and 3b " are arranged on the interlevel insulator 2e, to cover node semiconductor plug 3a ' and 3a down respectively ".

With reference to Figure 11 B and Figure 18, the drain region N1D of nmos pass transistor N1 is electrically connected to the node semiconductor plug 22b that penetrates interlevel insulator 21e and etching stop layer 21d, and following main body pattern 22a is arranged in interlevel insulator 21e and goes up to cover node semiconductor plug 22b.

With reference to Figure 11 C and Figure 19, the drain region N2D of nmos pass transistor N2 is electrically connected to the node semiconductor plug 42b that penetrates interlevel insulator 41e and etching stop layer 41d, and following main body pattern 42a is arranged in interlevel insulator 41e and goes up to cover node semiconductor plug 42b.

Under the situation of arranging memory cell, inverter, NAND door shown in Figure 11 A and 11C, the NOR door of Figure 11 D has the layout as Figure 10 D.

With reference to Figure 12 A, 17A and 17B, the gate pattern 4b ' that arranges PMOS transistor PU1 arranges the gate pattern 4b " to cross over down main body pattern 3b " of PMOS transistor PU2 to cross over down main body pattern 3b '.Last node semiconductor plug 4a ' the position that cloth deposits node semiconductor plug 3a ' be arranged in main body pattern 3b ' down above, the position that semiconductor-on-insulator connector 4a " deposits node semiconductor plug 3a at cloth " is arranged in main body pattern 3b down " the top.Gate electrode PU1G and the PU2G of PMOS transistor PU1 and PU2 are arranged in down main body pattern 3b ' and 3b " the top.The source area PU1S of PMOS transistor PU1 and drain region PU1D are arranged on down among the main body pattern 3b ', and the source area PU2S of PMOS transistor PU2 and drain region PU2D are arranged on down main body pattern 3b " in.Therefore, PMOS transistor PU1 and the PU2 as thin-film transistor is stacked on nmos pass transistor PD1 and the PD2.

With reference to Figure 12 B and Figure 18, gate pattern 23a is arranged in down the top of main body pattern 22a with the form identical with gate pattern 20c '.The gate electrode P1G of PMOS transistor P1 is arranged in down the top of main body pattern 22a, and the drain region P1D of PMOS transistor P1 and source area P1S are arranged on down among the main body pattern 22a.Cover the top that insulating barrier 24a is arranged in gate electrode P1G, gate insulator 24b is arranged in the below of gate electrode P1G.Sept 24c can be arranged on the sidewall of gate pattern 23a, and interlevel insulator 24e is arranged in the top on the whole surface of the following main body pattern 22a with PMOS transistor P1.Etching stop layer 24d can be additionally between interlevel insulator 24e with have between the following main body pattern 22a of PMOS transistor P1.Therefore, PMOS transistor P1 is stacked on the top of nmos pass transistor N1.

With reference to Figure 12 C and Figure 19, gate pattern 43a ' and 43a " be arranged in down the top of main body pattern 42a, with " overlapping with gate pattern 40c ' and 40c.The gate electrode P2G of PMOS transistor P2 and P3 and P3G are arranged in down the top of main body pattern 42a, and the drain region PSD of the source area P2S of the drain region P2D of PMOS transistor P2, PMOS transistor P2, the source area P3S of PMOS transistor P3 and PMOS transistor P3 is arranged on down among the main body pattern 42a.Cover the top that insulating barrier 44a ' is arranged in gate electrode P2G, gate insulator 44b ' is arranged in the below of gate electrode P2G.Similarly, cover insulating barrier 44a " be arranged in the top of gate electrode P3G, gate insulator 44b " and be arranged in gate electrode P3G below.On the sidewall that sept 44c ' and 44c " are arranged in gate pattern 43a ' and 43a ", interlevel insulator 44e is arranged in the top on the whole surface of the following main body pattern 42a with PMOS transistor P2 and P3.Etching stop layer 44d can be additionally between interlevel insulator 44e with have between the following main body pattern 42a of PMOS transistor P2 and P3.Therefore, PMOS transistor P2 and P3 are stacked on the top of nmos pass transistor N2 and N3 respectively.

Under the situation of arranging memory cell, inverter, NAND door shown in Figure 11 A and 11C, the NOR door of Figure 12 D has the layout as Figure 11 D.

With reference to Figure 13 A, 17A and 17B, last main body pattern 6a ' and 6a " are arranged on the interlevel insulator 5e.Main body pattern 6a ' and 6a on the layout " go up node semiconductor plug 4a ' and 4a to cover respectively " and are " overlapping with following main body pattern 3b ' and 3b.Arrange that wordline patterns 6b is overlapping to cross over main body pattern 6a ' and 6a " and with gate pattern 1c ' and 1c ".During word line T1G and T2G are arranged in main body pattern 6a ' and 6a " top, the drain region T1D of transmission transistor T1 and source area T1S are arranged among the main body pattern 6a ', the drain region T2D of transmission transistor T2 and source area T2S are arranged in main body pattern 6a ".Cover the top that insulating barrier 7a is arranged in word line T1G and T2G, gate insulator 7b is arranged in word line T1G and T2G below, and sept 7c is arranged on the sidewall of wordline patterns 6b.Interlevel insulator 7e is arranged in last main body pattern 6a ' and the 6a with transmission transistor T1 and T2 " the top on whole surface.Etching stop layer 7d can and have last main body pattern 6a ' and the 6a of transmission transistor T1 and T2 between interlevel insulator 7e in addition " between.Therefore, the top that is stacked on pull up transistor PU1 and PU2 respectively as the transmission transistor T1 and the T2 of thin-film transistor.

Under the situation of arranging memory cell as shown in FIG. 13A, the inverter of Figure 13 B and 13C has the layout identical with 12C with Figure 12 B with the NAND door.

With reference to Figure 13 D and Figure 20, the drain region P5D of PMOS transistor P5 is electrically connected to the node semiconductor plug 65b that penetrates interlevel insulator 64e and 61e and etching stop layer 41d, and last main body pattern 65a arranges and covers interlevel insulator 64e and node semiconductor plug 65b.

With reference to Figure 14 A, 17A and 17B, the gate electrode PD2G of source area T1S, the pull-down transistor PD2 of drain region PU1D, the transmission transistor T1 of drain region PD1D, the PU1 that pulls up transistor of following node semiconductor plug 3a ', last node semiconductor plug 4a ', pull-down transistor PD1 and the gate electrode PU2G of the PU2 that pulls up transistor are by node connector 8a ' electrical connection.The gate electrode PD1G of source area T2S, the pull-down transistor PD1 of drain region PU2D, the transmission transistor T2 of following node semiconductor plug 3a ", go up node semiconductor plug 4a ", the drain region PD2D of pull-down transistor PD2, the PU2 that pulls up transistor and the gate electrode PU1G of the PU1 that pulls up transistor " are electrically connected by node connector 8a.

Arranging that shown in Figure 14 A the inverter of Figure 14 B and 14C has the layout identical with 13C with Figure 13 B with the NAND door under the situation of memory cell.

With reference to Figure 14 D and Figure 20, gate pattern 66a ' and 66a " top that is arranged in main body pattern 65a with gate pattern 60c ' and 60c " are overlapping.As shown in figure 20, the gate electrode N4G of nmos pass transistor N4 and N5 and N5G are arranged in the top of main body pattern 65a, and the source area N4S of the source area of the drain region N5D of nmos pass transistor N5, nmos pass transistor N4 and N5 and drain region N5S and N5D and nmos pass transistor N4 is arranged among the main body pattern 65a.Cover the top that insulating barrier 67a ' is arranged in gate electrode N5G, gate insulator 67b be arranged in gate electrode N5G below.Similarly, " be arranged in the top of gate electrode N4G, gate insulator 67b " is arranged in the below of gate electrode N4G to cover insulating barrier 67a.On the sidewall that sept 67c ' and 67c " are arranged in gate pattern 66a ' and 66a ", interlevel insulator 67e is arranged in the top on the whole surface of the last main body pattern 65a with nmos pass transistor N4 and N5.Etching stop layer 67d can be additionally between interlevel insulator 67e with have between the last main body pattern 65a of nmos pass transistor N4 and N5.Therefore, nmos pass transistor N4 and N5 are stacked on the top of PMOS transistor P4 and P5 respectively.

With reference to Figure 15 A, 17A and 17B, interlevel insulator 9c is stacked on node connector 8a ' and 8a " and on the interlevel insulator 7e.The source area PU1S of PU1 of pulling up transistor is electrically connected to power line contact plunger 9a ', and the source area PU2S of the PU2 that pulls up transistor is electrically connected to power line contact plunger 9a ".The source area PD1S of pull-down transistor PD1 is electrically connected to earth connection contact plunger 9b ', and the source area PD2S of pull-down transistor PD2 is electrically connected to earth connection contact plunger 9b ".

With reference to Figure 15 B and Figure 18, interlevel insulator 26 is stacked on the interlevel insulator 24e.The drain region P1D of the drain region N1D of node semiconductor plug 22b, nmos pass transistor N1, PMOS transistor P1 is electrically connected to output signal line contact plunger 25a, the source area P1S of PMOS transistor P1 is electrically connected to power line contact plunger 25b, and the source area N1S of nmos pass transistor N1 is electrically connected to earth connection contact plunger 25c.Even without illustrating, the gate electrode P1G of PMOS transistor P1 and nmos pass transistor N1 and N1G also are electrically connected to input signal cable contact plunger 25d.

With reference to Figure 15 C and Figure 19, interlevel insulator 46 is stacked on the interlevel insulator 44e.The drain region P2D of the drain region N2D of node contact plunger 42b, nmos pass transistor N2, PMOS transistor P2 is electrically connected to output signal line contact plunger 45a, the source area P2S of PMOS transistor P2 and P3 and P3S are electrically connected to power line contact plunger 45b, the drain region P3D of PMOS transistor P3 is electrically connected to output signal line contact plunger 45c, and the source area N3S of nmos pass transistor N3 is electrically connected to earth connection contact plunger 45d.The gate electrode P2G of PMOS transistor P2 and nmos pass transistor N2 and N2G are electrically connected to the first input signal cable contact plunger 25e, and the gate electrode P3G of PMOS transistor P3 and nmos pass transistor N3 and N3G are electrically connected to the second input signal cable contact plunger 25f.

With reference to Figure 15 D and Figure 20, interlevel insulator 69 is stacked on the interlevel insulator 67e.The drain region P5D of node contact plunger 65b, PMOS transistor P5, the drain region N5D of nmos pass transistor N5 are electrically connected to output signal line contact plunger 68a, the source area N5S of nmos pass transistor N5 and the drain region N4D of nmos pass transistor N4D are electrically connected to earth connection contact plunger 68b, the source area N4S of nmos pass transistor N4 is electrically connected to output signal line contact plunger 68c, and the source area P4S of PMOS transistor P4 is electrically connected to power line contact plunger 68d.The gate electrode P5G of PMOS transistor P5 and nmos pass transistor N5 and N5G are electrically connected to the first input signal cable contact plunger 68c, and the gate electrode P4G of PMOS transistor P4 and nmos pass transistor N4 and N4G are electrically connected to the second input signal cable contact plunger 68f.

With reference to Figure 16 A, 17A and 17B, interlevel insulator 11 is arranged on the interlevel insulator 9c.Power line contact plunger 9a ' is covered by power voltage line 10b, and earth connection contact plunger 9b ' is grounded voltage 10a and covers.Power line contact plunger 9a " 10b covers by power voltage line, earth connection contact plunger 9b " is grounded voltage 10a and covers.Interlevel insulator 12 is arranged on the interlevel insulator 11, and drain region T1D and the T2D of transmission transistor T1 and T2 are electrically connected to bit line contact plug 13a ' and 13a respectively ".Bit line contact plug 13a ' and 13a " are covered by bit line 14.

With reference to Figure 16 B and Figure 18, interlevel insulator 28 is arranged on the interlevel insulator 26, output signal line contact plunger 25a is output holding wire 27a and covers, and earth connection contact plunger 25b is grounded pressure-wire 27b and covers, and power line contact plunger 25c is covered by power voltage line 27c.Input signal cable contact plunger 25d is transfused to holding wire 27d and covers.

With reference to Figure 16 C and Figure 19, interlevel insulator 48 is arranged on the interlevel insulator 46, output signal line contact plunger 45a is output holding wire 47a and covers, power line contact plunger 45b is covered by power voltage line 47b, output signal line contact plunger 45c is output holding wire 47c and covers, and earth connection contact plunger 45d is grounded pressure-wire 47d and covers.The first input signal cable contact plunger 45e is covered by the first input signal cable 47e, and the second input signal cable contact plunger 45f is covered by the second input signal cable 47f.

With reference to Figure 16 D and Figure 20, interlevel insulator 71 is arranged on the interlevel insulator 69, output signal line contact plunger 68a is output holding wire 70a and covers, power line contact plunger 68b is grounded pressure-wire 70b and covers, output signal line contact plunger 68c is output holding wire 70a and covers, and power line contact plunger 68d is covered by power voltage line 70.The first input signal cable contact plunger 68e is covered by the first input signal cable 70e, and the second input signal cable contact plunger 68f is covered by the second input signal cable 70f.

Node contact plunger and upper and lower main body pattern can be monocrystalline substrate.Upper and lower main body pattern can be the polysilicon substrate, under these circumstances, does not have the node contact plunger.

Under such situation, it is aforesaid memory cell, body transistor is arranged on the ground floor of memory cell and thin-film transistor is arranged on second and the 3rd layer, for the ease of make handling, preferably wait to be arranged in peripheral circuit second with the 3rd layer on thin-film transistor have be arranged in second and the 3rd layer of memory cell on the identical type of thin-film transistor.

Figure 21 A and 21B are the figure of explanation according to the stacked structure of the memory cell array of first embodiment of the invention and peripheral circuit.Be arranged at body nmos pass transistor, film PMOS transistor, film nmos pass transistor under the situation on first to the 3rd layer of memory cell array shown in Figure 21 A, the transistor preferred arrangements of type with Figure 21 B is on first to the 3rd layer of peripheral circuit.Promptly preferably, body nmos pass transistor or body PMOS transistor can be arranged on the ground floor, have with film PMOS transistor that is arranged in the thin-film transistor same type on second and the 3rd layer of memory cell and film nmos pass transistor to be arranged on second and the 3rd layer of peripheral circuit.

Figure 22 A and 22B are the figure of explanation according to the stacked structure of the memory cell array of second embodiment of the invention and peripheral circuit.Be arranged at body nmos pass transistor, film PMOS transistor, film nmos pass transistor under the situation on first to the 3rd layer of memory cell array shown in Figure 22 A, the transistor preferred arrangements of type with Figure 22 B is on first to the 3rd layer of peripheral circuit.Promptly preferably, body nmos pass transistor or body PMOS transistor can be arranged on the ground floor, have with the film nmos pass transistor that is arranged in the thin-film transistor same type on second and the 3rd layer of memory cell and film PMOS transistor layout on second and the 3rd layer of peripheral circuit.

Figure 23 A and 23B are the figure of explanation according to the stacked structure of the memory cell array of third embodiment of the invention and peripheral circuit.Be arranged at body PMOS transistor, film nmos pass transistor, film nmos pass transistor under the situation on first to the 3rd layer of memory cell array shown in Figure 23 A, the transistor preferred arrangements of type with Figure 23 B is on first to the 3rd layer of peripheral circuit.Promptly preferably, body nmos pass transistor or body PMOS transistor layout under the situation on the ground floor, have with the film nmos pass transistor that is arranged in the thin-film transistor same type on second and the 3rd layer of memory cell and film PMOS transistor layout on second and the 3rd layer of peripheral circuit.

Certainly, wait to be arranged in transistor on second and the 3rd layer of peripheral circuit and can have the transistorized type that is different from second and the 3rd layer that waits to be arranged in memory cell array.But this makes complicate fabrication process.

Can reduce the layout area size of peripheral circuit and the layout area size of memory cell.

In the above-described embodiments, having described the transistor that will form inverter, NAND door and NOR door piles up.But, also can pile up and form for example transistor of AND door and OR door of different logical circuits.

Arrange peripheral circuit of the present invention, make only to pile up and form for example transistor of row or column decoder of some functional blocks, but not pile up all functions piece, perhaps only pile up and be expert at and/or the lead-out terminal place of column decoder forms the transistor of driver (being made up of inverter usually).

The above-mentioned method of declining of forming inverter, NAND door and the NOR door of peripheral circuit can usefully be applied on the different semiconductor device.

If pile up transistor that forms peripheral circuit and the transistor that forms memory cell array with above-mentioned mode, then can reduce the layout area size of peripheral circuit, thereby can increase the influence of the layout area size of semiconductor memory.

Yet different with the foregoing description, even the transistor of stacked memory cells array, the transistor that forms peripheral circuit also can be arranged on the individual layer.In this case, even be difficult to reduce the layout area size in the zone of arranging peripheral circuit, also can arrange high performance transistor.

Figure 24 A and 24B illustrate according to the transistor of the static storage cell of fourth embodiment of the invention respectively and form the view of transistorized layout of inverter of the peripheral circuit of semiconductor memory.Arrange static storage cell with the identical method of Fig. 8 A, arrange that inverter makes similar arrangement among PMOS transistor P1 and nmos pass transistor N1 and Fig. 5 B on identical layer, but be arranged in the 3rd layer of 3F but not on the 1F.Here, first and second layers are served as pseudo-layer, and formed thereon without any transistor.

The transistorized formation method of peripheral circuit is described below by the structure of the inverter of the peripheral circuit of describing semiconductor memory of the present invention and its manufacture method.

Figure 25 is the plane graph of inverter of the peripheral circuit of key diagram 24B, and Figure 26 A and 26B to Figure 34 A and 34B are the profiles of the manufacture method of explanation memory cell and inverter.In Figure 26 A and 26B to Figure 34 A and 34B, label " C " and " P " represent memory cell array region territory and peripheral circuit region respectively.The cross section face figure of Figure 26 A to 34A is along line III-III ' acquisitions of the line I-I ' of Figure 10 A to Figure 16 A and Figure 25, and the sectional view of Figure 26 B to 34B is along the line IV-IV ' acquisition of the line II-II ' of Figure 16 A and Figure 25.

Semiconductor memory substrate 100 comprises cellular zone C and peripheral circuit region P.Structure and the layout of cellular zone C be can easily understand with reference to above-mentioned explanation, thereby structure and the layout of peripheral circuit region P the following describes.

With reference to Figure 25 and Figure 26 A and 26B, when interlevel insulator 2e was arranged in the top of cellular zone C, interlevel insulator 2e was arranged in the top corresponding to a part of Semiconductor substrate SUB of peripheral circuit region P.When etching stop layer 2d was arranged in the top of cellular zone C, etching stop layer 2d was arranged in the top of peripheral circuit region P.Etching stop layer 2d preferably has the etching selection to interlevel insulator 2e.For example, under the situation that interlevel insulator 2e is formed by silicon oxide layer, etching stop layer 2d can be formed by silicon nitride layer or silicon oxynitride layer.

With reference to Figure 25 and Figure 27 A and 27B, instantly main body pattern 3b ' and 3b " when being arranged in the top of cellular zone C; remove the etching stop layer 2d and the interlevel insulator 2e of the top that is arranged in peripheral circuit region P, are arranging above the peripheral circuit region P that main body pattern 3p is to cover Semiconductor substrate SUB under the periphery.In this case, etching stop layer 2d and the interlevel insulator 2e that is retained among the cellular zone C is used as etching stopping layer pattern and interlevel insulator pattern respectively.Arrange peripheral main body pattern 3p down, make its surface be positioned at at following main body pattern 3b ' and 3b above the cellular zone C " surperficial identical imaginary horizontal line on.Peripheral main body pattern 3p down has single crystalline semiconductor structure.For example, have at Semiconductor substrate SUB under the situation of monocrystal silicon structure, peripheral main body pattern 3p down has monocrystal silicon structure.

With reference to Figure 25 and Figure 28 A and 28B, when the etching stopping 5d that covers the first and second load transistor TL1 and TL2 and interlevel insulator 5e were arranged in the top of cellular zone C, etching stopping 5d and interlevel insulator 5e were arranged in the top of peripheral circuit region P.Etching stop layer 5d preferably has the etching selection to interlevel insulator 5e.For example, under the situation that interlevel insulator 5e is formed by silicon oxide layer, etching stop layer 5d can be formed by silicon nitride layer or silicon oxynitride layer.

With reference to Figure 25 and Figure 29 A and 29B, " be arranged in the top of cellular zone C; remove the etching stop layer 5d and the interlevel insulator 5e of the top that is arranged in peripheral circuit region P, what cover peripheral main body pattern 3p down places the top that main body pattern 6p is arranged in peripheral circuit region P outward for last main body pattern 6a ' and 6a.Arrange and to place main body pattern 6p outward, make its surface be positioned at and main body pattern 6b ' and 6b on above the cellular zone C " surperficial identical imaginary horizontal line on.Place the single crystalline semiconductor structure that main body pattern 6p has the crystal structure identical with pattern 3p under the periphery outward.For example, main body pattern 3p has under the situation of monocrystal silicon structure under the periphery, places main body pattern 6p outward and has single crystalline semiconductor structure, as monocrystal silicon structure.Peripheral upper and lower

main body pattern

6p, 3p form peripheral main body pattern 6p '.

Peripheral upper and lower

main body pattern

6p, 3p have single crystalline semiconductor structure, as the monocrystal silicon structure that is formed by single processing.Element separation insulator 7e ' is arranged in outer the placing on the main body pattern 6p of peripheral circuit region P top.

With reference to Figure 25 and Figure 30 A and 30B, when the wordline patterns 6b of nmos pass transistor T1 and T2 is arranged in the top of cellular zone C, arrange that there is the gate pattern 23a ' of the PMOS transistor P1 of source region 1p first periphery of crossing peripheral circuit region P.The gate pattern 23a ' of PMOS transistor P1 can comprise the polysilicon layer pattern P1G and the PMOS grid metal silicide layer 24a ' of sequence stack.Layout has the gate pattern 20c of the nmos pass transistor N1 of source region 1p ' across second periphery ".The gate pattern 20c of nmos pass transistor N1 " the polysilicon layer pattern N1G and the NMOS grid metal silicide layer 21a ' that comprise sequence stack.Grid metal silicide layer 21a ' and 24a ' can be formed by nickel silicide layer, silicon cobalt substrate, titanium silicide layer or tungsten silicide layer.The nmos pass transistor T1 and the T2 of cellular zone C top also comprise metal silicide layer 7d '.Have on the surface of source region 1p in first periphery on the both sides that are positioned at PMOS gate pattern 23a ', arrange drain region P1D and the source area P1S of PMOS transistor P1.PMOS gate pattern 23a ' forms PMOS transistor P1 with source area P1S and drain region P1D.Similarly, be positioned at NMOS gate pattern 20c " both sides on second periphery have on the surface of source region 1p ', arrange drain region N1D and the source area N1S of nmos pass transistor NP1.NMOS gate pattern 20c " forms nmos pass transistor N1 with source area N1S and drain region N1D.On the surface of the surface of the source area P1S of PMOS transistor P1 and drain region P1D and nmos pass transistor N1 source area N1S and drain region N1D, arrange metal silicide layer 7d ' respectively.Metal silicide layer 7d ' is formed by nickel silicide layer, silicon cobalt substrate, titanium silicide layer or tungsten silicide layer.Interlevel insulator 7e is arranged on the whole surface of the Semiconductor substrate with nmos pass transistor N1 and PMOS transistor P1.In addition, etching stop layer 7d can be between Semiconductor substrate SUB and interlevel insulator 7e.Etching stop layer 7d preferably has the etching selection to interlevel insulator 7e.For example, under the situation that interlevel insulator 7e is formed by silicon oxide layer, etching stop layer 7d can be formed by silicon nitride layer or silicon oxynitride layer.

With reference to Figure 25 and Figure 31 A and 31B, interlevel insulator 9c is arranged on the interlevel insulator 7e of peripheral circuit region P top as cellular zone C.

With reference to Figure 25 and Figure 32 A and 32B, peripheral power supply line contact plunger 9e, peripheral earth connection contact plunger 9f ' and output signal

line contact plunger

9f and 9e ' are arranged among the interlevel insulator 9c of peripheral circuit region P top.

Arrange the interlevel insulator 11 that covers peripheral power supply line contact plunger 9e, peripheral earth connection contact plunger 9f ' and output signal

line contact plunger

9f and 9e '.

With reference to Figure 25 and Figure 33 A and 33B, in the interlevel insulator 11 above peripheral circuit region P, arrange that peripheral power supply line 10e is to cover peripheral power supply line contact plunger 9e, arrange peripheral earth connection 10f to cover peripheral earth connection contact plunger 9f ', arrange that output signal line 10g is to cover output signal

line contact plunger

9f and 9e '.

Arrange that interlevel insulator 12 is to cover peripheral power supply line 10e, peripheral earth connection 10f and output signal line 10g.

In said method, form the transistor P1 of inverter and N1 and be arranged on the 3rd layer of peripheral circuit region P.Certainly, the transistor that forms NAND door and NOR door also can be arranged on the 3rd layer of peripheral circuit region P.

Below with reference to Figure 16, Figure 25 and Figure 26 A and 26B to 34A and 34B explanation manufacture method according to SRAM of the present invention.

With reference to Figure 16 A, Figure 25 and Figure 26 A and 26B, prepare to have the Semiconductor substrate SUB of cellular zone C and peripheral circuit region P.Semiconductor substrate SUB is a monocrystalline substrate.Semiconductor substrate SUB is a p type silicon substrate.Element isolation layer 1 ' be formed on the fate of Semiconductor substrate SUB has source region 1b ' and 1b to limit Unit first and second " on.Element isolation layer 1 ' preferably be formed among the cellular zone C.First and second have source region 1b ' and 1b, and " being parallel to the y axle forms.In addition, form element isolation layer 1 ' source region 1a ' is arranged along the x axle from first first ground connection that has the end of source region 1b ' to extend and from second source region 1b " an end extend having ideals, morality, culture, and discipline source region 1a " is arranged along the x axle to provide.Form relative to one another second and having ideals, morality, culture, and discipline source region 1a ' and 1a ".

Gate insulator 2b ' and 2b " are formed on first to fourth source region 1a ', 1b ', 1a are arranged " and 1b " on.Grid conducting layer and cover insulating barrier and sequentially be formed on and have gate insulator 2b ' and 2b " the whole surface of Semiconductor substrate SUB on.Grid conductive layer is formed by silicon layer, covers insulating barrier and is formed by silicon oxide layer or silicon nitride layer.Patterned gate covers insulating barrier and grid conductive layer, and crossing first with formation has the gate pattern 1c ' of source region 1b ' and cross the 3rd source region 1b " gate pattern 1c " is arranged.As a result, gate electrode PD1G and the covering separator 2a ' of formation gate pattern 1c ' to have sequence stack forms gate pattern 1c " with gate electrode PD2G and the covering insulating barrier 2a with sequence stack ".Can omit and form the technology that covers insulating barrier.In this case, gate pattern 1c ' only has gate electrode, and gate pattern 1c " only has gate electrode.

" as the ion doping mask, foreign ion is doped to first to fourth to be had among source region 1a ', 1b ', the 1b " and 1a " by using gate pattern 1c ' and 1c.As a result, source area PD1S that separates each other and drain region PD1D are formed on first to be had among the 1b ' of source region, and source area PD2S that separates each other and drain region PD2D are formed on the 3rd source region 1b " in.Source area PD1S and PD2S and drain region PD1D and PD2D can be n type ion doped regions.Source area PD1S and drain region PD1D are formed on the both sides of the following channel region of driving grid pattern 1c ', and source area PD2S and drain region PD2D are formed on driving grid pattern 1c " on the both sides of following channel region.Source area PD2S also is formed on second to be had among the 1a ' of source region, and source area PD2S also is formed on having ideals, morality, culture, and discipline source region 1a " on.Can form source area PD1S and PD2S and drain region PD1D and PD2D to have lightly doped drain (LDD) type structure.Grid spacer 2c is formed on gate pattern 1c ' and 1c " sidewall on.Grid spacer 2c can be formed by silicon nitride layer or silicon oxide layer.

The first driving grid pattern 1c ', source area PD1S and drain region PD1D form first body transistor, the i.e. first nmos pass transistor PD1, the second driving grid pattern 1c ", source area PD2S and drain region PD2D form second body transistor, i.e. the second nmos pass transistor PD2.

Etching stop layer 2d and interlevel insulator 2e sequentially are formed on the whole surface of the Semiconductor substrate SUB with the first and second transistor PD1 and PD2.Preferably by using chemical Mechanical Polishing Technique planarization interlevel insulator 2e.In this case, gate pattern 1c ' and 1c " on etching stop layer 2d serve as chemico-mechanical polishing and stop layer.

With reference to Figure 16 A, Figure 25 and Figure 27 A and 27B, patterning interlevel insulator 2e and etching stop layer 2d are with the fate of the drain region PD1D of exposure unit district C and PD2D and expose the Semiconductor substrate of peripheral circuit region P.As a result, insulator layer 2e and etching stop layer 2d " are formed among the cellular zone C with the following node contact hole 2f ' and the 2f of the fate of the drain region PD1D of exposure unit district C and PD2D between the order penetrated bed.In this case, interlevel insulator layer 2e and etching stop layer 2d are taken as interlevel insulator layer pattern and etching stopping layer pattern respectively.Form semiconductor layer 3p to cover the Semiconductor substrate SUB of interlevel insulator 2e and peripheral circuit region P, fill node contact hole 2f ' and 2f down simultaneously ".Semiconductor layer 3p is formed by single crystalline semiconductor structure.Form single crystalline semiconductor structure by epitaxy technology.In more detail, single crystalline semiconductor structure promptly, form to cover the Semiconductor substrate SUB of interlevel insulator 2e and peripheral circuit region P top and fills node contact hole 2f ' and 2f down simultaneously " epitaxial loayer.Epitaxy technology is the selective epitaxial growth technology.Form epitaxial loayer by the selective epitaxial growth technology, the selective epitaxial growth technology is used by lower node contact hole 2f ' and 2f, and " and the Semiconductor substrate SUB of the fate of the Semiconductor substrate SUB of peripheral circuit region P exposure is as inculating crystal layer.At Semiconductor substrate SUB is under the situation of monocrystalline substrate, epitaxial loayer is formed have monocrystal silicon structure.That is to say that epitaxial loayer can be formed by single crystalline semiconductor structure.Then, can come the upper surface of planarization epitaxial loayer by using for example chemico-mechanical polishing of planarization (CMP) technology.

Simultaneously, " and the semiconductor layer of the Semiconductor substrate SUB of covering interlevel insulator 2e and peripheral circuit region P can be formed by non-single crystal semiconductor layer to fill node contact hole 2f ' and 2f down.For example, semiconductor layer is formed by amorphous silicon layer or polysilicon layer.Can the planarization semiconductor layer.In this case, before or after the planarization semiconductor layer, can use epitaxy technology, the Semiconductor substrate that is about to the contact semiconductor layer is come crystalline semiconductor layer as the solid phase epitaxy technology of inculating crystal layer.As a result, can form semiconductor layer as single crystalline semiconductor structure.

The patterning single crystalline semiconductor structure is with main body patterning 3b ' and 3b under forming above the cellular zone ", main body pattern 3p under the periphery of the Semiconductor substrate SUB of the peripheral circuit region of formation covering simultaneously P.Be preferably formed down main body pattern 3b ' and 3b " the overlapping first and the 3rd source region 1b ' and 1b to be arranged respectively ".Form main body pattern 3b ' and 3b " to cover node contact hole 2f ' and 2f down respectively " down.

Preferably, following main body pattern 3b ' has overlapping second extension that the part of source region 1a ' arranged.Similarly, under the unit main body pattern 3b " preferably have overlapping having ideals, morality, culture, and discipline source region 1a " part the extension.

Simultaneously, form single-crystal semiconductor layer to fill down node contact hole 2f ' and 2f and " and cover the Semiconductor substrate SUB of interlevel insulator 2e and peripheral circuit region P.Single crystal semiconductor is carried out chemical mechanical polish process, with down node contact hole 2f ' and 2f " in form under node contact plunger 3a ' and 3a ", and the peripheral single-crystal semiconductor layer of the Semiconductor substrate SUB of formation covering peripheral circuit region P.Can form single-crystal semiconductor layer by epitaxy technology.Subsequently, semiconductor layer promptly descends body layer to be formed on to have following node contact plunger 3a ' and 3a " the whole surface of Semiconductor substrate SUB on." be under the situation of monocrystalline silicon connector, following body layer can be by non-single crystal semiconductor layer, and promptly amorphous silicon layer or polysilicon layer form at following node semiconductor plug 3a ' and 3a.Can use body layer under the crystallization of the known solid phase epitaxy of those of ordinary skill in the art (SPE) technology.For example, the solid phase epitaxy technology can be included in about 500 ℃ of main body pattern 3b ' and 3b under heat treatment and the crystallization to about 800 ℃ temperature " technology.

Simultaneously, the patterning single crystalline semiconductor structure is to form down main body pattern 3b ' and 3b ", the single crystalline semiconductor structure of removing peripheral circuit region P simultaneously is to expose the Semiconductor substrate SUB of peripheral circuit region P.

With reference to Figure 16 A, Figure 25 and Figure 28 A and 28B, gate insulator is formed on down main body pattern 3b ' and 3b " the surface on.Form load gate pattern 4b ' and 4b " to cross over down main body pattern 3b ' and 3b ".Be preferably formed gate pattern 4b ' and 4b " with overlapping gate pattern 1c ' of difference and 1c ".With with driving grid pattern 1c ' and 1c " identical method forms gate pattern 4b ' and 4b ".Thereby, gate pattern 4b ' formation is had the gate electrode PU1G of sequence stack and covers insulating barrier 5a ', with gate pattern 4b and " form gate electrode PU2G and cover insulating barrier 5a with sequence stack.

During use gate pattern 4b ' and 4b " as the ion doping mask, are doped to down main body pattern 3b ' and 3b with foreign ion ".As a result, source area PU1S that separates each other and drain region PU1D are formed on down among the main body pattern 3b ', and source area PU2S that separates each other and drain region PU2D are formed on down main body pattern 3b " in.Source area PU1S and drain region PU1D are formed on the both sides of the following channel region of gate pattern 4b ', and source area PU2S and drain region PU2D are formed on gate pattern 4b " on the both sides of following channel region.Source area PU1S and PU2S are respectively formed at down in the extension of main body pattern 3b ' and following main body pattern 3b " the extension in.Source area PU1S is formed on down among the following main body pattern 3b ' of node contact plunger 3a ' top, and drain region PU2D is formed on down among the node semiconductor plug 3a " the following main body pattern 3b of top ".Here, drain region PU1D can contact down node semiconductor plug 3a ', and drain region PU2D can contact down node semiconductor plug 3a ".

Source area PU1S and PU2S and drain region PU1D and PU2D can be p type ion doped regions.

Source area PU1S and PU2S and drain region PU1D and PU2D can be formed have LDD type structure.

Sept 5c can be formed on load gate pattern 4b ' and 4b " sidewall on.Sept 5c can be formed by silicon nitride layer or silicon oxide layer.

Gate pattern 4b ', source area PU1S and drain region PU1D form down thin-film transistor, i.e. PMOS transistor PU1; Gate pattern 4b ", source area PU2S and drain region PU2D form down thin-film transistor, i.e. PMOS transistor PU2.PMOS transistor PU1 and PU2 can be load transistors.Interlevel insulator 5e is formed on the whole surface of the Semiconductor substrate with load transistor PU1 and PU2.Before forming interlevel insulator 5e, can form etching stop layer 5d in addition.Form etching stop layer 5d and interlevel insulator 5e with the method identical with interlevel insulator 3e with etching stop layer 3d.In this case, interlevel insulator 5e and etching stop layer 5d are used as interlevel insulator pattern and etching stopping layer pattern respectively.

With reference to Figure 16 A, Figure 25 and Figure 29 A and 29B, patterning etching stop layer 5d and interlevel insulator 5e are with main body pattern 3p under the periphery of source of exposure polar region PU1S and drain region PU2D and exposure peripheral circuit region P.As a result, sequentially penetrating interlevel insulator 5e and etching stop layer 5d " is formed among the cellular zone C with last node contact hole 4f ' and the 4f of source of exposure polar region PU1S and drain region PU2D.Form semiconductor layer on interlevel insulator 5e and peripheral circuit region P, to fill node contact hole 4f ' and 4f ".Semiconductor layer can be formed by single crystalline semiconductor structure.Can form single crystalline semiconductor structure by epitaxy technology.Growth technology can be the selective epitaxial technology.In more detail, form single crystalline semiconductor structure, promptly cover interlevel insulator 5e and descend main body pattern 3p on every side and filling on node contact hole 4f ' and 4f " epitaxial loayer.Can form epitaxial loayer to have monocrystal silicon structure.By using by the selective epitaxial growth method formation epitaxial loayer of the presumptive area of last node contact hole 4f ' and 4f " and under the unit that exposes of peripheral main body pattern 3p main body pattern 3b ' and 3b " as inculating crystal layer.

As described in Figure 27 A and 27B, at the patterning single crystalline semiconductor structure to form main body pattern 3b ' and 3b under the unit " under the situation of the single crystalline semiconductor structure of removing peripheral circuit region P simultaneously with the Semiconductor substrate SUB that exposes peripheral circuit region P, by using by the selective epitaxial growth method formation epitaxial loayer of the presumptive area of last node contact hole 4f ' and 4f " and under the unit of the Semiconductor substrate SUB of peripheral circuit region P exposure main body pattern 3b ' and 3b " as inculating crystal layer.Then, come the upper surface of planarization epitaxial loayer by the use planarization of for example chemico-mechanical polishing (CMP) technology.

Simultaneously, node contact hole 4f ' and 4f in the filling " semiconductor layer form by the non-single crystal semiconductor layer on interlevel insulator 5e and peripheral circuit region P.For example, semiconductor layer is formed by amorphous silicon layer or polysilicon layer.Can the planarization semiconductor layer.In this case, before or after the planarization semiconductor layer, can use epitaxy technology, i.e. use is arranged in below the semiconductor layer and the single crystalline semiconductor structure of contact semiconductor layer comes crystalline semiconductor layer as the solid phase epitaxy method of inculating crystal layer.As a result, can form semiconductor layer as single crystalline semiconductor structure.

The single semiconductor structure of patterning " and is placed main body pattern 6p outside forming to form main body pattern 6a ' and 6a above the C of unit area on peripheral circuit region P.Here, form the outer main body pattern 6p that places and limit the peripheral groove 6b that there are

source area

1p and 1p ' in first and second peripheries to have.As a result, the outer main body pattern 6p that places that has a peripheral groove 6b is formed under the periphery of peripheral circuit region P on the main body pattern 3p.Peripheral upper and lower

main body pattern

3p, 6p have essentially identical mono-crystalline structures and can form peripheral main body pattern 6p '.

Simultaneously, carrying out under the situation of the previous single crystalline semiconductor structure that forms of patterning with the technology of the Semiconductor substrate SUB of exposure peripheral circuit region P, the single crystalline semiconductor structure that order forms can be formed the Semiconductor substrate SUB that directly contacts peripheral circuit region P.As a result, peripheral main body patterning 6p ' can be that monocrystal silicon structure forms by the single crystalline semiconductor structure that forms by single technology.Main body pattern 6a ' and 6a in the formation " go up node contact hole 4f ' and 4f ' to cover respectively.To be formed on node contact hole 4f ' and 4f " in epitaxial loayer be defined as node semiconductor plug 4a ' and 4a ".Be preferably formed main body pattern 6a ' and 6a " with difference overlapping main body pattern 3b ' and 3b down ".Yet, the extension of preferably going up main body pattern 6a ' and 6a " not overlapping main body pattern 3b ' and 3b down ".

Simultaneously, node contact hole 4f ' and 4f in the filling " single-crystal semiconductor layer can be formed on the Semiconductor substrate SUB of interlevel insulator 5e and peripheral circuit region P.Subsequently, this single-crystal semiconductor layer of planarization is to form node contact plunger 4a ' and 4a on first and second " and forms the single-crystal semiconductor layer that is retained in peripheral circuit region P top.Single-crystal semiconductor layer can be the monocrystal silicon structure that forms by epitaxy technology.Then, semiconductor layer is promptly gone up body layer and is formed on and has last node semiconductor plug 4a ' and 4a " the whole surface of Semiconductor substrate SUB on." be under the situation of monocrystalline silicon connector, last body layer can be formed by amorphous layer or polysilicon layer at last node semiconductor plug 4a ' and 4a.Body layer is to form first and second main body pattern 6a ' and the 6a on the patterning ", the last body layer of patterning peripheral circuit region P top limits the peripheral groove 6b that there are

source region

1p and 1p ' in first and second peripheries to form.By solid phase epitaxy technology well known to those of ordinary skill in the art with main body pattern 6a ' and 6a " crystallization on first and second.Element separation insulating barrier 7e ' can be formed among the peripheral groove 6b.Here, when element separation insulating barrier 7e ' is formed among the peripheral groove 6b, can form the last main body pattern 6a ' and the 6a of filler cells district C top " between the element separation insulating barrier 7e ' at interval.

Simultaneously, can omit the technology that is used for forming the element separation insulating barrier at peripheral groove 6b.

With reference to Figure 16 A, Figure 25 and Figure 30 A and 30B, gate insulator is formed on main body pattern 6a ' and 6a on the unit " and on the peripheral main body pattern 6p.Forming transmission gate pattern 6b promptly is insulated to cross over main body pattern 6a ' and 6a " word line, and formation is insulated peripheral PMOS gate pattern 23a ' and the peripheral NMOS gate pattern 20c that source

region

1p and 1p ' are arranged with first and second peripheries of crossing over peripheral main body pattern P ".

Simultaneously, " foreign ion can be doped to before, first and second peripheries has among source region 1p and the 1p ' to form n type trap 7f and p type trap 7f ' to form peripheral gates pattern 23a ' and 20c.Form peripheral main body pattern 6p ' with situation with n type or p type conductivity under, can omit the independent ion doping that is used to form n type or p type trap and handle.

Use word line 6p as the ion doping mask, foreign ion be doped to main body pattern 6a ' and 6a " in.In addition, use peripheral gates pattern 23a ' and the 20c of peripheral circuit region P " and element separation insulating barrier 7e is as the ion doping mask, foreign ion is doped to first and second peripheries to be had among source region 1p and the 1p '.The result, source area T1S that separates each other and drain region T1D are formed among the main body pattern 6a ', source area T2S that separates each other and drain region T2D are formed on main body pattern 6a " in; source area P1S that separates each other and drain region P1D are formed on the periphery to be had among the 1p of source region, and source area N1S that separates each other and drain region N1D are formed on the periphery to be had among the 1p ' of source region.Have under the situation of LDD type structure at source area and drain region T1S and T1D, T2S and T2D, P1S and P1D, N1S and N1D, at sidewall and peripheral gates pattern 23a ' and the 20c of word line 6b " sidewall on form insulation spacer 7c.

The source area T1S of cellular zone C and T2S and drain region T1D and T2D are n type ion doped regions.It can be p type ion doped region that there are the source area P1S of source region 1p and drain region P1D in the periphery, and it can be n type ion doped region that there are the source area N1S of source region 1p ' and drain region N1D in the periphery.Word line 6b and source area T1S and drain region T1D component units upper film transistor, i.e. NMOS transmission transistor T1, word line 6b and source area T2S and drain region T2D component units upper film transistor, i.e. NMOS transmission transistor T2.Peripheral PMOS gate pattern 23a " forms peripheral PMOS transistor P1, peripheral NMOS gate pattern 20c with source area P1S and drain region P1D and " forms peripheral nmos pass transistor N1 with source area N1S and drain region N1D.

Metal silicide layer can optionally be formed on the source area and drain region of the surface of gate electrode and/or periphery transistor P1 and N1.For example, salicide processes is used to reduce NMOS transmission transistor T1, NMOS transmission transistor T2, the gate electrode of peripheral PMOS transistor P1, peripheral NMOS transmission transistor N1 and the resistance of source area and drain region.Silicidation is to form the treatment technology of metal silicide layer with the resistance that reduces this gate electrode and source area and drain region selectively on gate electrode and source area and drain region.Silicidation comprises the silicidation anneal processing.Handle as silicidation anneal, can be or use for example radiation method of the light source of electric light, perhaps use the rapid thermal treatment of the transmission method of heating plate, perhaps use the annealing in process of the convective methods of heat-conducting gas.

" and peripheral main body pattern 6p goes up and forms after the gate insulator, forms for example polysilicon layer of silicon layer on the substrate of gate insulator having in more detail, main body pattern 6a ' and 6a on the unit.This polysilicon layer of patterning is to form the polysilicon layer pattern of crossing over main body pattern 6a ' on the unit and to form polysilicon layer pattern P1G and the N1G that there are source region 1p and 1p ' in the periphery of crossing over peripheral main body pattern 6p.On the sidewall of polysilicon layer pattern T1G, T2G, P1G and N1G, form insulation spacer 7c.Isolation spacer 7c can comprise silicon oxide layer or silicon nitride layer.Subsequently, form source area and drain region T1S and T1D, T2S and T2D, P1S and P1D, N1S and N1D.Can expose polysilicon layer pattern T1G, T2G, P1G and N1G and source area and drain region T1S and T1D, T2S and T2D, P1S and P1D, N1S and N1D.Subsequently, on Semiconductor substrate, form metal level with polysilicon layer pattern T1G, T2G, P1G and N1G and source area and drain region T1S and T1D, T2S and T2D, P1S and P1D, N1S and N1D.Metal level can be formed by nickel dam, tungsten layer, titanium layer or cobalt layer.Then, metal level being carried out silicidation anneal handles.

On the other hand, " and peripheral main body pattern 6p go up to form after the gate insulator; can form the grid conductive layer that comprises metal silicide layer having on the Semiconductor substrate of gate insulator, for example the polysilicon layer of sequence stack and metal silicide layer for main body pattern 6a ' and 6a on the unit.Then, on grid conducting layer, form hard mask insulating barrier.Patterning this hard mask insulating barrier and grid conducting layer are to form polysilicon layer pattern, metal silicide layer pattern and the hard mask pattern of sequence stack.As a result, the polysilicon layer pattern, metal silicide layer pattern and the hard mask pattern that form sequence stack be as gate pattern, and expose source area and drain region.Form metal level having on the Semiconductor substrate of gate pattern, then it is handled through silicidation anneal.As a result, in source area and drain region, form metal silicide layer.

Use silicidation, can be at word line 6p, peripheral PMOS gate pattern 23a ' and peripheral NMOS gate pattern 20c " on form gate metal silicide layer 7a respectively; PMOS gate metal silicide layer 24a ' and NMOS gate metal silicide layer 21a '; can be at source area and drain region T1S and the T1D of word line 6b; form metal silicide layer on the surface separately of T2S and T2D; can on the surface separately of the source area P1S of peripheral PMOS gate pattern 24a ' and drain region P1D, form metal silicide layer 7d ', can be at peripheral NMOS gate pattern 20c " source area N1S and the surface separately of drain region N1D on form metal silicide layer 7d '.As a result, can form polysilicon layer pattern T1G and T2G and the gate metal silicide layer 7a of word line 6p to have sequence stack.Can form polysilicon layer pattern P1G and the PMOS grid metal silicide layer 24a ' of peripheral PMOS gate pattern 23a ' to have sequence stack.Can form peripheral NMOS gate pattern 20c " to have polysilicon layer pattern N1G and the NMOS gate metal silicide layer 24a ' that sequentially piles up.Therefore, can reduce the gate electrode of periphery transistor P1 and N1 and the resistance of source area and drain region.That is to say, can improve the transfer rate of the signal of telecommunication of the gate electrode that is applied to periphery transistor P1 and N1.In addition, owing to can improve the source area of periphery transistor P1 and N1 and the sheet resistance of drain region, so can improve the operability of periphery transistor P1 and N1.As a result, can in peripheral circuit region P, realize high performance MOS transistor.In addition, because can improve transmission transistor T1 and the gate electrode of T2 and the electrical characteristics of source area and drain region of cellular zone C, so can improve the performance of transmission transistor T1 and T2.

Thereby, because can carry out the silicidation of the transistorized performance that is used to improve peripheral circuit region P, so can improve the performance of SRAM.In addition, in using the semiconductor integrated circuit of thin-film transistor,, after forming peripheral main body pattern, form the MOS transistor of peripheral circuit region, so can obtain to have the high-performance MOS transistor of the electrical characteristics of improvement because as mentioned above.The performance of SRAM depends on the peripheral circuit that is formed in the peripheral circuit region, thereby the performance of SRAM is determined by the transistorized performance as the essential part of peripheral circuit.In an embodiment of the present invention, because form peripheral main body pattern 6p as inculating crystal layer, so peripheral main body pattern 6p more approaches Semiconductor substrate on crystallinity by the Semiconductor substrate of using peripheral circuit region.That is to say, because epitaxial loayer is by the whole surface composition of the Semiconductor substrate of peripheral circuit region, so the mono-crystalline structures of peripheral main body pattern more approaches the mono-crystalline structures of Semiconductor substrate.The periphery transistor that is formed on peripheral circuit region P has and the similar characteristic of body transistor that is formed on basically on the Semiconductor substrate.And, be formed on the influence that periphery transistor among the peripheral circuit region P is not formed the heat that is produced during the processing of thin-film transistor of cellular zone C.That is to say, can under typical high temperature, carry out the epitaxy technique and the sept of the thin-film transistor of the district C of manufacturing cell and handle.Be exposed to the characteristics of transistor meeting deterioration of the processing of at high temperature carrying out, but the transistor of peripheral circuit region P is not subjected to the influence of high-temperature process.And, because metal silicide layer is respectively formed on the transistorized gate electrode and source area and drain region of peripheral circuit region P, so can further improve the transistorized performance of peripheral circuit region P.Thereby, can further improve the reliability of semiconductor device.

On the whole surface of Semiconductor substrate, form interlevel insulator 7e with nmos pass transistor T1 and T2, PMOS transistor P1 and nmos pass transistor N1.Before forming interlayer insulating film 7e, can additionally form etching stop layer 7d.

With reference to Figure 16 A, Figure 25, with Figure 31 A and 31B, etching interlevel insulator 2e, 5e and 7e and

etching stop layer

2d, 5d and 7d are to form the source area T1S that exposes nmos pass transistor T1, last node semiconductor plug 4a ', the drain region PU1D of transistor PU1, following node semiconductor plug 3a ', gate electrode PU2G, with the node contact hole 7f of gate electrode PD2G and the source area T2S of formation exposure nmos pass transistor T2, last node semiconductor plug 4a "; the drain region PU2D of transistor PU2; following node semiconductor plug 3a ", gate electrode PU1G, node contact hole 7f with gate electrode PD1G.

Simultaneously, " have under the situation of conduction type different with PD2D or intrinsic semiconductor, can form node contact hole 7f ' and 7f respectively " to expose drain region PD1D and the PD2D of MOS transistor PD1 and PD2 at following node semiconductor plug 3a ' and 3a with drain region PD1D.

Have node contact hole 7f ' and 7f " Semiconductor substrate on form conductive layer.This conductive layer of planarization is to expose interlevel insulator 7e.As a result, form node contact plunger 8a ' and 8a ".Node contact plunger 8a ' and 8a " are preferably formed by the conductive layer that demonstrates the ohmic contact characteristic of p and n N-type semiconductor N.For example, conductive layer can be formed by the metal level of for example tungsten layer.And the barrier metal layer by sequentially piling up titanium nitride layer for example and the metal level of for example tungsten layer form conductive layer.In this case, form each node contact plunger 8a ' and 8a " to have tungsten plug and around the barrier metal layer pattern of tungsten plug.

Have node contact plunger 8a ' and 8a " Semiconductor substrate on form interlevel insulator 9c.

With reference to Figure 16 A, Figure 25 and Figure 32 A and 32B, formation penetrates interlevel insulator 2e, 5e, 7e and 9c and etching stop layer 2d, 5d and 7d, to contact second respectively source area PD1S among the 1a ' of source region and having ideals, morality, culture, and discipline source region 1a " source area PD2S earth connection contact plunger 9b ' and 9b " is arranged.Forming earth connection contact plunger 9b ' and 9b " in, the power line contact plunger 9a ' and the 9a of the extension (the source area PU2S of load transistor) of the extension (the source area PU1S of load transistor) of main body pattern 3b ' and following main body pattern 3b under formation contacts respectively ".And, forming earth connection contact plunger 9b ' and 9b " in; form and contact the source area P1S of PMOS transistor P1 and output signal line contact plunger 9e and the peripheral power supply line contact plunger 9f of drain region P1D respectively, and formation contacts the source area N1S of nmos pass transistor N1 and output signal line contact plunger 9e ' and the peripheral power supply line contact plunger 9f of drain region N1D respectively.Contact plunger 9a ', 9a ", 9b ', 9b ", 9f, 9e, 9f ' and 9e ' are preferably formed by the conductive layer that demonstrates the ohmic contact characteristic of p and n N-type semiconductor N.For example, with form with reference to Figure 31 A and 31B described node contact plunger 8a ' and 8a " same method formation contact plunger 9a ', 9a ", 9b ', 9b ", 9f, 9e, 9f ' and 9e '.

Form interlevel insulator 11 on contact plunger 9a ', 9a ", 9b ', 9b ", 9f, 9e, 9f ' and the 9e ' Semiconductor substrate having.

With reference to Figure 16 A, Figure 25 and Figure 33 A and 33B, in interlevel insulator 11, form unit earth connection 10a and unit power line 10b.When forming unit earth connection 10a and unit power line 10b, in the interlevel insulator 11 of peripheral circuit region P, can form peripheral power supply line 10e, peripheral earth connection 10f and output signal line 10g.

In an embodiment of the present invention, in figure, described inverter, but peripheral circuit is not limited thereto as the example of peripheral circuit.That is to say that the MOS transistor of peripheral circuit region P can be as the parts of different peripheral circuits.That is to say that peripheral power supply line 10e, peripheral earth connection 10f and output signal line 10g will carry out the inverter as the example of peripheral circuit, the PMOS transistor of peripheral circuit region P can be formed different peripheral circuits with nmos pass transistor.

Form unit earth connection 10a and unit power line 10b to be arranged essentially parallel to word line 6b.Form unit earth connection 10 to cover earth connection contact plunger 9b ' and 9b ", form unit power line 10b to cover power line contact plunger 9a ' and 9a ".Form output signal line 10g to cover output signal line contact plunger 9e ' and 9f.Form peripheral earth connection 10f to cover peripheral earth connection contact plunger 9f '.When forming output signal line 10g, can form and be electrically connected to peripheral PMOS gate electrode 23a ' and peripheral NMOS gate electrode 20c " input signal cable 10h.Input signal cable 10h is electrically connected to peripheral PMOS gate electrode 23a ' and peripheral NMOS gate electrode 20c by the input signal cable contact plunger ".On Semiconductor substrate, form interlevel insulator 12 with

earth connection

10a and 10f,

power line

10b and 10e, output signal line 10g, input signal cable 10h.

With reference to Figure 16 A, Figure 25 and Figure 34 A and 34B, etching interlevel insulator 7e, 9c, 11 and 12 and etching stop layer 7d are with first and second contact plunger 13a ' and the 13a of the drain region T2D that forms the drain region T1D that contacts nmos pass transistor T1 respectively and nmos pass transistor T2 ".On interlevel insulator 12, form the first and second parallel bit lines 14.Form first and second bit lines 14 to cross over unit earth connection 10a and unit power line 10b.Form first bit line 14 to cover bit line contact plug 13a ', form second bit line 14 " to cover bit line contact plug 13a.

Described the foregoing description that concentrates on the static semiconductor memory, but peripheral circuit of the present invention can be used in the dynamic semiconductor memory device to reduce the layout area size.

As described in before this, can reduce whole layout area size according to semiconductor memory of the present invention and its method for arranging, because can pile up the transistor of forming peripheral circuit and memory cell array.

And, can provide according to semiconductor memory of the present invention and its manufacture method and to have the highly integrated memory cell and the semiconductor integrated circuit of high performance periphery transistor, be arranged in the memory cell array because have the memory cell of thin-film transistor, periphery transistor is arranged in the peripheral main body pattern of the single crystalline semiconductor structure of being grown by the Semiconductor substrate of peripheral circuit region.That is to say, can carry out stable operation by transistor that piles up the composition memory cell array and the transistor of on the 3rd layer, arranging the composition peripheral circuit.

The application requires in the rights and interests of the korean patent application No.2005-38621 of the korean patent application No.2004-61527 of application on August 4th, 2004 and application on May 9th, 2005, and its whole contents is bonded to herein with the form of quoting.

Claims

1. integrated circuit memory devices comprises:

Semiconductor substrate; With

On described Semiconductor substrate, have the NAND door of NMOS pull-down transistor to arranging with the vertical stacking that it is right that PMOS pulls up transistor.

2. according to the storage component part of claim 1, wherein said vertical stacking is arranged body semiconductor regions and the semiconductor layer on described body semiconductor regions that is included in the described Semiconductor substrate; And wherein said NMOS pull-down transistor is to pulling up transistor of centering in described body semiconductor regions with PMOS, and described NMOS pull-down transistor is to pulling up transistor another of centering in described semiconductor layer with PMOS.

3. integrated circuit memory devices comprises:

Semiconductor substrate;

On described Semiconductor substrate, comprise that nmos access transistor is to, NMOS pull-down transistor static RAM (SRAM) unit to arranging with the vertical stacking that it is right that PMOS pulls up transistor; With

On described Semiconductor substrate, be included in the gate of the vertical stacking layout of the MOS transistor on three grades.

4. according to the storage component part of claim 3, wherein said sram cell is arranged in the memory cell part of described Semiconductor substrate; And wherein said gate is arranged in the peripheral circuit part of described Semiconductor substrate.

5. according to the storage component part of claim 4, wherein said gate is selected from the group of being made up of inverter, NAND door and NOR door.

6. according to the storage component part of claim 3, wherein said gate is selected from the group of being made up of inverter, NAND door and NOR door.

7. according to the storage component part of claim 3, wherein said gate is nmos pass transistor and the transistorized inverter of PMOS that comprises two parallel connections.

8. according to the storage component part of claim 7, two nmos pass transistors in the wherein said inverter are stacked on in three layers two mutual vertically.

9. storage component part according to Claim 8, one in wherein said two nmos pass transistors is the body nmos pass transistor.

10. according to the storage component part of claim 9, the PMOS transistor layout in the wherein said inverter is between two nmos pass transistors.

11. according to the storage component part of claim 3, wherein said gate is to comprise the nmos pass transistor of two parallel connections and the inverter of a nmos pass transistor.

12. according to the storage component part of claim 11, two PMOS transistors in the wherein said inverter are stacked on in three layers two mutual vertically.

13. according to the storage component part of claim 11, one in wherein said two PMOS transistors is body PMOS transistor.

14. according to the storage component part of claim 13, the nmos pass transistor in the wherein said inverter is arranged between two PMOS transistors.

15. according to the storage component part of claim 14, the nmos pass transistor in the wherein said inverter is a thin-film transistor.

16. a semiconductor device comprises:

Comprise respectively at least one first pull up transistor and first pull-down transistor and the conversion and output input signal a plurality of inverters; With

If comprise that respectively at least two second pull up transistor and at least one of second pull-down transistor and two input signals has a plurality of NAND doors that low level just produces the output signal with high level at least,

Wherein said at least one first pull up transistor and first pull-down transistor and described at least two second pull up transistor and second pull-down stack of transistors and being arranged at least two layers.

17. according to the device of claim 16, wherein said first and second to pull up transistor be the PMOS transistor, described first and second pull-down transistors are nmos pass transistors.

18. according to the device of claim 17, the transistor of wherein waiting to be arranged on the ground floor is a body transistor, wait to be arranged in second or more multi-layered on transistor be thin-film transistor.

19. according to the device of claim 18, some of wherein said first and second some that pull up transistor and described first and second pull-down transistors are arranged on the ground floor jointly.

20. according to the device of claim 19, wherein only described first and second pull up transistor or only described first and second pull-down transistors be arranged in second or more multi-layered on.

21. a semiconductor device comprises:

Comprise that respectively at least one first pulls up transistor and a plurality of inverters of first pull-down transistor and conversion and output input signal;

If comprise that respectively at least two second pull up transistor and at least one of second pull-down transistor and two input signals has low level and just produce a plurality of NAND doors with high level output signal at least; With

If comprise that respectively at least two the 3rd pull up transistor and the 3rd pull-down transistor and two all input signals all have a plurality of NOR doors that low level just produces the output signal with high level at least,

Wherein said at least one first pull up transistor and first pull-down transistor, described at least two second pull up transistor and second pull-down transistor, described at least two the 3rd pull up transistor and the 3rd pull-down stack of transistors and be arranged in two-layer at least on.

22. according to the device of claim 21, wherein said first to the 3rd to pull up transistor be the PMOS transistor, described first to the 3rd pull-down transistor is a nmos pass transistor.

23. according to the device of claim 22, the transistor of wherein waiting to be arranged on the ground floor is a body transistor, wait to be arranged in second or more multi-layered on transistor be thin-film transistor.

24. according to the device of claim 23, some of wherein said first to the 3rd some that pull up transistor and described first to the 3rd pull-down transistor are arranged on the ground floor jointly.

25. according to the device of claim 24, wherein only described first to the 3rd pull up transistor or only described first to the 3rd pull-down transistor be arranged in second or more multi-layered on.

26. a semiconductor memory comprises:

Memory cell array comprises a plurality of word line selection signals of response and a plurality of array selecting signal and a plurality of memory cells of access;

Row decoder is used for the decode line address to produce a plurality of word line selection signals; With

Column decoder is used to decipher column address to produce a plurality of array selecting signals;

Wherein said row (row) decoder comprises a plurality of inverters, and each in described a plurality of inverters comprises that all at least one pulls up transistor and pull-down transistor, draw on described with pull-down stack of transistors and be arranged in two-layer at least on.

27. according to the device of claim 26, wherein said a plurality of memory cells comprise a plurality of nmos pass transistors, and described a plurality of nmos pass transistor pile up and be arranged in two-layer at least on.

28. according to the device of claim 27, wherein said pulling up transistor is the PMOS transistor, described pull-down transistor is a nmos pass transistor.

29. according to the device of claim 28, the transistor of wherein waiting to be arranged on the ground floor is a body transistor, wait to be arranged in second or more multi-layered on transistor be thin-film transistor.

30. according to the device of claim 29, some of wherein said some that pull up transistor and described pull-down transistor are arranged on the ground floor jointly.

31. according to the device of claim 30, wherein only described pull up transistor or only described pull-down transistor be arranged in second or more multi-layered on.

32. according to the device of claim 31, wherein dispose at least two and pull up transistor, and described at least two pull up transistor and are arranged on the different layers by dividing each channel width that pulls up transistor.

33. according to the device of claim 32, wherein dispose at least two pull-down transistors, and described at least two pull-down transistors are arranged on the different layers by the channel width of dividing each pull-down transistor.

34. device according to claim 26, wherein said row (OK) decoder comprises a plurality of inverters, in described a plurality of inverter each comprises that all at least one pulls up transistor and pull-down transistor, draws on described with pull-down stack of transistors and is arranged at least two layers.

35. according to the device of claim 34, wherein said a plurality of memory cells comprise a plurality of nmos pass transistors, and described a plurality of nmos pass transistor pile up and be arranged in two-layer at least on.

36. according to the device of claim 35, wherein said pulling up transistor is the PMOS transistor, described pull-down transistor is a nmos pass transistor.

37. according to the device of claim 36, the transistor of wherein waiting to be arranged on the ground floor is a body transistor, wait to be arranged in second or more multi-layered on transistor be thin-film transistor.

38. according to the device of claim 37, some of wherein said some that pull up transistor and described pull-down transistor are arranged on the ground floor jointly.

39. according to the device of claim 38, wherein only described pull up transistor or only described pull-down transistor be arranged in second or more multi-layered on.

40. according to the device of claim 39, wherein dispose at least two and pull up transistor, and described at least two pull up transistor and are arranged on the different layers by dividing each channel width that pulls up transistor.

41. according to the device of claim 39, wherein dispose at least two pull-down transistors, and described at least two pull-down transistors are arranged on the different layers by the channel width of dividing each pull-down transistor.

42. a semiconductor memory comprises:

Column decoder is used to decipher column address producing a plurality of array selecting signals,

Wherein said row (row) decoder comprises a plurality of inverters and a plurality of NAND door, in described a plurality of inverter each comprises that all at least one first pulls up transistor and first pull-down transistor, in described a plurality of NAND door each comprises that all at least two second pull up transistor and second pull-down transistor, and described first and second pull up transistor and described first and second pull-down stack of transistors and be arranged in two-layer at least on.

43. according to the device of claim 42, wherein said a plurality of memory cells comprise a plurality of nmos pass transistors, described a plurality of nmos pass transistors pile up and be arranged in two-layer at least on.

44. according to the device of claim 43, wherein said first and second to pull up transistor be the PMOS transistor, described first and second pull-down transistors are nmos pass transistors.

45. according to the device of claim 44, the transistor of wherein waiting to be arranged on the ground floor is a body transistor, wait to be arranged in second or more multi-layered on transistor be thin-film transistor.

46. according to the device of claim 45, some of wherein said first and second some that pull up transistor and described first and second pull-down transistors are arranged on the ground floor jointly.

47. according to the device of claim 46, wherein only described first and second pull up transistor or only described first and second pull-down transistors be arranged in second or more multi-layered on.

48. according to the device of claim 31, wherein dispose at least two first and second and pull up transistor, and described at least two first and second pull up transistor and are arranged on the different layers by dividing each first and second channel width that pulls up transistor.

49. according to the device of claim 48, wherein dispose at least two first and second pull-down transistors, and described at least two first and second pull-down transistors are arranged on the different layers by the channel width of dividing each first and second pull-down transistor.

50. device according to claim 42, wherein said row (OK) decoder comprises a plurality of inverters and a plurality of NAND door, in described a plurality of inverter each comprises that all at least one first pulls up transistor and first pull-down transistor, in described a plurality of NAND door each comprises that all at least two second pull up transistor and second pull-down transistor, described first and second pull up transistor and described first and second pull-down stack of transistors and be arranged in two-layer at least on.

51. according to the device of claim 50, wherein said a plurality of memory cells comprise a plurality of nmos pass transistors, and described a plurality of nmos pass transistor pile up and be arranged in two-layer at least on.

52. according to the device of claim 51, wherein said first and second to pull up transistor be the PMOS transistor, described first and second pull-down transistors are nmos pass transistors.

53. according to the device of claim 52, the transistor of wherein waiting to be arranged on the ground floor is a body transistor, wait to be arranged in second or more multi-layered on transistor be thin-film transistor.

54. according to the device of claim 53, some of wherein said first and second some that pull up transistor and described first and second pull-down transistors are arranged on the ground floor jointly.

55. according to the device of claim 54, wherein only described first and second pull up transistor or only described first and second pull-down transistors be arranged in second or more multi-layered on.

56., wherein dispose at least two first and second and pull up transistor, and draw the body pipe to be arranged on the different layers at least on described two first and second by dividing each first and second channel width that pulls up transistor according to the device of claim 55.

57. according to the device of claim 55, wherein dispose at least two first and second pull-down transistors, and described at least two first and second pull-down transistors are arranged on the different layers by the channel width of dividing each first and second pull-down transistor.

58. a semiconductor memory comprises:

Memory cell array comprises a plurality of word line selection signals of response and a plurality of array selecting signal and a plurality of memory cells of access; And

Peripheral circuit, comprise be used for the decode line address with the row decoder that produces a plurality of word line selection signals, be used to decipher column address with the column decoder that produces a plurality of array selecting signals be used to control and enter data into memory cell array and from the controller of memory cell array dateout

Wherein said peripheral circuit comprises a plurality of inverters, a plurality of NAND door and a plurality of NOR door, in described a plurality of inverter each comprises that all at least one first pulls up transistor and first pull-down transistor, in described a plurality of NAND door each comprises that all at least two second pull up transistor and second pull-down transistor, in described a plurality of NOR door each comprises that all at least three the 3rd pull up transistor and the 3rd pull-down transistor, and described first to the 3rd pulls up transistor and first to the 3rd pull-down stack of transistors and being arranged at least two layers.

59. according to the device of claim 58, wherein said a plurality of memory cells comprise a plurality of nmos pass transistors, and described a plurality of nmos pass transistor piles up and is arranged at least two layers.

60. according to the device of claim 59, wherein said first to the 3rd to pull up transistor be the PMOS transistor, described first to the 3rd pull-down transistor is a nmos pass transistor.

61. according to the device of claim 60, the transistor of wherein waiting to be arranged on the ground floor is a body transistor, wait to be arranged in second or more multi-layered on transistor be thin-film transistor.

62. according to the device of claim 61, some of wherein said first to the 3rd some that pull up transistor and described first to the 3rd pull-down transistor are arranged on the ground floor jointly.

63. according to the device of claim 62, wherein only described first to the 3rd pull up transistor or only described first to the 3rd pull-down transistor be arranged in second or more multi-layered on.

64. according to the device of claim 63, wherein pull up transistor by dividing described first to the 3rd at least two first to the 3rd of the channel width configurations that pull up transistor, described at least two first to the 3rd transistor layout are on different layers.

65. according to the device of claim 47, wherein dispose at least two first to the 3rd pull-down transistors by the channel width of dividing first to the 3rd pull-down transistor, described at least two first to the 3rd pull-down transistors are arranged on the different layers.

66. the method for arranging of a semiconductor memory comprises:

On two-layer at least, pile up and arrange that each two transmission transistors, two first in the memory cell of forming a plurality of memory cell arrays pull up transistor, two first pull-down transistors; And

On at least two layers, pile up and arrange that each at least one in a plurality of inverters of forming peripheral circuit second pulls up transistor and second pull-down transistor and each two the 3rd that form in a plurality of NAND doors pull up transistor and the 3rd pull-down transistor at least.

67. according to the method for claim 66, wherein said first to the 3rd to pull up transistor be the PMOS transistor, described first to the 3rd pull-down transistor is a nmos pass transistor.

68. according to the method for claim 67, the transistor of wherein waiting to be arranged on the ground floor is a body transistor, wait to be arranged in second or more multi-layered on transistor be thin-film transistor.

69. method according to claim 68, wherein regardless of the transistorized type on the ground floor of waiting to be arranged in described memory cell array, wait to be arranged in transistor on the ground floor at least two layers of described peripheral circuit and be can with the described second and the 3rd pull up transistor and some transistors of arranging together of the described second and the 3rd pull-down transistor.

70. according to the method for claim 69, wherein only arrange have with at least two layers that are arranged in described peripheral circuit second or more multi-layered on the second and the 3rd the pulling up transistor or the second and the 3rd pull-down transistor only of transistor same type.

71. according to the method for claim 70, wherein dispose at least two second and the 3rd and pull up transistor, and described at least two second and the 3rd pull up transistor and are arranged on the different layers by dividing second to the 3rd channel width that pulls up transistor.

72. according to the method for claim 70, wherein dispose at least two second and the 3rd pull-down transistor, and described at least two second and the 3rd pull-down transistor are arranged on the different layers by the channel width of dividing the second and the 3rd pull-down transistor.

73. the method for arranging of a semiconductor memory comprises:

Two transmission transistors, two first that pile up and arrange in a plurality of memory cells of forming memory cell array each at least two layers pull up transistor, two first pull-down transistors; With

On at least two layers, pile up and arrange in a plurality of inverters of forming peripheral circuit each at least one second pull up transistor and second pull-down transistor, form in a plurality of NAND doors that each at least two the 3rd pull up transistor and the 3rd pull-down transistor and form in a plurality of NOR doors each at least two the 4th and pull up transistor and the 4th pull-down transistor.

74. according to the method for claim 73, wherein said first to fourth to pull up transistor be the PMOS transistor, described first to the 3rd pull-down transistor is a nmos pass transistor.

75. according to the method for claim 74, the transistor of wherein waiting to be arranged on the ground floor is a body transistor, wait to be arranged in second or more multi-layered on transistor be thin-film transistor.

76. method according to claim 75, wherein regardless of the transistorized type on the ground floor of waiting to be arranged in described memory cell array, wait to be arranged in transistor on the ground floor at least two layers of peripheral circuit and be can with described second to the 4th pull up transistor and the transistor of some layouts of described second to the 4th pull-down transistor.

77. according to the method for claim 75, wherein only arrange have be arranged in peripheral circuit two-layer at least second or more multi-layered on first to fourth the pulling up transistor or first to fourth pull-down transistor of transistor same type.

78. according to the method for claim 77, wherein dispose at least two second to the 4th and pull up transistor, and described at least two second to the 4th pull up transistor and are arranged on the different layers by dividing second to the 4th channel width that pulls up transistor.

79. according to the method for claim 77, wherein dispose at least two second to the 4th pull-down transistors, and described at least two second to the 4th pull-down transistors are arranged on the different layers by the channel width of dividing second to the 4th pull-down transistor.

80. a semiconductor device comprises:

Semiconductor substrate with unit area and peripheral circuit region;

Be arranged in the body transistor on the Semiconductor substrate of described unit area;

Be arranged in the described unit area to cover the interlevel insulator pattern of described body transistor;

Be arranged in the thin-film transistor on the described interlevel insulator pattern;

Layout is with the peripheral main body pattern of the Semiconductor substrate that contacts described peripheral circuit region; With

Be arranged in the periphery transistor in the described peripheral main body pattern, described periphery transistor be arranged in the essentially identical imaginary horizontal line of the thin-film transistor of described unit area on.

81. 0 device according to Claim 8, wherein said peripheral main body pattern is a single crystalline semiconductor structure.

82. 0 device according to Claim 8, wherein said thin-film transistor is the monocrystal thin films transistor.

83. 0 device according to Claim 8, wherein said body transistor and described thin-film transistor are the cell transistors of SRAM memory cell.

84. 0 device according to Claim 8, wherein said body transistor comprises first and second body transistors, described thin-film transistor comprises first and second thin-film transistors, arranges that described first and second thin-film transistors are with overlapping described first and second body transistors of difference.

85. 4 device according to Claim 8, also comprise, be arranged in first and second times thin-film transistors between described first and second body transistors and described first and second thin-film transistors, wherein said first and second times thin-film transistors are arranged overlapping described first and second body transistors respectively.

86. 5 device also comprises according to Claim 8,

The first node connector is used for being electrically connected by described interlevel insulator first ion doping zone and the transistorized first ion doping zone of described first upper film of the first ion doping zone of described first body transistor, described first time thin-film transistor; With

The second node connector is used for being electrically connected by described interlevel insulator first ion doping zone and the transistorized first ion doping zone of described second upper film of the first ion doping zone of described second body transistor, described second time thin-film transistor.

87. 6 device according to Claim 8, wherein said first and second body transistors are respectively the first and second n channel driver transistors, and the first ion doping zone of described first and second body transistors is drain regions.

88. 7 device according to Claim 8, the gate electrode of wherein said first driving transistors is electrically connected to the described second node connector, and the grid of described second driving transistors are electrically connected to the described first node connector.

89. 8 device according to Claim 8, wherein said first and second times thin-film transistors are respectively the first and second p raceway groove load transistors, described first and second thin-film transistors are first and second n channel pass transistor, the first ion doping zone of described first and second times thin-film transistors is drain regions, and the first ion doping zone of described first and second thin-film transistors is source areas.

90. 9 device according to Claim 8, wherein arrange the gate electrode of the gate electrode of described first and second load transistors with overlapping described first and second driving transistorss, the gate electrode of described first load transistor is electrically connected to the described second node connector, and the gate electrode of described second load transistor is electrically connected to the described first node connector.

91. according to the device of claim 90, the gate electrode of wherein said first and second thin-film transistors is electrically connected to each other to form word line.

92. 0 device according to Claim 8, wherein peripheral at least transistor comprises the metal silicide layer that is arranged on the peripheral gate electrode surface.

93. comprising, 0 device according to Claim 8, wherein peripheral at least transistor be arranged in the peripheral lip-deep metal silicide layer of source area and drain region.

94. a method of making semiconductor device comprises:

Preparation has the Semiconductor substrate of unit area and peripheral circuit region;

Be formed on the body transistor on the Semiconductor substrate of described unit area;

Has the interlevel insulator pattern that forms the Semiconductor substrate that exposes described peripheral circuit region on the Semiconductor substrate of body transistor;

Form unit main body pattern and peripheral main body pattern on the expose portion of described Semiconductor substrate and described interlevel insulator pattern, wherein said peripheral main body pattern contacts the expose portion of described Semiconductor substrate; With

In described unit main body pattern and described peripheral main body pattern, form unit film transistor and periphery transistor respectively.

95. according to the method for claim 94, the step that wherein forms described unit main body pattern and described peripheral main body pattern comprises:

On Semiconductor substrate, form semiconductor layer with described interlevel insulator pattern; With

The described semiconductor layer of planarization is to form elemental semiconductor layer and peripheral semiconductor layer on the Semiconductor substrate of interlevel insulator pattern and peripheral circuit region, wherein said peripheral semiconductor layer is than described semiconductor bed thickness.

96. according to the method for claim 95, wherein said semiconductor layer is formed by non-single crystal semiconductor layer.

97. the method according to claim 96 also comprises, before or after the described semiconductor layer of planarization, utilization use Semiconductor substrate is come the described semiconductor layer of crystallization as the solid phase epitaxy layer of inculating crystal layer.

98. according to the method for claim 94, the step that wherein forms described interlevel insulator pattern comprises:

Form interlevel insulator having on the Semiconductor substrate of body transistor; With

The described interlevel insulator of patterning is with the contact hole of the presumptive area of the Semiconductor substrate of the Semiconductor substrate that form to expose described peripheral circuit region and described unit area.

99. according to the method for claim 78, the step that wherein forms described unit main body pattern and described peripheral main body pattern comprises:

On the expose portion of the Semiconductor substrate of described peripheral circuit region and described interlevel insulator pattern, form single crystalline semiconductor structure; With

The described single crystalline semiconductor structure of planarization.

100. according to the method for claim 79, wherein the Semiconductor substrate by utilize using the exposure that is touched Semiconductor substrate that the hole exposes and peripheral circuit region forms single crystalline semiconductor structure as the selective epitaxial growth method of inculating crystal layer.

101. according to the method for claim 94, the step that wherein forms described unit film transistor and described periphery transistor comprises:

Form respectively unit gate electrode and peripheral gate electrode across described unit main body pattern and described peripheral main body pattern;

Use described gate electrode to come described unit main body pattern of ion doping and described peripheral main body pattern, in the unit main body pattern, to form cell source district and drain region and peripheral source area and drain region in peripheral main body pattern as the ion doping mask.

102. the method according to claim 101 also comprises, forms metal silicide layer selectively on the surface of peripheral gate electrode and/or peripheral source area and drain region.

103. a method of making semiconductor device comprises:

Organizator transistor on the Semiconductor substrate of described unit area;

Have insulator pattern between the ground floor that forms the Semiconductor substrate that exposes peripheral circuit region on the Semiconductor substrate of body transistor, insulator pattern has first contact hole of the presumptive area in the ion doping zone that exposes described body transistor between described ground floor;

Be formed for covering main body pattern under the unit of described first contact hole on the insulator pattern between described ground floor;

Under described unit, form thin-film transistor under the unit in the main body pattern;

Be formed for covering insulator pattern between the second layer of thin-film transistor under the described unit on the insulator pattern between described ground floor, insulator pattern has second contact hole that exposes the presumptive area in the ion doping zone of thin-film transistor under the described unit between the described second layer;

Be formed for covering main body pattern on the unit of second contact hole on the insulator pattern between the described second layer and form peripheral main body pattern in the peripheral circuit region; With

Form the periphery transistor in the unit upper film transistor in the main body pattern and described peripheral main body pattern on the described unit.

104. the method according to claim 103 also comprises, is formed for covering main body pattern and peripheral main body pattern under the unit of Semiconductor substrate of described peripheral circuit region.

105., form wherein under the described unit that the step of main body pattern comprises under the main body pattern and described periphery according to the method for claim 104

Form first single crystalline semiconductor structure, described first single crystalline semiconductor structure is filled first contact hole and is covered the Semiconductor substrate of insulator pattern and peripheral circuit region between ground floor; With

Described first single crystalline semiconductor structure of planarization.

106., wherein form main body pattern on the described unit and the described outer step of placing the main body pattern comprises according to the method for claim 105

Form second single crystalline semiconductor structure, described second single crystalline semiconductor structure is filled second contact hole and is covered the Semiconductor substrate of insulator pattern and peripheral circuit region between the second layer;

Described second single crystalline semiconductor structure of planarization; With

Described second single crystalline semiconductor structure of patterning, place the main body pattern with main body pattern on the formation unit in described unit area with outside in described peripheral circuit region, forming, form the peripheral main body pattern that has peripheral main body pattern down and place the main body pattern outward thus.

107. according to the method for claim 106, wherein by using growth technology to form single crystalline semiconductor structure.

108. according to the method for claim 103, the step that wherein forms main body pattern under the described unit comprises

Form first single crystalline semiconductor structure, described first single crystalline semiconductor structure is filled first contact hole and is covered the Semiconductor substrate of insulator pattern and described peripheral circuit region between described ground floor; With

Described first single crystalline semiconductor structure of patterning is to expose the Semiconductor substrate of described peripheral circuit region.

109., form wherein that the step of main body pattern and described peripheral main body pattern comprises on the described unit according to the method for claim 108

Form second single crystalline semiconductor structure, described second single crystalline semiconductor structure is filled second contact hole and is covered the Semiconductor substrate of insulator pattern and peripheral circuit region between the described second layer, and has smooth upper surface; With

Described second single crystalline semiconductor structure of patterning is with main body pattern on the formation unit in described unit area and form peripheral main body pattern in described peripheral circuit region.

110. according to the method for claim 109, wherein by using growth technology to form described single crystalline semiconductor structure.

111. according to the method for claim 103, wherein body transistor is a n type channel driver transistors, thin-film transistor is a P type raceway groove load transistor under the unit, and unit upper film transistor is a n type channel pass transistor.

112., wherein form described unit upper film transistor and the transistorized step of described peripheral upper film comprises according to the method for claim 103

Form respectively across gate electrode and peripheral gate electrode on the unit of main body pattern on the described unit and described peripheral main body pattern; With

Use described gate electrode to come main body pattern and described peripheral main body pattern on the described unit of ion doping, to form source, unit and drain region and described peripheral source and the drain region of in peripheral main body pattern, forming in the main body pattern on described unit as the ion doping mask.

113. the method according to claim 112 also comprises, forms metal silicide layer selectively on the surface of described peripheral gate electrode and/or peripheral source area and drain region.