KR20060009420A - Method for forming metal interconnection line of semiconductor device - Google Patents

Method for forming metal interconnection line of semiconductor device Download PDF

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KR20060009420A
KR20060009420A KR1020040056736A KR20040056736A KR20060009420A KR 20060009420 A KR20060009420 A KR 20060009420A KR 1020040056736 A KR1020040056736 A KR 1020040056736A KR 20040056736 A KR20040056736 A KR 20040056736A KR 20060009420 A KR20060009420 A KR 20060009420A
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wiring
metal wiring
metal
forming
film
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KR1020040056736A
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Korean (ko)
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김봉천
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

본 발명은 금속배선 형성시 발생하는 구리 잔여물(Residue)을 제거하여 금속배선 간의 결함(Shortage)을 방지할 수 있는 반도체 소자의 금속배선 형성방법을 개시한다. 개시된 본 발명은 하부 금속배선이 형성된 반도체 기판을 제공하는 단계; 상기 하부 금속배선을 덮도록 기판 상에 층간절연막을 형성하는 단계; 상기 층간절연막을 식각하여 하부 금속배선을 노출시키는 콘택홀을 포함한 상부 금속배선 형성 영역을 한정하는 트렌치를 형성하는 단계; 상기 콘택홀을 포함한 트렌치를 매립하도록 층간절연막 상에 확산베리어막과 배선용 금속막을 차례로 증착하는 단계; 상기 확산베리어막이 노출되도록 배선용 금속막을 1차로 CMP하는 단계; 및 상기 층간절연막이 노출되도록 확산베리어막을 2차로 CMP하여 상부 금속배선을 형성하는 단계를 포함하며, 상기 트렌치를 형성하는 단계시 상부 금속배선 형성 영역들 사이에 더미 트렌치들을 형성하여, 상기 배선용 금속막 CMP시 금속 잔여물 발생을 방지시키는 더미 패턴이 형성되도록 하는 것을 특징으로 한다.The present invention discloses a method for forming a metal wiring of a semiconductor device capable of preventing a residue between the metal wirings by removing copper residues generated when the metal wiring is formed. The present invention provides a method of manufacturing a semiconductor substrate, the method comprising: providing a semiconductor substrate on which a lower metal wiring is formed; Forming an interlayer insulating film on the substrate to cover the lower metal wiring; Etching the interlayer insulating layer to form a trench defining an upper metal wiring forming region including a contact hole exposing a lower metal wiring; Sequentially depositing a diffusion barrier film and a wiring metal film on the interlayer insulating film so as to fill the trench including the contact hole; CMPing the wiring metal film primarily so that the diffusion barrier film is exposed; And forming an upper metal wiring by secondly CMPing the diffusion barrier film so that the interlayer insulating film is exposed, and forming dummy trenches between the upper metal wiring formation regions during the forming of the trench, wherein the metal film for wiring is formed. It is characterized in that to form a dummy pattern to prevent the generation of metal residues during CMP.

Description

반도체 소자의 금속배선 형성방법{METHOD FOR FORMING METAL INTERCONNECTION LINE OF SEMICONDUCTOR DEVICE}METHOD FOR FORMING METAL INTERCONNECTION LINE OF SEMICONDUCTOR DEVICE}

도 1은 종래 반도체 소자의 금속배선 형성방법의 문제점을 설명하기 위한 공정단면도.1 is a cross-sectional view illustrating a problem of a method for forming metal wiring of a conventional semiconductor device.

도 2a 내지 2c는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도.2A to 2C are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

21 : 반도체 기판 23 : 하부 금속배선21 semiconductor substrate 23 lower metal wiring

25 : 층간절연막 26 : 콘택홀25: interlayer insulating film 26: contact hole

27a : 트렌치 27b : 더미 트렌치27a: trench 27b: dummy trench

28 : 확산베리어막 29 : 배선용 금속막28: diffusion barrier film 29: wiring metal film

30 : 상부 금속배선 31 : 더미 패턴30: upper metal wiring 31: dummy pattern

본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 금속배선 형성시 발생하는 구리 잔여물(Residue)을 제거하여 금속배선 간의 결함 (Shortage)을 방지할 수 있는 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to forming a metal wiring of a semiconductor device capable of preventing a defect between metal wirings by removing copper residues generated during metal wiring formation. It is about a method.

일반적으로, 반도체 소자의 금속배선 공정은 화학적기계연마(Chemical Mechanical Polishing : CMP) 공정을 이용하여 층간절연막에 트렌치를 형성한 후에 베리어 금속막(Barrier Metal)과 배선 금속막을 증착한 다음, CMP 공정을 통해 층간절연막 상부에 증착된 베리어 금속막과 배선 금속막을 제거하는 방법으로 이루어진다. 아울러, 알루미늄(Al) 또는 구리(Cu)를 배선 금속막으로 사용할 경우, 그 하부에 Ti/TiN 또는 Ta/TaN 등의 확산베리어막이 적용된다. In general, a metal wiring process of a semiconductor device is formed by forming a trench in an interlayer insulating film using a chemical mechanical polishing (CMP) process, depositing a barrier metal film and a wiring metal film, and then performing a CMP process. The barrier metal film and the wiring metal film deposited on the interlayer insulating film are removed. In addition, when aluminum (Al) or copper (Cu) is used as the wiring metal film, a diffusion barrier film such as Ti / TiN or Ta / TaN is applied to the lower portion thereof.

그러나, 구리 배선은 다마신(Damascene) 배선 구조를 가지므로, 일반적인 CMP 공정과 달리, 부식(Erosion)에 취약하다. 일반적으로, 금속 배선의 부식은 구리 배선이 형성되는 패턴 내의 유전막의 손실(Loss)양을 말하며, 구리 배선을 CMP하는 경우, 다마신 구조를 갖는 패턴에서 발생되는 부식은 구리 배선의 증착 두께와 패턴 크기에 따라 변하게 된다. 이러한 부식의 변동은 구리 배선의 저항, 동작속도 및 신뢰성에 영향을 미치므로, 부식의 발생을 최소화하기 위해 구리 배선 주변에 더미 패턴(Dummy Pattern)을 형성한다.However, copper wiring has a damascene wiring structure and, unlike the general CMP process, is susceptible to corrosion. In general, corrosion of metal wiring refers to the amount of loss of the dielectric film in the pattern in which the copper wiring is formed, and in the case of CMP of the copper wiring, the corrosion occurring in the pattern having the damascene structure is determined by the deposition thickness and pattern of the copper wiring. It varies with size. This variation in corrosion affects the resistance, operating speed and reliability of the copper wiring, so that a dummy pattern is formed around the copper wiring to minimize the occurrence of corrosion.

일반적으로, 더미 패턴은 구리배선과 일정 간격을 유지하도록 사각형 또는 변형된 십자형 모양으로 형성되나, 금속배선 형성시 층간절연막 상에 부식과 상반되는 구리 잔여물(Residue)이 남게되어 구리배선의 결함(Shortage)을 발생시킨다. In general, the dummy pattern is formed in a quadrangular or deformed cross shape so as to maintain a constant distance from the copper wiring. However, when the metal wiring is formed, copper residues, which are opposite to corrosion, are left on the interlayer insulating film so that the defect of the copper wiring ( Shortage).

특히, 구리배선의 CMP 공정은 대부분이 두 단계로 나누어지는데, 1단계는 베리어 금속막이 노출되도록 배선 금속막을 제거하며, 2단계는 층간절연막이 노출되도록 베리어 금속막을 제거한다. 그러나, 1단계에서 배선 금속막과 베리어 금속막 간의 식각 선택비가 높은 슬러리(Slurry)를 사용히여 제거하므로, 대부분 배선 금속막이 제거되고, 베리어 금속막은 남게되며, 부분적으로 배선 금속막이 남아있어 2단계에서 잔류된 배선 금속막이 제거되지 못하면 금속 배선에 불량이 발생하게 된다. In particular, the CMP process of the copper wiring is mostly divided into two stages. The first step removes the wiring metal film to expose the barrier metal film, and the second step removes the barrier metal film to expose the interlayer insulating film. However, in the first step, since a slurry having a high etching selectivity between the wiring metal film and the barrier metal film is removed by using a slurry, most of the wiring metal film is removed, the barrier metal film remains, and the wiring metal film remains partially, so in the second step If the remaining wiring metal film is not removed, a defect occurs in the metal wiring.

도 1은 종래 반도체 소자의 금속배선 형성방법의 문제점을 설명하기 위한 공정 단면도로서, 반도체 기판(1) 상에 하부 금속배선(3) 사이에 더미 패턴(4)이 형성되어 있으나, 상부 금속배선(7) 사이에 더미 패턴이 형성되어 있지 않으므로, 층간절연막(6) 상에 배선 금속막의 잔여물(A)이 남게되어 금속배선에 불량이 발생하게 되어 소자의 수율에 영향을 주게되는 문제점이 있다. 여기에서, 도면부호 2와 5는 층간절연막을 나타낸다.1 is a cross-sectional view illustrating a problem of a method of forming a metal wiring of a semiconductor device according to the related art. Although a dummy pattern 4 is formed between a lower metal wiring 3 on a semiconductor substrate 1, an upper metal wiring ( Since the dummy pattern is not formed between the layers, the residue A of the wiring metal film remains on the interlayer insulating film 6, thereby causing a defect in the metal wiring, thereby affecting the yield of the device. Here, reference numerals 2 and 5 denote interlayer insulating films.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 금속배선 형성시 발생하는 구리 잔여물을 제거하여 금속배선 간의 결함을 방지할 수 있는 반도체 소자의 금속배선 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, to provide a method for forming a metal wiring of the semiconductor device that can prevent the defects between the metal wiring by removing the copper residue generated when forming the metal wiring. There is this.

상기 목적을 달성하기 위한 본 발명은, 하부 금속배선이 형성된 반도체 기판을 제공하는 단계; 상기 하부 금속배선을 덮도록 기판 상에 층간절연막을 형성하는 단계; 상기 층간절연막을 식각하여 하부 금속배선을 노출시키는 콘택홀을 포함한 상부 금속배선 형성 영역을 한정하는 트렌치를 형성하는 단계; 상기 콘택홀을 포함한 트렌치를 매립하도록 층간절연막 상에 확산베리어막과 배선용 금속막을 차례로 증착하는 단계; 상기 확산베리어막이 노출되도록 배선용 금속막을 1차로 CMP하는 단계; 및 상기 층간절연막이 노출되도록 확산베리어막을 2차로 CMP하여 상부 금속배선을 형성하는 단계를 포함하며, 상기 트렌치를 형성하는 단계시 상부 금속배선 형성 영역들 사이에 더미 트렌치들을 형성하여, 상기 배선용 금속막 CMP시 금속 잔여물 발생을 방지시키는 더미 패턴이 형성되도록 하는 것을 특징으로 한다.The present invention for achieving the above object, providing a semiconductor substrate formed with a lower metal wiring; Forming an interlayer insulating film on the substrate to cover the lower metal wiring; Etching the interlayer insulating layer to form a trench defining an upper metal wiring forming region including a contact hole exposing a lower metal wiring; Sequentially depositing a diffusion barrier film and a wiring metal film on the interlayer insulating film so as to fill the trench including the contact hole; CMPing the wiring metal film primarily so that the diffusion barrier film is exposed; And forming an upper metal wiring by secondly CMPing the diffusion barrier film so that the interlayer insulating film is exposed, and forming dummy trenches between the upper metal wiring formation regions during the forming of the trench, wherein the metal film for wiring is formed. It is characterized in that to form a dummy pattern to prevent the generation of metal residues during CMP.

여기에서, 상기 하부 금속배선의 폭은 1㎛ 이상으로 형성하는 것을 특징으로 한다.Here, the width of the lower metal wiring is characterized in that formed to 1㎛ or more.

상기 상부 금속배선의 폭은 50㎛ 이상으로 형성하는 것을 특징으로 한다.The width of the upper metal wiring is characterized in that formed to 50㎛ or more.

상기 더미패턴은 상부 금속배선과 50㎛ 이하의 간격을 유지하도록 형성하는 것을 특징으로 한다.The dummy pattern may be formed to maintain an interval of 50 μm or less with the upper metal wiring.

(실시예)(Example)

이하, 본 발명의 바람직한 실시예에 대해 첨부된 도면을 참조하여 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 2c는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도이다.2A through 2C are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.

도 2a에 도시된 바와 같이, 하부 금속배선(23)이 형성된 반도체 기판(21)을 제공한다. 그 다음, 상기 하부 금속배선(23)을 덮도록 기판 상에 층간절연막(25)을 형성한 후에 상기 층간절연막(25)을 식각하여 하부 금속배선(23)을 노출시키는 콘택홀(26)을 형성한다. 이어서, 상기 층간절연막(25)을 식각하여 상부 금속배선 형성 영역을 한정하는 트렌치(27a)를 형성함과 동시에 상부 금속배선 형성 영역들 사 이에 더미 트렌치들(27b)을 형성한다. 여기에서, 도면부호 22는 층간절연막을, 24는 더미패턴을 나타낸다.As shown in FIG. 2A, a semiconductor substrate 21 having a lower metal wiring 23 is provided. Next, after forming the interlayer insulating film 25 on the substrate to cover the lower metal wiring 23, the interlayer insulating film 25 is etched to form the contact hole 26 exposing the lower metal wiring 23. do. Subsequently, the interlayer insulating layer 25 is etched to form trenches 27a defining the upper metal wiring forming regions, and at the same time, dummy trenches 27b are formed between the upper metal wiring forming regions. Here, reference numeral 22 denotes an interlayer insulating film and 24 denotes a dummy pattern.

도 2b에 도시된 바와 같이, 상기 콘택홀(26)을 포함한 트렌치(27a) 및 더미 트렌치들(27b)을 매립하도록 층간절연막(25) 상에 확산베리어막(28)과 배선용 금속막(29)을 차례로 증착한다. 여기에서, 상기 배선용 금속막(29)은 구리(Cu), 텅스텐(W), 백금(Pt)으로 구성된 그룹으로부터 선택되는 어느 하나로 형성한다. 그 다음, 상기 확산베리어막(28)이 노출되도록 배선용 금속막(29)을 CMP한다.As shown in FIG. 2B, the diffusion barrier layer 28 and the wiring metal layer 29 are disposed on the interlayer insulating layer 25 to fill the trench 27a and the dummy trenches 27b including the contact hole 26. In order to deposit. Here, the wiring metal film 29 is formed of any one selected from the group consisting of copper (Cu), tungsten (W), and platinum (Pt). Next, the wiring metal film 29 is CMP so that the diffusion barrier film 28 is exposed.

도 2c에 도시된 바와 같이, 상기 층간절연막(25)이 노출되도록 확산베리어막(28)을 CMP하여 상부 금속배선(30)을 형성함과 동시에 더미 패턴(31)을 형성한다. 이때, 상기 상부 금속배선(30)의 폭은 50㎛ 이상으로 형성하며, 상기 더미 패턴(31)은 상부 금속배선(30)과 50㎛ 이하의 간격을 유지하도록 형성한다. 여기에서, 상기 더미패턴(31)의 밀도는 패턴 밀도의 50％를 넘지 않아야 한다.As illustrated in FIG. 2C, the diffusion barrier layer 28 is CMP so that the interlayer insulating layer 25 is exposed to form the upper metal wiring 30 and the dummy pattern 31. In this case, the width of the upper metal wiring 30 is formed to be 50 μm or more, and the dummy pattern 31 is formed to maintain a distance of 50 μm or less from the upper metal wiring 30. Here, the density of the dummy pattern 31 should not exceed 50% of the pattern density.

본 발명은 금속배선 형성시 층간절연막 상에 발생하는 금속 잔여물로 인해 금속배선에 불량이 발생하는 종래 공정과 달리, 상기 상부 금속배선들 사이에 더미 패턴들을 형성함으로써 금속배선 형성시 층간절연막 상에 발생하는 금속 잔여물이 더미패턴에서 발생하더라도 상부 금속배선에서는 금속 잔여물이 발생하지 않게 된다. According to the present invention, unlike the conventional process in which defects occur in the metal wiring due to metal residues generated on the interlayer insulating film when the metal wiring is formed, dummy patterns are formed between the upper metal wires to form the metal wiring on the interlayer insulating film. Even if the generated metal residue occurs in the dummy pattern, the metal residue does not occur in the upper metal wiring.

전술한 바와 같이, 본 발명에서는 하부 금속배선들 사이에 더미 패턴들이 형성된 경우에 하부 금속배선들 사이에 더미 패턴들이 형성된 위치와 동일하게 상부 금속배선들 사이에 더미 패턴들을 형성하는 것에 대해 설명하였으나, 하부 금속배 선들 사이에 더미 패턴들이 형성되어 있고, 상부 금속배선들 사이에 더미 패턴들이 형성되어 있지 않은 경우에는 상부 금속배선들의 폭은 1㎛ 이상 되어야 하며, 상부 금속배선의 밀도는 패턴 밀도의 50％를 넘지 않아야 한다. As described above, in the present invention, when the dummy patterns are formed between the lower metal wires, the dummy patterns are formed between the upper metal wires in the same position as the dummy patterns are formed between the lower metal wires. When the dummy patterns are formed between the lower metal interconnections and the dummy patterns are not formed between the upper metal interconnections, the widths of the upper metal interconnections should be 1 μm or more, and the density of the upper metal interconnections is 50 times the pattern density. It should not exceed%.

이상, 본 발명은 몇 가지 예를 들어 설명하였으나, 본 발명은 이에 한정되는 것은 아니며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자라면 본 발명의 사상에서 벗어나지 않으면서 많은 수정과 변형을 가할 수 있음을 이해할 수 있을 것이다.In the above, the present invention has been described with reference to some examples, but the present invention is not limited thereto, and those skilled in the art may make many modifications and variations without departing from the spirit of the present invention. It will be appreciated.

이상에서와 같이, 본 발명에 의하면, 금속배선 형성시 하부 금속배선들 사이에 더미 패턴들이 형성된 경우에는 하부 금속배선에 더미 패턴들이 형성된 위치와 동일하게 상부 금속배선 사이에 더미 패턴들을 형성함으로써 금속배선 형성시 층간절연막 상에 발생하는 금속 잔여물이 더미 패턴들에서 발생하더라도 상부 금속배선에서는 금속 잔여물이 발생하지 않게 됨으로써 금속배선 간의 결함을 방지할 수 있다. 이로 인해, 소자의 수율을 향상시킬 수 있다.As described above, according to the present invention, in the case where the dummy patterns are formed between the lower metal wires when the metal wires are formed, the metal wires are formed by forming the dummy patterns between the upper metal wires in the same position as the dummy patterns are formed on the lower metal wires. When the metal residue generated on the interlayer insulating layer is formed in the dummy patterns, the metal residue does not occur in the upper metal interconnection, thereby preventing defects between the metal interconnections. For this reason, the yield of an element can be improved.

Claims (4)

하부 금속배선이 형성된 반도체 기판을 제공하는 단계; Providing a semiconductor substrate having a lower metal wiring formed thereon; 상기 하부 금속배선을 덮도록 기판 상에 층간절연막을 형성하는 단계; Forming an interlayer insulating film on the substrate to cover the lower metal wiring; 상기 층간절연막을 식각하여 하부 금속배선을 노출시키는 콘택홀을 포함한 상부 금속배선 형성 영역을 한정하는 트렌치를 형성하는 단계; Etching the interlayer insulating layer to form a trench defining an upper metal wiring forming region including a contact hole exposing a lower metal wiring; 상기 콘택홀을 포함한 트렌치를 매립하도록 층간절연막 상에 확산베리어막과 배선용 금속막을 차례로 증착하는 단계; Sequentially depositing a diffusion barrier film and a wiring metal film on the interlayer insulating film so as to fill the trench including the contact hole; 상기 확산베리어막이 노출되도록 배선용 금속막을 1차로 CMP하는 단계; 및 CMPing the wiring metal film primarily so that the diffusion barrier film is exposed; And 상기 층간절연막이 노출되도록 확산베리어막을 2차로 CMP하여 상부 금속배선을 형성하는 단계를 포함하며, CMPing the diffusion barrier layer so as to expose the interlayer insulating layer to form an upper metal wiring; 상기 트렌치를 형성하는 단계시 상부 금속배선 형성 영역들 사이에 더미 트렌치들을 형성하여, 상기 배선용 금속막 CMP시 금속 잔여물 발생을 방지시키는 더미 패턴이 형성되도록 하는 것을 특징으로 하는 반도체 소자의 다층금속배선 형성방법. Forming a plurality of dummy trenches between the upper metal wiring forming regions during the forming of the trench, so that a dummy pattern is formed to prevent metal residues from occurring during the CMP of the wiring metal layer; Formation method. 제 1 항에 있어서, 상기 하부 금속배선의 폭은 1㎛ 이상으로 형성하는 것을 특징으로 하는 반도체 소자의 다층금속배선 형성방법. The method of claim 1, wherein the lower metal wiring has a width of 1 μm or more. 제 1 항에 있어서, 상기 상부 금속배선의 폭은 50㎛ 이상으로 형성하는 것을 특징으로 하는 반도체 소자의 다층금속배선 형성방법.The method of claim 1, wherein the upper metal wiring has a width of 50 µm or more. 제 1 항에 있어서, 상기 더미패턴은 상부 금속배선과 50㎛ 이하의 간격을 유지하도록 형성하는 것을 특징으로 하는 반도체 소자의 다층금속배선 형성방법.The method of claim 1, wherein the dummy pattern is formed to maintain an interval of 50 μm or less from an upper metal wiring.
KR1020040056736A 2004-07-21 2004-07-21 Method for forming metal interconnection line of semiconductor device KR20060009420A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7531449B2 (en) 2006-11-10 2009-05-12 Samsung Electronics Co., Ltd. Method of forming fine patterns using double patterning process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7531449B2 (en) 2006-11-10 2009-05-12 Samsung Electronics Co., Ltd. Method of forming fine patterns using double patterning process

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