KR20060008588A - Flash memory device and read method thereof - Google Patents

Abstract

A flash memory device according to the present invention includes a memory cell array including a plurality of pages; The memory cell array comprises first and second data storage regions; Each of the first and second data storage regions includes a plurality of strings each comprising a plurality of memory cells; The memory cells of each row of the memory cells of each of the first and second data storage regions constitute a page, and at least two memory cells of each of the strings of the second data storage region may correspond to a corresponding page. Programmed to store information; A page select circuit for selecting pages of the memory cell array in response to a row address, the page select circuit including latches corresponding to each of the pages.

Description

Flash memory device and its reading method {FLASH MEMORY DEVICE AND READ METHOD THEREOF}

1 is a view showing an array structure for explaining a method of reading page information stored in a spare area of a flash memory device according to the prior art;

2 shows schematically a flash memory device according to the invention; And

3 is a diagram illustrating an array structure for explaining a method of reading page information stored in a spare area of a flash memory device according to the present invention.

Explanation of symbols on the main parts of the drawings

1, 110: memory cell array 120: switch circuit

130: page decoder circuit 140: block decoder circuit

20, 150: page buffer circuit

The present invention relates to a semiconductor memory device, and more particularly, to a flash memory device for storing information indicating whether pages of a memory block have been programmed.

Semiconductor memories are generally the most essential microelectronic devices of digital logic designs, such as computers and applications based on microprocessors, which range from satellite to consumer electronics technology. Therefore, advances in the manufacturing technology of semiconductor memories, including process improvement and technology development, achieved through scaling for high integration and high speed, help to establish performance criteria for other digital logic families.

The semiconductor memory device is largely divided into a volatile semiconductor memory device and a nonvolatile semiconductor memory device. In a volatile semiconductor memory device, logic information is stored by setting a logic state of a bistable flip-flop in the case of static random access memory or through charging of a capacitor in the case of dynamic random access memory. In the case of a volatile semiconductor memory device, data is stored and read while power is applied, and data is lost when power is cut off.

Nonvolatile semiconductor memory devices such as MROM, PROM, EPROM, and EEPROM can store data even when the power is cut off. The nonvolatile memory data storage state is either permanent or reprogrammable, depending on the manufacturing technique used. Nonvolatile semiconductor memory devices are used for the storage of programs and microcode in a wide range of applications such as the computer, avionics, telecommunications, and consumer electronics industries. The combination of volatile and nonvolatile memory storage modes on a single chip is also available in devices such as nonvolatile RAM (nvRAM) in systems that require fast and reprogrammable nonvolatile memory. In addition, specific memory structures have been developed that include some additional logic circuitry to optimize performance for application-oriented tasks.

In the nonvolatile semiconductor memory device, the MROM, PROM and EPROM are not free to erase and write in the system itself, so that it is not easy for ordinary users to update the storage contents. On the other hand, since EEPROMs can be electrically erased and written, applications to system programming or auxiliary storage devices requiring continuous updating are expanding. In particular, the flash EEPROM (hereinafter referred to as flash memory) has a high degree of integration compared to the conventional EEPROM, which is very advantageous for application to a large capacity auxiliary storage device. Among flash memories, NAND-type flash memory has a higher density than NOR flash memory.

The NAND flash memory includes a memory cell array as a storage area for storing information, and the memory cell array is composed of a plurality of cell strings (or called NAND strings). Flash memory is provided with a page buffer circuit to store data in or read data from the memory cell array. As is well known, memory cells of a NAND flash memory are erased and programmed using F-Nordheim tunneling current. Erasing and programming methods of NAND flash EEPROM are described in US. Patent No. 5,473,563 entitled "Nonvolatile Semiconductor Memory," US. Patent No. 5,696,717, entitled "Nonvolatile Integrated Circuit Memory Devices Having Adjustable Erase / Program Threshold Voltage Verification Capability," respectively.

A diagram showing an array structure of a flash memory is shown in FIG. Referring to FIG. 1, the memory cell array 1 is divided into a main area and a spare area. Although the main and spare regions associated with only one memory block are shown in FIG. 1, it is apparent to those skilled in the art that more memory blocks are provided in the memory cell array 1. The main region includes a plurality of cell strings (or NAND strings) 10 respectively corresponding to the bit lines BL0 -BLn. Each cell string 10 includes a plurality of flash EEPROM cells connected in series between a string select transistor SST as a first select transistor, a ground select transistor GST as a second select transistor, and the select transistors SST and GST. It consists of (Mm). The string select transistor SST has a drain connected to the corresponding bit line and a gate connected to the string select line SSL, and the ground select transistor GST has a source and ground select line GSL connected to the common source line CSL. Has a gate connected to it. Flash EEPROM cells M0-Mm are connected in series between the source of the string select transistor SST and the drain of the ground select transistor GSL, and the cells M0-Mm are connected to the corresponding word lines WL0-WLm. Each is connected. As can be seen in Figure 1, the spare area is provided with a plurality of cell strings having the same structure as the main area. The cell strings of the spare area are connected to the corresponding spare bit lines SBL0-SBLx, respectively. The bit lines BL0-BLn and SBL0-SBLx are connected to the page buffer circuit 20. As is well known, the page buffer circuit 20 operates as a sense amplifier in read / verify operation and as a driver in program operation.

In order to store data in the main area of the memory cell array, first, a data loading command is given to the flash memory device, and an address and data are continuously input to the flash memory device. In general, the data to be programmed is sequentially delivered to the page buffer circuit 20 in bytes or words. When the data to be programmed, i.e., one page amount of data, is all loaded into the page buffer circuit 20, the data stored in the page buffer circuit 20 is stored according to the program command in the main area of the memory cell array (i.e. Memory cells belonging to the page). After all the memory cells of the selected page have been programmed, information indicating that data has been correctly stored in the memory cells of the selected page is programmed again in a specific area (eg, a spare area) of the memory cell array.

Information indicating that the selected page has been programmed or that data has been correctly stored in the memory cells of the selected page (hereinafter referred to as page information) (or referred to as a confirmation mark) is generally placed in any column of the spare area. It is programmed into the string to which it belongs. For example, page information of each of the pages WL0-WLm is stored in corresponding memory cells (memory cells indicated by dotted lines in FIG. 1) of a cell string connected to the spare bit line SBL0. That is, the WL0 page information is stored in the memory cell M0 of the cell string connected to the spare bit line SBL0, and the WL1 page information is stored in the memory cell M1 of the cell string connected to the spare bit line SBL0. The WLm page information is stored in the memory cell Mm of the cell string connected to the spare bit line SBL0.

When the page information is stored in the above-described manner, there is a disadvantage in that the time required to read the page information stored in the spare area is long. Because page information is stored in one cell string, a read operation is required as many as the number of pages of a memory block to read page information of each page. As a result, as the number of pages of a memory block increases, the time required to read page information stored in the spare area becomes longer.

SUMMARY OF THE INVENTION An object of the present invention is to provide a flash memory device capable of reducing the time required to read page information stored in a spare area and a method of reading the same.

According to an aspect of the present invention for achieving the above object, a flash memory device includes a memory cell array including a plurality of pages; The memory cell array comprises first and second data storage regions; Each of the first and second data storage regions includes a plurality of strings each comprising a plurality of memory cells; The memory cells of each row of the memory cells of each of the first and second data storage regions constitute a page, and at least two memory cells of each of the strings of the second data storage region may correspond to a corresponding page. Programmed to store information; A page select circuit for selecting pages of the memory cell array in response to a row address, the page select circuit including latches corresponding to each of the pages.

In this embodiment, after the page selection information corresponding to the latches is stored, the selected pages are activated at the same time so that the information of the pages stored in the second data storage area is read at the same time.

In this embodiment, the first data storage area is a main area, and the second data storage area is a spare area.

According to another aspect of the present invention, a method of reading a flash memory device including a memory cell array having a plurality of pages may include sequentially storing row addresses input to latches to select all or part of the pages. Wow; After input of the row addresses is completed, simultaneously activating corresponding pages in response to the output of the latches in which the row addresses are stored; And simultaneously reading information related to the pages of the memory cell array from the spare area of the memory cell array.

In this embodiment, the information related to each page is stored at the same value in two or more memory cells per string of the spare area.

Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

2 is a block diagram schematically illustrating a flash memory device according to the present invention.

Referring to FIG. 2, the flash memory device 100 of the present invention includes a memory block 110, and the memory block 110 is configured substantially the same as that shown in FIG. 1. Therefore, the description of the memory block shown in FIG. 2 is therefore omitted. The string select line SSL, the ground select line GSL, and the word lines WL0-WLm are connected to the page decoder circuit 130 through the switch circuit 120. The switch circuit 120 includes pass transistors PT0-PT4 corresponding to the string select line SSL, the ground select line GSL, and the word lines WL0-WLm, respectively, and the pass transistors PT0. PT4) is commonly controlled by the block select signal BLK output from the block decoder circuit 140. The block decoder circuit 140 activates the block select signal BLK and the select signals SS and GS in response to the block address for selecting the memory block 110.

The page decoder circuit 130 according to the present invention selects the word lines WL0-WLm of the memory block 110 and drives the selected word line to the word line voltage required for the operation mode. In particular, the page decoder circuit 130 according to the present invention includes latches LAT0-LATm for latching the selection signals S0-Sm, and each of the latches LAT0-LATm has a corresponding selection signal. Latch.

In the flash memory device 100 according to the present invention, when reading page information stored in a spare area, latches of the page decoder circuit 130 include address information of a page to be selected so that a plurality of word lines are selected at the same time. Each is stored. In order to perform a read operation of the flash memory device, as is well known, a first command (eg, 00h) indicating a read operation is input, and then column and row addresses are input to the flash memory device at a predetermined timing. When the address input is completed, a second command (e.g., 30h) for initiating the read operation is input to the flash memory device. At this time, a read operation is performed. In contrast, in the flash memory device of the present invention, in order to read page information stored in the spare area, a command and address information indicating a read operation are repeatedly input to the flash memory device by the number of pages to be selected. Page selection information among the inputted address information is stored in the corresponding latch.

For example, the page selection information entered in the first cycle is stored in the latch (LAT0), the page selection information entered in the second cycle is stored in the latch (LATm-1), and the page selection entered in the third cycle. The information is stored in the latch LATm. After all of the address information of the pages to be selected are stored in the page decoder circuit 130, the selected word lines are simultaneously selected as a command for informing the start of a read operation is input. Word lines that are not selected will be driven to a voltage that is set according to the mode of operation (eg, a voltage that can sufficiently turn on the programmed cell during a read operation).

3 is a diagram illustrating an array structure for explaining a method of reading page information stored in a spare area of a flash memory device according to the present invention. The method of reading page information according to the present invention will be described in detail below on the basis of the reference figures. In a flash memory device according to the present invention, page information of pages of a memory block is stored in one column, that is, corresponding strings, respectively. For example, referring to FIG. 3, page information of whether the page WL0 is correctly programmed may include at least two memory cells (eg, M0 indicated by a dotted line) among memory cells of a string connected to the spare bit line SBL0. Programmed in M1). This means that information about one page is stored in all or some of the memory cells of one string. The operation of reading page information under such conditions will be described in detail below.

In order to read the page information stored in the spare area, first, a first command for informing a read operation (eg, 00h) is input, and then column and row addresses are input to the flash memory device at a predetermined timing. The page address of the input row address is stored in the corresponding latch of the page decoder circuit 130. This command and address input process will be repeated as many times as the number of pages to be selected. Assuming two word lines WL0 and WL1 are simultaneously activated, for example, the page selection information input in the first cycle is stored in the latch LAT0, and the page selection information input in the second cycle is latched. Stored in LAT1.

After all of the address information of the pages to be selected are stored in the page decoder circuit 130, the selected word lines WL0 and WL1 are simultaneously selected as a command for initiating a read operation is input. Word lines that are not selected will be driven to a voltage that is set according to the mode of operation (eg, a voltage that can sufficiently turn on the programmed cell during a read operation). As the selected word lines are activated, page information stored in memory cells of a spare area connected to the selected word lines is simultaneously read by the page buffer circuit 150.

It is apparent to those skilled in the art that the number of word lines to be selected at the same time may vary. For example, as in a normal read operation, only one word line may be selected. Even in this case, the page information will be read at the same time. In addition, all word lines may be activated at the same time. In the above, the configuration and operation of the circuit according to the present invention has been shown in accordance with the above description and drawings, but this is only an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.

As described above, by implementing the page decoder circuit to simultaneously read the page information stored in the spare area, the time required for the read operation of the spare area can be shortened.

Claims (5)

A memory cell array including a plurality of pages; The memory cell array comprises first and second data storage regions; Each of the first and second data storage regions includes a plurality of strings each comprising a plurality of memory cells; The memory cells of each row of the memory cells of each of the first and second data storage regions constitute a page, and at least two memory cells of each of the strings of the second data storage region may correspond to a corresponding page. Programmed to store information; And a page selection circuit for selecting pages of the memory cell array in response to a row address, the page selection circuit including latches corresponding to each of the pages. The method of claim 2, And after page selection information corresponding to the latches is stored, pages selected to simultaneously read information of the pages stored in a second data storage area are simultaneously activated. The method of claim 1, And the first data storage area is a main area and the second data storage area is a spare area. A method of reading a flash memory device including a memory cell array having a plurality of pages, the method comprising: Sequentially storing the row addresses that are input to select all or part of the pages in latches; After input of the row addresses is completed, simultaneously activating corresponding pages in response to the output of the latches in which the row addresses are stored; And And simultaneously reading information related to the pages of the memory cell array from the spare area of the memory cell array. The method of claim 4, wherein And the information related to each page is stored at the same value in two or more memory cells per string of the spare area.

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