KR20060008031A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR20060008031A KR20060008031A KR1020040057684A KR20040057684A KR20060008031A KR 20060008031 A KR20060008031 A KR 20060008031A KR 1020040057684 A KR1020040057684 A KR 1020040057684A KR 20040057684 A KR20040057684 A KR 20040057684A KR 20060008031 A KR20060008031 A KR 20060008031A
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- oxide film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로서, 필드산화막 형성시의 필드산화막 증착을 위한 CVD 공정시 실리콘 소스 가스 공급관의 첨담에 펄스 밸브를 연결해서 상기 필드산화막의 증착 및 에치를 연속적으로 실시하여 필드산화막의 오버행에 의한 보이드 발생을 방지하므로, 후속 공정에서의 불량발생을 방지하여 공정수율 및 소자의 동작 특성을 향상시킬 수 있다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein a field is formed by connecting a pulse valve to an attachment of a silicon source gas supply pipe during a CVD process for depositing a field oxide film when forming a field oxide film, and continuously performing deposition and etching of the field oxide film. Since the generation of voids due to the overhang of the oxide film is prevented, it is possible to prevent the occurrence of defects in the subsequent process to improve the process yield and the operation characteristics of the device.
Description
도 1은 종래 기술에 따른 반도체소자의 평면 SEM 사진. 1 is a planar SEM photograph of a semiconductor device according to the prior art.
도 2는 본 발명에 따른 반도체소자 제조에 사용되는 필드산화막 증착 장비를 도시한 도면. Figure 2 is a view showing the field oxide film deposition equipment used for manufacturing a semiconductor device according to the present invention.
도 3은 트링거 펄스(tringger pulse)의 주기를 도시한 도면. 3 shows the period of a tringger pulse.
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 고밀도 소자의 얕은 트렌치 소자분리(shallow trench isolation; 이하 STI라 칭함) 공정에서 소자분리산화막 형성 공정시의 실리콘 공급 가스의 밸브에 스위칭 밸브를 장치하여 증착-에칭 공정이 반복되도록하여 STI 공정에서의 보이드 발생을 방지하고 트렌치를 원활하게 메울 수 있는 반도체소자의 제조방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a switching valve is provided to a valve of a silicon supply gas during a device isolation oxide film formation process in a shallow trench isolation (STI) process of a high density device. The present invention relates to a method of fabricating a semiconductor device capable of repeating the deposition-etching process to prevent voids in the STI process and to smoothly fill the trenches.
일반적으로 반도체소자는 소자가 형성되는 활성영역과, 이들을 분리하는 소자분리 영역으로 구분할 수 있으며, 소자분리영역이 소자의 전체 면적에서 차지하는 비율이 크므로 소자의 고집적화를 위해서는 소자분리영역의 축소가 필요하다. In general, semiconductor devices can be divided into active regions in which devices are formed and device isolation regions separating them, and since the device isolation region occupies a large portion of the entire area of the device, it is necessary to reduce the device isolation region for high integration. Do.
고집적 소자에서는 기판에 얕은 트렌치를 형성하고 이를 절연막으로 메우는 STI 방법이 많이 사용되고 있다. In high-density devices, many STI methods that form a shallow trench in a substrate and fill it with an insulating film are widely used.
도시되어 있지는 않으나, 종래 기술에 따른 반도체소자의 제조방법으로 살펴보면 다음과 같다. Although not shown, it will be described with reference to a method of manufacturing a semiconductor device according to the prior art.
먼저, 반도체기판상에 패드산화막과 질화막을 형성하고, 소자분리 마스크로 패터닝하여 반도체기판에서 소자분리 영역으로 예정되어있는 부분을 노출시키는 패드질화막 패턴과 패드산화막 패턴을 형성한다. First, a pad oxide film and a nitride film are formed on a semiconductor substrate, and patterned with an isolation mask to form a pad nitride film pattern and a pad oxide film pattern exposing a portion of the semiconductor substrate, which is intended as an isolation region.
그다음 상기 질화막 패턴에 의해 노출되어있는 반도체기판을 일정 깊이 식각하여 트렌치를 형성하고, 상기 구조의 전표면에 필드산화막을 도포하여 트렌치를 메우고, 상기 필드산화막의 상부를 화학-기계적 연마(chemical mechanical polishing ; 이하 CMP라 칭함) 등의 방법으로 식각하여 평탄화시킨 후, 상기 패드질화막과 패드산화막을 제거한다. 여기서 상기 필드산화막은 비활성 가스인 He 및 Rf를 이용한 플라즈마 발생 상태에서 일정시간 동안 SiH4 가스 60sccm, O2 75sccm을 주입하여 형성한다. Then, the semiconductor substrate exposed by the nitride film pattern is etched to a certain depth to form a trench, a field oxide film is applied to the entire surface of the structure to fill the trench, and the upper portion of the field oxide film is chemical-mechanical polishing. After etching and planarization by a method such as CMP), the pad nitride film and the pad oxide film are removed. Here, the field oxide film is formed by injecting 60 sccm of SiH4 gas and 75 sccm of O2 for a predetermined time in a plasma generation state using He and Rf as inert gases.
그러나, 상기와 같은 종래 기술에 따른 반도체 소자의 제조방법은 90㎚ 이하의 디자인룰을 가지는 고집적 소자에 사용되는 STI 공정에서는 상기 트렌치를 3000Å 이상의 깊이로 형성하고, 필드산화막 도포는 2000Å/분 정도의 비율로 형성하므로, 가장 악조건의 갭필 간격이 약 80-90㎚ 정도가 되어, 70㎚ 이하의 간격은 메우기 어려워 도 1에서와 같은 보이드가 형성되어 후속 공정시 배선간 단락이나, 기판 손상등으로 공정수율 및 소자의 동작 특성을 저하시키는 문제점이 있다. However, in the method of manufacturing a semiconductor device according to the prior art as described above, in the STI process used in a highly integrated device having a design rule of 90 nm or less, the trench is formed to a depth of 3000 mV or more, and the field oxide film is applied at about 2000 mV / min. As the ratio is formed, the gap fill gap of the worst condition is about 80-90 nm, and the gap of 70 nm or less is difficult to fill and voids are formed as shown in FIG. There is a problem of lowering the yield and operating characteristics of the device.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 필드산화막 형성 공정시 실리콘 소스 가스 밸브의 첨단에 스위칭 밸브를 설치하여 필드산화막 증착 단계에서 증착과 식각이 반복되어 오버행에 의한 보이드 생성을 방지하여 공정수율 및 소자의 동작 특성을 향상시킬 수 있는 반도체소자의 제조방법을 제공함에 그 목적이 있다. Therefore, the present invention has been made to solve the above problems, by installing a switching valve on the tip of the silicon source gas valve during the field oxide film forming process, the deposition and etching is repeated in the field oxide film deposition step to generate voids due to overhang It is an object of the present invention to provide a method for manufacturing a semiconductor device that can improve the process yield and the operation characteristics of the device by preventing the.
상기와 같은 목적을 달성하기 위하여, 본 발명은, 반도체기판상에 패드산화막과 질화막을 순차적으로 형성하는 공정과, 상기 질화막과 패드산화막을 소자분리마스크를 이용한 패터닝 공정으로 선택 식각하여 반도체기판의 소자분리영역으로 예정되어있는 부분을 노출시키는 패드질화막 패턴을 형성하는 공정과, 상기 패드질화막에 의해 노출되어있는 반도체기판을 일정 두께 식각하여 트렌치를 형성하는 공정과, 상기 구조의 전표면에 필드산화막을 형성하되, 실리콘 소스 가스 공급관의 첨단에 펄스 밸브가 부착되어있는 증착 장비를 사용하여 필드산화막 형성 공정시 소정 주기로 실리콘 소스 가스를 온/오프시켜 필드산화막 증착과 에칭이 반복되도록하여 증착하는 공정을 포함하는 반도체소자의 제조방법을 제공한다. In order to achieve the above object, the present invention, by forming a pad oxide film and a nitride film sequentially on the semiconductor substrate, and selectively etching the nitride film and the pad oxide film by a patterning process using a device isolation mask device of the semiconductor substrate Forming a pad nitride film pattern exposing a predetermined portion as a separation region; forming a trench by etching a semiconductor substrate exposed by the pad nitride film by a predetermined thickness; and forming a field oxide film on the entire surface of the structure. Forming, but using the deposition equipment is attached to the tip of the silicon source gas supply pipe using the deposition equipment is a field oxide film forming process, the silicon oxide source gas is turned on and off at a predetermined cycle to repeat the field oxide film deposition and etching is repeated It provides a method for manufacturing a semiconductor device.
여기서, 상기 펄스 밸브는 펄스 주파수가 1-100kHz 이고, 증착-에치 공정의 비율은 증착 공정을 10-90% 진행하고, 주기는 수 msc-수초의 간격으로 실시하는 것을 특징으로 한다. Here, the pulse valve is characterized in that the pulse frequency is 1-100kHz, the ratio of the deposition-etch process proceeds 10-90% of the deposition process, the cycle is carried out at intervals of several msc-seconds.
(실시예)(Example)
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상게하게 설명 하도록 한다. Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
도 2는 본 발명에 따른 반도체소자의 제조 장치의 개략도로서, 필드산화막 제조를 위한 증착장치이다.2 is a schematic diagram of an apparatus for manufacturing a semiconductor device according to the present invention, which is a deposition apparatus for field oxide film production.
통상의 CVD 장비로서 챔버 내부의 테이블상에 웨리퍼가 탑재되고, 테이블에 연결된 Rf 파워가 플라즈마를 생성하며, O2, He 및 SiH4 의 소스 및 운반 가스 공급라인을 가지고 있고, 상기 실리콘 소스가스 공급장치에 펄스 밸브를 연결되어 있어, 필드산화막 형성공정시 펄스 파워 공급기가 도 3에서와 같은 펄스 신호를 입력시켜 일정 주기로 실리콘 소스 공급라인을 개폐시켜 실리콘 소스 가스를 개폐시켜 산화막 증착과 에치가 반복되어 산화막 증착과 에치백이 반복되어 STI 공정에서 트렌치 상부의 필드산화막에 오버행이 형성되는 것을 방지한다. As a conventional CVD equipment, a wafer is mounted on a table inside a chamber, an Rf power connected to the table generates a plasma, has a source and a carrier gas supply line of O 2, He, and SiH 4, and the silicon source gas supply device. In the field oxide film forming process, a pulse power supply inputs a pulse signal as shown in FIG. 3 to open and close the silicon source supply line at regular intervals, and to open and close the silicon source gas to repeat oxide film deposition and etching. Deposition and etch back are repeated to prevent overhangs in the field oxide layer over the trench in the STI process.
여기서, 펄스 밸브는 도 3에 도시된 바와 같이, 10kHz의 50% 증착공정을 나타내며, 펄스 주파수는 1-100kHz 이고, 증착-에치공정의 비율은 증착 공정 10-90% 까지 진행 할 수 있으며, 주기는 수 msc- 수초의 간격으로 실시한다. Here, the pulse valve represents a 50% deposition process of 10kHz, as shown in Figure 3, the pulse frequency is 1-100kHz, the ratio of the deposition-etch process can proceed to the deposition process 10-90%, period Is carried out at intervals of several msc- several seconds.
상기의 장비를 사용하여 소자분리 공정을 진행하면 다음과 같다. The device separation process using the above equipment is as follows.
먼저, 반도체기판상에 패드산화막과 질화막을 순차적으로 형성하고, 소자분리 마스크를 이용한 사진식각 공정으로 상기 질화막과 패드산화막을 패터닝하여 반도체기판에서 소자분리 영역으로 예정되어있는 부분을 노출시키는 질화막 패턴과 패드산화막 패턴을 형성한 후, 상기 질화막 패턴에 의해 노출되어있는 반도체기판을 일정 깊이 식각하여 트렌치를 형성한다. First, a nitride film pattern for sequentially forming a pad oxide film and a nitride film on a semiconductor substrate and patterning the nitride film and the pad oxide film by a photolithography process using a device isolation mask to expose a predetermined portion of the semiconductor substrate as a device isolation region; After forming the pad oxide film pattern, the semiconductor substrate exposed by the nitride film pattern is etched to a predetermined depth to form a trench.
그 다음 도 2의 장비를 이용하여 상기 구조의 전표면에 필드산화막을 도포하 여 트렌치를 메우고, 상기 필드산화막 상부를 CMP(chemical mechanical polishing) 등의 방법으로 식각하여 평탄화시킨 후, 상기 질화막과 패드산화막 패턴을 제거한다. Then, the field oxide film is applied to the entire surface of the structure by using the apparatus of FIG. 2 to fill the trenches, and the top of the field oxide film is etched and planarized by a chemical mechanical polishing (CMP) method, and then the nitride film and the pad are formed. The oxide film pattern is removed.
이상에서와 같이, 본 발명은 STI 공정에서 필드산화막 형성시에 실리콘 소스를 펄스 제너레이트시켜 산화막 증착과 식각을 반복하여 오버행이나 불량 발생을 방지하므로, 공정수율 및 소자의 동작 특성을 향상시킬 수 있다. As described above, the present invention pulse generation of the silicon source when forming the field oxide film in the STI process to prevent the occurrence of overhang or failure by repeating the oxide film deposition and etching, it is possible to improve the process yield and operation characteristics of the device .
이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100905278B1 (en) * | 2007-07-19 | 2009-06-29 | 주식회사 아이피에스 | Apparatus, method for depositing thin film on wafer and method for gap-filling trench using the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100905278B1 (en) * | 2007-07-19 | 2009-06-29 | 주식회사 아이피에스 | Apparatus, method for depositing thin film on wafer and method for gap-filling trench using the same |
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