KR20060008030A - Method for forming capacitor of semiconductor device - Google Patents

Method for forming capacitor of semiconductor device Download PDF

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KR20060008030A
KR20060008030A KR1020040057683A KR20040057683A KR20060008030A KR 20060008030 A KR20060008030 A KR 20060008030A KR 1020040057683 A KR1020040057683 A KR 1020040057683A KR 20040057683 A KR20040057683 A KR 20040057683A KR 20060008030 A KR20060008030 A KR 20060008030A
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film
forming
tin
capacitor
semiconductor device
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KR100631949B1 (en
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오재민
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02194—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing more than one metal element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD

Abstract

본 발명은 유전 물질로 HfxAlyOz를 적용한 반도체 소자의 캐패시터 형성방법을 개시한다. 개시된 본 발명에 따른 반도체 소자의 캐패시터 형성방법은, 하지층을 구비한 반도체기판 상에 TiN막을 증착하는 단계와, 상기 TiN막 Ru 박막을 증착하는 단계와, 상기 Ru 박막 상에 ALD 공정에 따라 HfxAlyOz의 유전막을 형성함과 아울러 상기 Ru막 표면에 산화막이 형성되는 것에 의해 TiN/Ru/RuO2의 하부전극을 형성하는 단계와, 그리고, 상기 HfxAlyOz의 유전막 상에 TiN/poly-Si의 상부전극을 형성하는 단계를 포함하는 것을 특징으로 한다. The present invention discloses a method for forming a capacitor of a semiconductor device applying Hf x Al y O z as a dielectric material. A method of forming a capacitor of a semiconductor device according to the present invention includes the steps of depositing a TiN film on a semiconductor substrate having an underlayer, depositing the TiN film Ru thin film, and Hf according to an ALD process on the Ru thin film. forming a dielectric film of x Al y O z and forming a lower electrode of TiN / Ru / RuO 2 by forming an oxide film on the surface of the Ru film, and on the dielectric film of Hf x Al y O z . And forming an upper electrode of TiN / poly-Si.

Description

반도체 소자의 캐패시터 형성방법{Method for forming capacitor of semiconductor device}Method for forming capacitor of semiconductor device

도 1은 종래 문제점을 설명하기 위한 단면도. 1 is a cross-sectional view for explaining a conventional problem.

도 2 내지 도 5는 본 발명에 따른 반도체 소자의 캐패시터 형성방법을 설명하기 위한 단면도.2 to 5 are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

21 : 반도체기판 22 : TiN막21 semiconductor substrate 22 TiN film

23 : Ru막 23a : RuO2막23: Ru film 23a: RuO 2 film

24 : 하부전극 25 : HfxAlyOz 유전막24: lower electrode 25: Hf x Al y O z dielectric film

26a : TiN막 26b : poly-Si막26a: TiN film 26b: poly-Si film

27 : 상부전극 30 : 캐패시터27: upper electrode 30: capacitor

본 발명은 반도체 소자의 캐패시터 형성방법에 관한 것으로, 특히, 유전 물질로 HfxAlyOz를 적용한 반도체 소자의 캐패시터 형성방법에 관한 것이다. The present invention relates to a method of forming a capacitor of a semiconductor device, and more particularly, to a method of forming a capacitor of a semiconductor device in which Hf x Al y O z is applied as a dielectric material.

반도체 소자가 미세화됨에 따라, 캐패시터의 충전용량(Cs)을 확보하는 문제가 디램 소자를 개발하는 공정에서 핵심적인 사항중의 하나로 부상하고 있다. 특히, ㎚급의 소자로 축소됨에 따라 기존의 캐패시터는 충전용량을 확보하기 위한 방법으로 전극 표면적을 넓히는 방법을 이용하여 왔고, 상기 전극 표면적을 넓히는 하나의 방법으로 캐패시터 높이를 높이는 방법을 주로 이용하여 왔는데, 캐패시터의 높이를 높이면, 메탈1콘택(M1C) 높이가 높아져 포토 및 식각 공정의 마진이 급속히 감소하게 되고, 아울러, 캐패시터 형성시 많은 결함(defect)이 발생되어 수율 감소가 초래된다. As semiconductor devices are miniaturized, the problem of securing the capacitor's charge capacity (Cs) has emerged as one of the key issues in the process of developing DRAM devices. In particular, as it is reduced to the ㎚-class device, the conventional capacitor has been using a method of increasing the electrode surface area as a method for securing the charging capacity, and mainly using a method of increasing the capacitor height as a method of increasing the electrode surface area. As the height of the capacitor increases, the height of the metal 1 contact M1C increases, and the margin of the photo and etching process is rapidly reduced, and a large number of defects are generated when the capacitor is formed, resulting in a decrease in yield.

따라서, 이에 대한 해결책으로서 고유전(high k) 물질을 적용하려는 많은 연구가 진행되고 있다. 최근의 디램 소자는 유전물질로 기존의 ONO막에서 ALD(Atomic Layer Deposition) 공정에 의한 Al2O3(k=9), 그리고, ALD 공정에 의한 HfO2(k=25)를 이용하기에 이르렀다. 이에 따라 캐패시터 구조 또한 기존 SIS(Silicon-Insulator-Silicon) 구조에서 MIM(Metal-Insulator-Metal) 구조로 변화되어 기생 캐패시터의 감소를 통해 충전용량(Cs)을 확보하는 방향으로 공정이 개발되고 있다. Therefore, a lot of researches are going on to apply high k material as a solution. Recently, DRAM devices have used Al 2 O 3 (k = 9) by ALD (Atomic Layer Deposition) process and HfO 2 (k = 25) by ALD process. . Accordingly, the capacitor structure is also changed from a conventional silicon-insulator-silicon (SIS) structure to a metal-insulator-metal (MIM) structure, and a process is being developed in order to secure a charging capacity (Cs) by reducing parasitic capacitors.

한편, 유전 물질로 HfO2를 적용함에 있어서, 상기 HfO2는 낮은 결정화 온도를 가지며, 또한, 두께가 증가함에 따라 결정화가 진행되므로써, 누설전류를 증가시키는 단점이 있다. 이에, 현재는 HfO2를 단독으로는 이용하지 않고 비결정성이 높아 누설전류가 작은 Al2O3를 적용하여 Al2O3/HfO2/Al 2O3의 적층 구조로 공정을 개발하고 있다.On the other hand, in the application of HfO 2 as a dielectric material, the HfO 2 has a low crystallization temperature, and also has a disadvantage of increasing the leakage current by the crystallization proceeds as the thickness increases. As a result, the present invention is developing a process using a laminated structure of Al 2 O 3 / HfO 2 / Al 2 O 3 by applying Al 2 O 3 , which does not use HfO 2 alone but has a high crystallinity and low leakage current.

그런데, 이 방법은 유전상수가 상대적으로 작은 Al2O3를 적층하여 이용하기 때문에 충전용량의 감소를 감수해야 한다. 또한, Al2O3/HfO2/Al2 O3 적층 구조의 유전막은 고온에서의 열적 안정성이 취약하여, 고온 공정이 진행될 경우, 많은 누설전류를 발생시키는 단점이 있다. However, since this method uses a stack of relatively small dielectric constants of Al 2 O 3 , the charging capacity must be reduced. In addition, the dielectric film of the Al 2 O 3 / HfO 2 / Al 2 O 3 laminated structure has a weak thermal stability at high temperature, there is a disadvantage that generates a large leakage current when the high temperature process proceeds.

이에, 최근에는 TMA(Al 소오스)와 TEMAH(Hf 소오스)를 이용하여 300℃ 이하의 ALD(Atomic Layer Deposition) 공정에 의한 HfxAlyOz 박막을 캐패시터 유전막으로 적용하려는 연구가 시도되고 있다. 이러한 ALD HfxAlyOz 박막은 높은 비정질 특성을 갖는 것으로 인해 누설전류가 작으며, 또한, 유전상수가 HfO2와 거의 유사하고, 게다가, 고온에서의 열적 안정성이 우수하다.Recently, a research has been attempted to apply a Hf x Al y O z thin film by a ALD (Atomic Layer Deposition) process below 300 ° C using TMA (Al source) and TEMAH (Hf source) as a capacitor dielectric film. The ALD Hf x Al y O z thin film has a low leakage current due to its high amorphous characteristics, and also has a dielectric constant similar to that of HfO 2, and also has excellent thermal stability at high temperatures.

그러나, 상기 ALD HfxAlyOz 박막은 막내에 탄소(C) 및 질소(N) 등의 불순물이 다량으로 함유되어 있기 때문에, 그 증착 후에 고온의 O2 분위기로 열처리하거나 O3 플라즈마 처리를 통해 막내의 불순물을 감소시키는 공정이 수반되어야 하는데, 이렇게 하면, 도 1에 도시된 바와 같이, TiN의 하부전극(3)과 HfxAlyOz의 유전막(5) 사이에 산화물층(4)이 형성되어 기생 캐패시터가 형성되는 바, 급격한 충전용량 감소가 유발된다. However, since the ALD Hf x Al y O z thin film contains a large amount of impurities such as carbon (C) and nitrogen (N) in the film, the ALD Hf x Al y O z thin film is subjected to heat treatment in a high temperature O 2 atmosphere or an O 3 plasma treatment after deposition. A process of reducing impurities in the film must be accompanied. In this case, as shown in FIG. 1, the oxide layer 4 is interposed between the lower electrode 3 of TiN and the dielectric film 5 of Hf x Al y O z . This is formed so that the parasitic capacitor is formed, causing a sudden decrease in the charging capacity.

도 1에서, 미설명된 도면부호 1은 반도체기판, 2는 층간절연막, 6은 상부전극, 6a는 상부전극용 TiN막, 그리고, 6b는 상부전극용 poly-Si막을 각각 나타낸다. In FIG. 1, reference numeral 1 denotes a semiconductor substrate, 2 an interlayer insulating film, 6 an upper electrode, 6a an TiN film for an upper electrode, and 6b an poly-Si film for an upper electrode, respectively.

결국, 고용량의 캐패시터를 얻기 위해서는 상기한 HfxAlyOz의 적용이 유용하겠지만, 기생 캐패시터가 형성됨에 따른 급격한 충전용량의 감소 문제를 해결하지 않는 한, 현재로는 유전 물질로서 HfxAlyOz의 적용이 실질적으로 곤란하다. After all, the application of the above Hf x Al y O z is useful to obtain a high capacity capacitor, but at present, Hf x Al y as a dielectric material as long as it does not solve the problem of the abrupt reduction of the charging capacity as the parasitic capacitor is formed Application of O z is substantially difficult.

따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출된 것으로서, 유전 물질로 HfxAlyOz를 적용하면서도 기생 캐패시터의 형성에 의한 급격한 충전용량의 감소를 방지할 수 있는 반도체 소자의 캐패시터 형성방법을 제공함에 그 목적이 있다. Accordingly, the present invention has been made to solve the above-mentioned conventional problems, while applying a Hf x Al y O z as a dielectric material of the semiconductor device that can prevent a sudden decrease in the charge capacity due to the formation of the parasitic capacitor It is an object to provide a method of forming a capacitor.

상기와 같은 목적을 달성하기 위하여, 본 발명은, 하지층을 구비한 반도체기판 상에 TiN막을 증착하는 단계; 상기 TiN막 Ru 박막을 증착하는 단계; 상기 Ru 박막 상에 ALD 공정에 따라 HfxAlyOz의 유전막을 형성함과 아울러, 상기 Ru막 표면에 산화막이 형성되는 것에 의해 TiN/Ru/RuO2의 하부전극을 형성하는 단계; 및 상기 HfxAlyOz의 유전막 상에 TiN/poly-Si의 상부전극을 형성하는 단계를 포함하는 반도체 소자의 캐패시터 형성방법을 제공한다. In order to achieve the above object, the present invention, the step of depositing a TiN film on a semiconductor substrate having a base layer; Depositing the TiN film Ru thin film; Forming a lower electrode of TiN / Ru / RuO 2 by forming an Hf x Al y O z dielectric film on the Ru thin film and forming an oxide film on the surface of the Ru film; And forming an upper electrode of TiN / poly-Si on the dielectric film of Hf x Al y O z .

여기서, 상기 HfxAlyOz의 유전막은 "TEMAH(Hf 소오스) 플로우 -> N2 퍼지 -> O3 플라즈마 처리 -> N2 퍼지 -> TMA(Al 소오스) -> N2 퍼지 -> O3 -> N2 퍼지"를 1-싸이클로 하는 ALD 공정에 따라 형성하는 것을 특징으로 한다. Here, the dielectric film of Hf x Al y O z is " TEMAH (Hf source) flow-> N 2 purge-> O 3 plasma treatment-> N 2 purge-> TMA (Al source)-> N 2 purge-> O 3- > N 2 purge "according to the ALD process with 1-cycle.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

먼저, 본 발명의 기술적 원리를 간략하게 설명하면, 본 발명은 유전 물질로 HfxAlyOz를 적용함에 있어서 하부전극 물질인 TiN막 상에 Ru막을 추가 증착해 줌으로써 TiN의 하부전극과 Hfx`한 충전용량의 감소가 초래되는 것을 방지한다. First, the technical principle of the present invention will be briefly described. In the present invention, in the application of Hf x Al y O z as a dielectric material, the lower electrode and Hf x of TiN are deposited by further depositing a Ru film on the TiN film, which is a lower electrode material. `Prevents a reduction in charge capacity.

즉, Ru은 그 자체로 전도성 물질인데, 산소와 결합하여 RuO2로 변할지라도 산화막이면서 전도성 물질의 특성을 그대로 유지한다. 따라서, 이와 같은 Ru막을 TiN막 상에 추가 증착해준 상태로 HfxAlyOz 박막을 증착함과 아울러 막내의 탄소(C) 및 질소(N) 불순물을 제거하기 위해 고온 산소 분위기에서의 열처리, 또는 O3 플라즈마 처리를 수행할 경우, 상기 Ru막 표면에 RuO2의 산화물층이 형성되어도 이러한 RuO2막에 의한 기생 캐패시터는 형성되지 않으므로, 결국, 본 발명은 HfxAly Oz의 유전막 적용시 문제점인 기생 캐패시터의 형성에 기인하는 급격한 충전용량의 감소를 방지할 수 있게 된다. That is, Ru is a conductive material in itself, and even though it is combined with oxygen to RuO 2 , it is an oxide film and maintains the properties of the conductive material as it is. Therefore, in order to deposit the Hf x Al y O z thin film in the state of further depositing such a Ru film on the TiN film, heat treatment in a high temperature oxygen atmosphere to remove carbon (C) and nitrogen (N) impurities in the film, Alternatively, when performing an O 3 plasma treatment, even if an oxide layer of RuO 2 is formed on the surface of the Ru film, the parasitic capacitor by the RuO 2 film is not formed. Thus, the present invention is applied to the dielectric film of Hf x Al y O z It is possible to prevent a sudden decrease in the charging capacity due to the formation of a parasitic capacitor, which is a problem in time.

자세하게, 도 2 내지 도 5는 본 발명에 따른 반도체 소자의 캐패시터 형성방법을 설명하기 위한 공정별 단면도로서, 이를 설명하면 다음과 같다. 2 to 5 are cross-sectional views for each process for describing a method of forming a capacitor of a semiconductor device according to the present invention.

도 2를 참조하면, 비트라인이 형성되고 이를 덮도록 층간절연막이 형성된 구조의 소정의 하지층(도시안됨)이 형성된 반도체기판(21) 상에 하부전극 물질로서 TiCl4 가스를 이용한 CVD 공정에 따라 150∼250Å, 바람직하게, 200Å의 두께로 TiN막(22)을 증착한다. Referring to FIG. 2, a semiconductor substrate 21 having a predetermined base layer (not shown) having a bit line formed thereon and an interlayer insulating layer formed thereon is formed in accordance with a CVD process using TiCl 4 gas as a lower electrode material. The TiN film 22 is deposited at a thickness of ˜250 kPa, preferably 200 kPa.

도 3을 참조하면, 하부전극 물질인 TiN막(22) 상에 MOCVD(Metal Organic CVD) 공정에 따라 Ru막(23)을 증착한다. 상기 Ru막(23)은, 전술한 바와 같이, 그 자체로 전도성 물질이며, 산화막으로 변화되더라도 전도성의 특성을 그대로 유지한다. Referring to FIG. 3, a Ru film 23 is deposited on a TiN film 22, which is a lower electrode material, by a metal organic CVD (MOCVD) process. As described above, the Ru film 23 is a conductive material in itself, and retains its conductivity even if it is changed into an oxide film.

도 4를 참조하면, Ru막(23) 상에 "TEMAH(Hf 소오스) 플로우 -> N2 퍼지 -> O3 플라즈마 처리 -> N2 퍼지 -> TMA(Al 소오스) -> N2 퍼지 -> O3 -> N2 퍼지"를 1-싸이클로 하는 ALD 공정에 따라 HfxAlyOz의 유전막(25)을 증착한다. 상기 HfxAlyOz의 유전막(25)은 높은 비정질 특성을 갖는 것으로 인해 누설전류가 작으며, 유전상수가 높고, 그리고, 고온의 열적 안정성이 우수하다. 4, "TEMAH (Hf source) flow-> N 2 purge-> O 3 plasma treatment-> N 2 purge-> TMA (Al source)-> N 2 purge on the Ru film 23> A dielectric film 25 of Hf x Al y O z is deposited according to an ALD process with O 3- > N 2 purge ". The dielectric film 25 of Hf x Al y O z has a high leakage characteristic, a low leakage current, a high dielectric constant, and excellent thermal stability at high temperature.

여기서, 상기 HfxAlyOz의 유전막(25)은 박막내에 탄소(C) 및 질소(N)의 불순물이 다량으로 함유되어 있는 바, 이를 제거하기 위해서 그 증착 후에 고온의 산소 (O2) 분위기에서 열처리하거나, 또는, O3 플라즈마 처리를 수행해야 한다. Here, the dielectric film 25 of Hf x Al y O z contains a large amount of impurities of carbon (C) and nitrogen (N) in the thin film. In order to remove this, high temperature oxygen (O 2 ) Heat treatment in the atmosphere or O 3 plasma treatment must be performed.

이때, TiN의 하부전극 상에 상기 HfxAlyOz의 유전막을 증착한 종래의 경우에는 산소 분위기의 열처리 또는 O3 플라즈마 처리시 TiN 하부전극의 표면에 산화물층이 형성되므로써, 기생 캐패시터의 발생으로 인해 급격한 충전용량의 감소가 초래된다. At this time, in the conventional case in which the dielectric film of Hf x Al y O z is deposited on the TiN lower electrode, an oxide layer is formed on the surface of the TiN lower electrode during an oxygen atmosphere heat treatment or O 3 plasma treatment, thereby generating parasitic capacitors. This leads to a sudden decrease in the charging capacity.

이에 반해, 본 발명은 TiN막(22) 상에 Ru막(23)을 증착해 준 상태로 HfxAlyOz의 유전막(25)을 증착하고, 그 과정에서 O3 플라즈마 처리를 수행하는데, 도시된 바와 같이, O3 플라즈마 처리 과정에서 상기 Ru막(23)의 표면에 RuO2막(23a)이 형성되지만, 이러한 RuO2막(23a)은 여전히 전도성 물질의 특성을 유지하므로, 기생 캐패시터는 형성되지 않으며, 따라서, 본 발명에서는 기생 캐패시터 형성에 기인하는 급격한 충전용량 감소는 초래되지 않는다. In contrast, the present invention deposits the dielectric film 25 of Hf x Al y O z in a state in which the Ru film 23 is deposited on the TiN film 22, and performs an O 3 plasma treatment in the process. Since, O 3 plasma process that the surface RuO 2 film (23a) in the Ru film 23 is formed from, such RuO 2 film (23a) is still maintaining the properties of the conductive material, as shown, a parasitic capacitor It is not formed, and therefore, in the present invention, a sudden decrease in charge capacity due to parasitic capacitor formation is not caused.

한편, 상기 TiN막(22)과 Ru막(23) 및 RuO2막(23a)은 모두 하부전극 물질이 되며, 이에 따라, TiN/Ru/RuO2의 하부전극(24)이 얻어진다. On the other hand, both the TiN film 22, the Ru film 23 and the RuO 2 film 23a are made of lower electrode materials, whereby the lower electrode 24 of TiN / Ru / RuO 2 is obtained.

도 5를 참조하면, HfxAlyOz의 유전막(25) 상에 상부전극 물질로서 TiCl4 가스를 이용한 CVD 공정에 따라 250∼350Å, 바람직하게, 300Å의 두께로 TiN막(26a)을 증착한 후, 1400∼1600Å, 바람직하게, 1500Å의 두께로 poly-Si막(26b)을 증착하고, 이를 통해, TiN/poly-Si의 상부전극(27)을 형성하므로써, 본 발명에 따른 캐패시터(30)의 형성을 완성한다. Referring to FIG. 5, the TiN film 26a is deposited on the dielectric film 25 of Hf x Al y O z with a thickness of 250 to 350 mW, preferably 300 mW according to a CVD process using TiCl4 gas as the upper electrode material. After that, the poly-Si film 26b is deposited to a thickness of 1400-1600 mV, preferably 1500 mV, thereby forming the upper electrode 27 of TiN / poly-Si, thereby allowing the capacitor 30 according to the present invention. Complete the formation of.

전술한 본 발명의 실시예에 있어서, 하부전극은 단순 플레이트형으로 형성되었지만, 보다 큰 충전용량의 확보를 위해 깊은 콘택을 갖는 오목형 또는 실린더형 구조로도 형성 가능하며, 그 밖의 다른 3차원 구조로도 형성 가능하다. In the above-described embodiment of the present invention, the lower electrode is formed in a simple plate shape, but can also be formed in a concave or cylindrical structure having a deep contact to secure a larger charging capacity, and other three-dimensional structures It is also possible to form.

또한, 전술한 본 발명의 실시예에서는 하부전극 물질인 TiN막 상에 Ru막을 증착하였지만, 그 대신 RuO막을 증착하여도 동일한 효과를 얻을 수 있다. In addition, in the above-described embodiment of the present invention, although the Ru film is deposited on the TiN film, which is the lower electrode material, the same effect can be obtained by depositing the RuO film instead.

이상에서와 같이, 본 발명은 TiN의 하부전극 표면에 산화막이면서도 전도성 물질을 형성하는 Ru막을 증착해줌으로써 유전 물질로 HfxAlyOz를 적용하더라도 충전용량의 감소는 방지할 수 있다. 따라서, 본 발명은 유전 물질로 고유전의 HfxAlyO z를 적용할 수 있으므로 ㎚급 소자에서 요구하는 높은 충전용량의 캐패시터를 구현할 수 있다. As described above, the present invention can prevent the reduction of the charging capacity even if Hf x Al y O z is applied as the dielectric material by depositing a Ru film that forms an oxide film and a conductive material on the TiN lower electrode surface. Therefore, the present invention can apply a high dielectric constant Hf x Al y O z as a dielectric material, it is possible to implement a high charge capacity capacitor required in the nm-class device.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

Claims (4)

소정의 하지층을 구비한 반도체기판 상에 TiN막을 증착하는 단계; Depositing a TiN film on a semiconductor substrate having a predetermined underlayer; 상기 TiN막 Ru 박막을 증착하는 단계; Depositing the TiN film Ru thin film; 상기 Ru 박막 상에 ALD 공정에 따라 HfxAlyOz의 유전막을 형성함과 아울러, 상기 Ru막 표면에 산화막이 형성되는 것에 의해 TiN/Ru/RuO2의 하부전극을 형성하는 단계; 및 Forming a lower electrode of TiN / Ru / RuO 2 by forming an Hf x Al y O z dielectric film on the Ru thin film and forming an oxide film on the surface of the Ru film; And 상기 HfxAlyOz의 유전막 상에 TiN/poly-Si의 상부전극을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법.And forming an upper electrode of TiN / poly-Si on the dielectric film of Hf x Al y O z . 제 1 항에 있어서, 상기 HfxAlyOz의 유전막은 The dielectric layer of claim 1, wherein the dielectric layer of Hf x Al y O z is "TEMAH(Hf 소오스) 플로우 -> N2 퍼지 -> O3 플라즈마 처리 -> N2 퍼지 -> TMA(Al 소오스) -> N2 퍼지 -> O3 -> N2 퍼지"를 1-싸이클로 하는 ALD 공정에 따라 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법. 1-cycle "TEMAH (Hf source) flow-> N 2 purge-> O 3 plasma treatment-> N 2 purge-> TMA (Al source)-> N 2 purge-> O 3- > N 2 purge" A capacitor forming method for a semiconductor device, characterized in that formed according to the ALD process. 제 1 항에 있어서, 상기 TiN막은 The method of claim 1, wherein the TiN film TiCl4 가스를 이용하여 150∼250Å 두께로 증착하는 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법. A method for forming a capacitor of a semiconductor device, characterized in that the deposition using a TiCl 4 gas to a thickness of 150 ~ 250Å. 제 1 항에 있어서, 상기 TiN/poly-Si은 The method of claim 1, wherein the TiN / poly-Si is 각각 250∼350Å 및 1400∼1600Å의 두께로 증착하는 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법. A method of forming a capacitor for a semiconductor device, characterized in that the deposition is carried out at a thickness of 250 to 350 kPa and 1400 to 1600 kPa, respectively.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101303178B1 (en) * 2006-10-10 2013-09-09 삼성전자주식회사 Method of manufacturing dielectric film in capacitor
US8859383B2 (en) 2009-02-06 2014-10-14 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device having dielectric layer with improved electrical characteristics

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101303178B1 (en) * 2006-10-10 2013-09-09 삼성전자주식회사 Method of manufacturing dielectric film in capacitor
US8859383B2 (en) 2009-02-06 2014-10-14 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device having dielectric layer with improved electrical characteristics

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