KR20060007918A - Display apparatus - Google Patents

Abstract

In the display device, the data driver provides a data signal inverted in units of 2k (k is one or more natural numbers) scan lines as a plurality of data lines, and the scan driver 4k * n− in response to the start signal or the control signal of the previous stage. 4k * n-3 stages outputting scan signals to 3 scan lines (n is a natural number greater than 1), 4k outputting scan signals to 4k * n-1 scan lines in response to control signals from 4k * n-3 stages 4k * n-2 stages for outputting scan signals to 4k * n-2 scan lines in response to control signals from * n-1 stages, 4k * n-1 stages, and control signals from 4k * n-2 stages A 4k * n stage outputs a scan signal to the 4k * n scan line in response. Therefore, power consumption of the display device can be reduced.

Description

Display device {DISPLAY APPARATUS}

1 is a plan view of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating in detail a scan driver of a liquid crystal display device employing a 1-line inversion driving method.

FIG. 3 is an output waveform diagram of the scan driver and the data driver shown in FIG. 2.

4 shows the polarity of the data signal during one frame.

5 is an output waveform diagram of a liquid crystal display device employing a two-line inversion driving method according to another embodiment of the present invention.

6 shows the polarity of the data signal during one frame.

7 is a view showing in detail the scan driver according to another embodiment of the present invention.

8 is an output waveform diagram of the scan driver of FIG. 7.

       * Description of the symbols for the main parts of the drawings *

100: liquid crystal display 110: data driver

130: display unit 150: scan driver

151: shift register

The present invention relates to a display device, and more particularly, to a display device capable of reducing power consumption.

A general liquid crystal display device includes a liquid crystal display panel for displaying an image and a driver for driving the liquid crystal display panel. The liquid crystal display panel has an array substrate, a color filter substrate, and a liquid crystal layer interposed between the array substrate and the color filter substrate.

The array substrate includes a plurality of data lines and a plurality of scan lines, and unit pixels are formed in the pixel region defined by the data lines and the scan lines. The unit pixel includes a thin film transistor, a liquid crystal capacitor, and a storage capacitor, which are one of the switching elements. The gate electrode of the thin film transistor is connected to the corresponding scan line, the source electrode is connected to the corresponding data line, and the drain electrode is connected to the pixel electrode which is the first electrode of the liquid crystal capacitor. The storage capacitor is defined by the common voltage line and the pixel electrode to which the common voltage is applied.

The color filter substrate includes a color filter formed of color pixels corresponding to unit pixels, and a common electrode to which a common voltage, which is a second electrode of the liquid crystal capacitor, is applied.

When a scan signal is applied to a predetermined scan line, data signals are simultaneously applied to the data lines. Each of the data signals applied to the data lines is applied to the corresponding pixel electrode, and a voltage difference from the common voltage applied to the common electrode is applied to the liquid crystal layer.

On the other hand, when a voltage in one direction is continuously applied to the liquid crystal layer employed in the liquid crystal display device, the liquid crystal layer has a deterioration characteristic. In order to prevent such deterioration, the liquid crystal display adopts an inversion driving method in which the polarity of the data signal is driven by a predetermined period, for example, one frame unit, one line unit, or two line unit. In particular, the small- and medium-size liquid crystal display adopts a one-line inversion or two-line inversion driving method for supplying data signals having different polarities to adjacent data lines.

The 1-line inversion driving method is a driving method for inverting the level of the common voltage every 1H and inverting the level of the data signal with respect to the level of the common voltage. Here, 1H time is a time used to activate one horizontal line (or scan line), and is defined by Equation 1 below.

In the case of adopting the one-line inversion or two-line inversion driving method in the recently developed high resolution liquid crystal display, the inverting frequency of the common voltage also increases as the resolution is increased. As the frequency of inversion of the common voltage increases, power consumption of the liquid crystal display increases.

Accordingly, it is an object of the present invention to provide a display device for reducing power consumption.

According to an aspect of the present invention, a display device includes a display unit including a plurality of data lines and a plurality of scan lines, and displays an image in response to a data signal and a scan signal, and is inverted by 2k (k is a natural number of 1 or more) And a scan driver comprising a plurality of stages coupled to one-to-one corresponding to the plurality of scan lines and outputting the scan signal to a corresponding scan line.

The plurality of stages are 4k * n-3 stages for outputting a scan signal to a 4k * n-3 scan line (n is a natural number of 1 or more) in response to a start signal or a control signal of a previous stage, and the 4k * n-3 stages. A 4k * n-1 stage that outputs a scan signal to a 4k * n-1 scan line in response to a control signal from a 4k * n-2 scan line in response to a control signal from the 4k * n-1 stage 4k * n-2 stages for outputting signals, and 4k * n stages for outputting scan signals to 4k * n scan lines in response to control signals from the 4k * n-2 stages.

According to another aspect of the present invention, a display device includes a display unit including a plurality of data lines and a plurality of scan lines, and displays an image in response to a data signal and a scan signal, and is inverted by 2k (k is a natural number of 1 or more) And a scan driver comprising a plurality of stages coupled to one-to-one corresponding to the plurality of scan lines and outputting the scan signal to a corresponding scan line.

The plurality of stages are 3n + 1 (n is an integer greater than 0) stages that output scan signals to corresponding scan lines in response to a clock and a first enable signal, and corresponding to the clock and a second enable signal. And a 3n + 2 stage for outputting a scan signal to a scan line, and a 3n stage for outputting a scan signal to a corresponding scan line in response to the clock and the third enable signal.

According to such a display device, by using a common voltage having a pulse period of 4H or 8H can operate in a one-line inversion or two-line inversion driving method, it is possible to reduce the power consumption of the display device.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

1 is a plan view of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the liquid crystal display device 100 according to an exemplary embodiment may include a display unit 130 displaying an image, a scan driver 150 outputting a scan signal, and a data driver 110 outputting a data signal. ).

The display unit 130 includes a plurality of scan lines and a plurality of data lines, and the plurality of scan lines SL1, SL2, SL3, SL4,... SLn and the plurality of data lines DL1 to DLm Orthogonal to each other. The plurality of scan lines SL1 to SLn and the plurality of data lines DL1 to DLm divide a plurality of pixel regions in a matrix form on the display unit 130, and each of the pixel regions includes a thin film transistor TFT and a liquid crystal. A capacitor CLC and a storage capacitor CS are provided.

A gate electrode of the thin film transistor TFT is connected to a corresponding scan line, a source electrode is connected to a corresponding data line, and a drain electrode is a pixel which is a first electrode of the liquid crystal capacitor CLC and the storage capacitor CS. Coupled with the electrode. The common voltage VCOM is applied to the common electrode (not shown), which is the second electrode of the liquid crystal capacitor CLC, and the common voltage line, which is the second electrode of the storage capacitor CS.

The scan driver 150 is coupled to one end of the plurality of scan lines SL1 to SLn and outputs the scan signals to the plurality of scan lines SL1 to SLn. The scan driver will be described in detail later with reference to FIGS. 2 and 3. Meanwhile, the data driver 110 is coupled to one end of the plurality of data lines DL1 to DLm and outputs the data signals to the plurality of data lines DL1 to DLm.

FIG. 2 is a diagram illustrating in detail a scan driver of a liquid crystal display device employing a 1-line inversion driving method.

Referring to FIG. 2, the scan driver 150 (shown in FIG. 1) includes a shift register 151 including a plurality of stages SRC1 to SRCn + 1. Each of the plurality of stages SRC1 to SRCn + 1 includes a clock terminal CK, an input terminal IN, a control terminal CT, a first driving voltage terminal VON, a second driving voltage terminal VOFF, and an output. It includes a terminal (OUT).

The first clock CKV is provided to the clock terminal CK of the odd stages SRC1, SRC3,... SRCn + 1 of the plurality of stages SRC1 to SRCn + 1, and the even stages SRC2, The clock terminal CK of SRC4, ... SRCn is provided with a second clock CKVB having a phase different from that of the first clock CKV. The first clock CKV and the second clock CKVB have different phases. Here, the first clock CKV and the second clock CKVB have inverted phases.

The plurality of stages SRC1 to SRCn + 1 may include first to n-th driving stages SRC1 to SRCn and one dummy stage SRCn + 1. The first to n-th driving stages SRC1 to SRCn are connected in one-to-one correspondence with the plurality of scan lines SL1 to SLn provided on the display unit 130. The dummy stage SRCn + 1 is a stage provided as a dummy to drive the n-th driving stage SRCn.

The first to nth driving stages SRC1 to SRCn are divided into n / 4 blocks including four stages, and each block operates sequentially. Hereinafter, the overall configuration of the shift register 151 will be described in detail by describing a first block including first, second, third, and fourth driving stages SRC1, SRC2, SRC3, and SRC4 as an example. .

The start signal STV is applied to the input terminal IN of the first driving stage SRC1, and the control terminal CT is coupled to the output terminal OUT of the third driving stage SRC3. The input terminal IN of the second driving stage SRC2 is coupled to the output terminal OUT of the third driving stage SRC3, and the control terminal CT is an output terminal of the fourth driving stage SRC4. OUT). The input terminal IN of the third driving stage SRC3 is coupled with the output terminal OUT of the first driving stage SRC1, and the control terminal CT is an output terminal of the second driving stage SRC2. OUT). Finally, the input terminal IN of the fourth driving stage SRC4 is coupled to the output terminal OUT of the second driving stage SRC2, and the control terminal CT is the fifth driving stage (not shown). Combine with the output terminal of OUT.                     

Therefore, in the first block, the first driving stage SRC1 operates first, after which the third driving stage SRC3 operates, then the second driving stage SRC2 operates, and finally As a result, the fourth driving stage SRC4 operates.

3 is an output waveform diagram of the scan driver and the data driver shown in FIG. 2, and FIG. 4 is a diagram illustrating the polarity of the data signal during one frame.

Referring to FIG. 3, the first driving stage SRC1 outputs the first scan signal S1 to the first scan line SL1 in response to the first clock CKV and the start signal STV. Thereafter, the third driving stage SRC1 outputs a third scan signal S3 to the third scan line SL3 in response to the first clock CKV and the first scan signal S1. Next, the second driving stage SRC2 outputs the second scan signal S2 to the second scan line SL2 in response to the second clock CKVB and the third scan signal S3. . Finally, the fourth driving stage SRC4 outputs a fourth scan signal S4 to the fourth scan line SL4 in response to the second clock CKVB and the second scan signal S2. The period of the first and second clocks CKV and CKVB is four times the high period of each of the first to fourth scan signals S1 to S4.

Thereafter, the second block including the fifth, sixth, seventh, and eighth driving stages (not shown) operates in the same manner as the first block. Accordingly, the fifth, seventh, sixth, and eighth scan signals S5, S7, S6, and S8 are output in the order of the fifth, seventh, sixth, and eighth driving stages, respectively. The sixth and eighth scan lines (not shown).                     

Meanwhile, the data signal DATA output from the data driver 110 (shown in FIG. 1) has a phase inverted with the common voltage VCOM. When the first scan signal S1 is applied to the first scan line SL1, the data driver 110 outputs the bipolar data signal DATA higher than the common voltage VCOM to the plurality of data lines. DL1 to DLm (shown in FIG. 1). Thereafter, when the third scan signal S3 is applied to the third scan line SL3, the data driver 110 still transmits the bipolar data signal DATA to the plurality of data lines DL1 to DLm. Is authorized.

Next, when the second scan signal S2 is applied to the second scan line SL2, the data driver 110 outputs the data signals DATA having a lower polarity than the common voltage to the plurality of data lines. (DL1 to DLm). Thereafter, when the fourth scan signal S4 is applied to the fourth scan line SL4, the data driver 110 still transmits the negative data signal DATA to the plurality of data lines DL1 to DLm. Is authorized. As such, the polarity of the data signal DATA is inverted in units of two scan lines.

As shown in FIG. 4, the polarity of the data signal DATA is inverted in units of two scan lines, but the polarity of the data signal DATA in the display unit 130 in one frame is inverted in units of one scan line. do.

As described above, the liquid crystal display 100 drives 1-line reversal driving using a common voltage having a pulse period of 4H with the scan driver 150 outputting scan signals out of sequence to the plurality of scan lines SL1 to SLn. By adopting the method, the power consumption of the liquid crystal display device 100 can be reduced. In particular, the liquid crystal display device 100 according to the present invention has a cycle reduced by 1/2 compared to the liquid crystal display device using the 1-line inversion driving method using the common voltage VCOM having a pulse period of 2H. Compared with the conventional liquid crystal display, power consumption can be relatively reduced.

FIG. 5 is an output waveform diagram of a liquid crystal display device employing a two-line inversion driving method according to another embodiment of the present invention, and FIG. 6 is a view showing polarities of data signals during one frame.

Referring to FIG. 5, according to another exemplary embodiment of the present invention, the first driving stage SRC1 may receive the first scan signal as the first scan line SL1 in response to the first clock CKV and the start signal STV. The second driving stage SRC2 outputs the second scan signal S2 to the second scan line SL2 in response to the second clock CKVB and the first scan signal S1. Output Next, the fifth driving stage SRC5 outputs the fifth scan signal S5 to the fifth scan line SL5 in response to the first clock CKV and the second scan signal S2. The sixth driving stage SRC6 outputs a sixth scan signal S6 to the sixth scan line SL6 in response to the second clock CKVB and the fifth scan signal S5.

Thereafter, the third driving stage SRC3 outputs a third scan signal S3 to the third scan line SL3 in response to the first clock CKV and the sixth scan signal S6, and fourth The driving stage SRC4 outputs a fourth scan signal S4 to the fourth scan line SL4 in response to the second clock CKVB and the third scan signal S3. Finally, the seventh driving stage SRC7 outputs the seventh scan signal S7 to the seventh scan line SL7 in response to the first clock CKV and the fourth scan signal S4. The eighth driving stage SRC8 outputs the eighth scan signal S8 to the eighth scan line SL8 in response to the second clock CKVB and the seventh scan signal S7.

Meanwhile, the data signal DATA output from the data driver 110 (shown in FIG. 1) has a phase inverted with the common voltage VCOM. When the first and second scan signals S1 and S2 are respectively applied to the first and second scan lines SL1 and SL2, the data driver 110 may have bipolar data higher than the common voltage VCOM. The signal DATA is applied to the plurality of data lines DL1 to DLm. Thereafter, when the fifth and sixth scan signals S5 and S6 are applied to the fifth and sixth scan lines SL5 and SL6, the data driver 110 still receives the bipolar data signal DATA. The data lines are applied to the plurality of data lines DL1 to DLm.

Next, when the third and fourth scan signals S3 and S4 are respectively applied to the third and fourth scan lines SL3 and SL4, the data driver 110 may be larger than the common voltage VCOM. The data signal DATA inverted with low negative polarity is applied to the plurality of data lines DL1 to DLm. Thereafter, when the seventh and eighth scan signals S7 and S8 are respectively applied to the seventh and eighth scan lines SL7 and SL8, the data driver 110 still receives the negative data signal DATA. The data lines are applied to the plurality of data lines DL1 to DLm. As such, the polarity of the data signal DATA is inverted in units of 4 scan lines.

As shown in FIG. 6, the polarity of the data signal DATA is inverted in units of 4 scan lines, but the polarity of the data signal DATA shown in the display unit 130 in one frame is inverted in units of 2 scan lines. .                     

As described above, the liquid crystal display 100 drives the two-line inversion using the common voltage having a pulse period of 8H with the scan driver 150 which outputs scan signals out of sequence to the plurality of scan lines SL1 to SLn. By adopting the method, the power consumption of the liquid crystal display device 100 can be reduced. In particular, the liquid crystal display device 100 according to the present invention has a conventional cycle by reducing the cycle by 1/2 compared to the liquid crystal display device using the two-line inversion driving method using a common voltage VCOM having a pulse period of 4H. It is possible to reduce the power consumption relative to the LCD.

7 is a diagram illustrating a scan driver in accordance with another embodiment of the present invention in detail, and FIG. 8 is an output waveform diagram of the scan driver shown in FIG. 7.

Referring to FIG. 7, the scan driver 151 according to another embodiment of the present invention includes a shift register including a plurality of stages SRC1 to SRCn + 1. Each of the plurality of stages SRC1 to SRCn + 1 includes a clock terminal CK, an input terminal IN, a control terminal CT, an enable terminal OE, a first driving voltage terminal VON, and a second driving. It includes a voltage terminal (VOFF) and an output terminal (OUT).

The plurality of stages SRC1 to SRCn + 1 may include first to n-th driving stages SRC1 to SRCn and one dummy stage SRCn + 1. The first to n-th driving stages SRC1 to SRCn are connected in a one-to-one correspondence with the plurality of scan lines SL1 to DLn included in the display unit 130 (shown in FIG. 1), and are independent of adjacent driving stages. Is connected. The dummy stage SRCn + 1 is a stage provided as a dummy to drive the n-th driving stage SRCn.                     

The first clock CKV is provided to the clock terminal CK of the odd stages SRC1, SRC3,... SRCn + 1 of the plurality of stages SRC1 to SRCn + 1, and the even stages SRC2, The clock terminal CK of SRC4, ... SRCn is provided with a second clock CKVB having a phase different from that of the first clock CKV. The first clock CKV and the second clock CKVB have inverted phases.

A first enable signal OE1 is provided to the enable terminal OE of the 3k + 1 driving stages SRC1, SRC4, and SRC7 among the first to nth driving stages SRC1 to SRCn, and drives 3k + 2. The second enable signal OE2 is provided to the enable terminal OE of the stages SRC2, SRC5, and SRC8, and the third enable signal OE is provided to the enable terminal OE of the 3k driving stages SRC3 and SRC6. OE3) is provided. Here, k is an integer of 0 or more.

As shown in FIG. 8, the first to third enable signals OE1 to OE3 are kept low for one third of one period. The second enable signal OE3 is a signal delayed by one-third period than the first enable signal OE1, and the third enable signal OE3 is greater than the second enable signal OE2. This signal is delayed by 1/3 cycle.

The 3k + 1 driving stages SRC1, SRC4, and SRC7 output a scan signal to a high section of the first or second clocks CKV and CKVB when the first enable signal OE1 is low. The 3k + 2 driving stages SRC2, SRC5, and SRC8 output a scan signal to a high section of the first or second clocks CKV and CKVB when the second enable signal OE2 is in a low state. The 3k driving stages SRC3 and SRC6 output a scan signal to a high section of the first or second clocks CKV and CKVB when the third enable signal OE3 is low.

When the first driving stage SRC1 outputs the first scan signal S1 to the first scan line SL1 in response to the first enable signal OE1 and the first clock CKV, the second driving stage SRC1 outputs the first scan signal S1. The stage SRC2 outputs the second scan signal S2 to the second scan line SL2 in response to the second enable signal OE2 and the second clock CKVB. Subsequently, when the fifth driving stage SRC5 outputs the fifth scan signal S5 to the fifth scan line SL5 in response to the second enable signal OE2 and the first clock CKV, The sixth driving stage SRC6 outputs the sixth scan signal S6 to the sixth scan line SL6 in response to the third enable signal OE3 and the second clock CKVB.

Next, when the third driving stage SRC3 outputs the third scan signal S3 to the third scan line SL3 in response to the third enable signal OE3 and the first clock CKV. The fourth driving stage SRC4 outputs a fourth scan signal S4 to the fourth scan line SL4 in response to the first enable signal OE1 and the second clock CKVB. Finally, when the seventh driving stage SRC7 outputs the seventh scan signal S7 to the seventh scan line SL7 in response to the first enable signal OE1 and the first clock CKV, The eighth driving stage SRC8 outputs an eighth scan signal S8 to the eighth scan line SL8 in response to the second enable signal OE2 and the second clock CKVB.

Meanwhile, the data signal DATA output from the data driver 110 (shown in FIG. 1) has a phase inverted with the common voltage VCOM. When the first and second scan signals S1 and S2 are respectively applied to the first and second scan lines SL1 and SL2, the data driver 110 may have bipolar data higher than the common voltage VCOM. The signal DATA is applied to the plurality of data lines DL1 to DLm. Thereafter, when the fifth and sixth scan signals S5 and S6 are applied to the fifth and sixth scan lines SL5 and SL6, the data driver 110 still receives the bipolar data signal DATA. Applied to the plurality of data lines DL to DLm.

Next, when the third and fourth scan signals S3 and S4 are respectively applied to the third and fourth scan lines SL3 and SL4, the data driver 110 may be larger than the common voltage VCOM. The data signal DATA inverted with low negative polarity is applied to the plurality of data lines DL1 to DLm. Thereafter, when the seventh and eighth scan signals S7 and S8 are respectively applied to the seventh and eighth scan lines SL7 and SL8, the data driver 110 still receives the negative data signal DATA. The data lines are applied to the plurality of data lines DL1 to DLm. As such, the polarity of the data signal DATA is inverted in units of 4 scan lines.

As described above, the liquid crystal display 100 drives the two-line inversion using the common voltage having a pulse period of 8H with the scan driver 150 which outputs scan signals out of sequence to the plurality of scan lines SL1 to SLn. By adopting the method, the power consumption of the liquid crystal display device 100 can be reduced. In particular, the liquid crystal display device 100 according to the present invention has a conventional cycle by reducing the cycle by 1/2 compared to the liquid crystal display device using the two-line inversion driving method using a common voltage VCOM having a pulse period of 4H. It is possible to reduce the power consumption relative to the LCD.

According to such a display device, the scan driver outputs scan signals in a non-sequential manner so that the display device can operate in a one-line inversion or two-line inversion driving method using a common voltage having a pulse period of 4H or 8H. do.

Therefore, in the display device adopting the one-line inversion or the two-line inversion driving method, the frequency of the common voltage is increased by about twice that of the related art, thereby reducing power consumption of the display device.

Although described with reference to the embodiments, it will be understood by those skilled in the art that the present invention may be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (5)

A display unit including a plurality of data lines and a plurality of scan lines and displaying an image in response to the data signal and the scan signal; A data driver for providing the plurality of data lines with the data signal inverted in units of 2k (k is one or more natural numbers) scan lines; And A scan driver including a plurality of stages coupled to correspond to the plurality of scan lines one-to-one and outputting the scan signal to a corresponding scan line; The plurality of stages, A 4k * n-3 stage for outputting a scan signal to a 4k * n-3 scan line (n is a natural number of 1 or more) in response to a start signal or a control signal of a previous stage; A 4k * n-1 stage outputting a scan signal to a 4k * n-1 scan line in response to the control signal from the 4k * n-3 stage; A 4k * n-2 stage outputting a scan signal to a 4k * n-2 scan line in response to a control signal from the 4k * n-1 stage; And And a 4k * n stage outputting a scan signal to a 4k * n scan line in response to a control signal from the 4k * n-2 stage. The display device of claim 1, wherein k is 1 or 2. A display unit including a plurality of data lines and a plurality of scan lines and displaying an image in response to the data signal and the scan signal; A data driver for providing the plurality of data lines with the data signal inverted in units of 2k (k is one or more natural numbers) scan lines; And A scan driver including a plurality of stages coupled to correspond to the plurality of scan lines one-to-one and outputting the scan signal to a corresponding scan line; The plurality of stages, A 3n + 1 (n is an integer greater than or equal to 0) stage for outputting a scan signal to a corresponding scan line in response to a clock and a first enable signal; A 3n + 2 stage outputting a scan signal to a corresponding scan line in response to the clock and a second enable signal; And And a 3n stage configured to output a scan signal to a corresponding scan line in response to the clock and the third enable signal. The method of claim 3, wherein the first to third enable signals are kept low for one third of one period. And the first to third enable signals are delayed by one-third period in the order of the first, third and second enable signals. The method of claim 4, wherein the 3n + 1 stage outputs the scan signal to a 3n + 1 scan line when the first enable signal is low and the clock is high. The 3n + 2 stage outputs the scan signal to a 3n + 2 scan line when the second enable signal is low and the clock is high. And the 3n stage outputs the scan signal to the 3n scan line when the third enable signal is low and the clock is high.

Images