KR20060001350A - Thin film transistor, method of manufacturing of that tft, and flat panel display device with that tft - Google Patents

Abstract

An object of the present invention is to provide a polycrystalline silicon thin film transistor having a uniform current characteristic, a method of manufacturing the same, and a flat panel display device having the same. An active layer having a thickness of 530 Å, a gate electrode provided to correspond to a channel region of the active layer, a gate insulating film insulating the active layer and the gate electrode, and a source electrode and a drain electrode connected to the active layer; A thin film transistor is provided.

Description

Thin film transistor, method of manufacturing the thin film transistor and a flat panel display device having the same {Thin Film transistor, method of manufacturing of that TFT, and flat panel display device with that TFT}

1 is a cross-sectional view showing a polycrystalline silicon thin film transistor according to a preferred embodiment of the present invention.

2 is a graph showing the relationship between the thickness of an amorphous silicon layer of a thin film transistor and the magnitude of a current flowing through a channel region of the silicon layer.

FIG. 3 shows the relationship between the thickness of the amorphous silicon layer of a thin film transistor and the variation of the magnitude of the on current flowing through the channel region of the semiconductor layer, exactly three times the value (3σ) of the dispersion. graph.

4 is a flow chart showing a process of manufacturing a polycrystalline silicon thin film transistor according to another preferred embodiment of the present invention.

5 to 13 are cross-sectional views illustrating a process for manufacturing the polycrystalline silicon thin film transistor according to the flowchart of FIG. 4.

Fig. 14 is a circuit diagram schematically showing a circuit of an active matrix type electroluminescent display device according to another preferred embodiment of the present invention.

FIG. 15 is a circuit diagram illustrating a portion A of FIG. 14.

FIG. 16 is a plan view of an active matrix type electroluminescence display schematically showing portion A of FIGS. 14 and 15.

FIG. 17 is a cross-sectional view of a subpixel unit of an active matrix type electroluminescent display taken along P1 to P7 of FIG.

<Description of the symbols for the main parts of the drawings>

100 substrate 110 buffer layer

120: amorphous silicon layer 122: polycrystalline silicon layer

124a and 124b: source region 124b: drain region

124c: channel region 124: semiconductor layer

130: gate insulating film 140: gate electrode

150: interlayer insulating film 150a, 150b: contact hole

160a, 160b: source and drain electrodes 201: controller

202: Data Driver 203: Scan Driver

210: first thin film transistor 211: first gate electrode

212: first source electrode 213: first drain electrode

220: first conductor 230: second conductor

240: storage capacitor 250: second thin film transistor

251: second gate electrode 252: second source electrode

253: second drain electrode 260: display unit

261: first electrode 262: second electrode

270: third conductive wire 280: semiconductor layer

281: substrate 282: buffer layer

283: gate insulating film 284: interlayer insulating film

285: first protective film 286: planarization layer

287a: first intermediate layer 287b: light emitting layer

287c: second intermediate layer 289: second protective film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor, a method for manufacturing the thin film transistor, and a flat panel display device using the same. More particularly, the present invention relates to a thin film transistor having a semiconductor layer having a thickness of about 390 Å to 530 와, a manufacturing method thereof, and a flat display device using the same. will be.

Thin film transistors (TFTs) can be roughly divided into amorphous silicon type and polycrystalline silicon type according to the characteristics of the semiconductor layer. In the case of a thin film transistor using amorphous silicon as a semiconductor layer, a large area can be reduced by deposition at a low temperature of about 350 ° C. or lower, and a low cost glass substrate can be used, thereby reducing manufacturing costs. In many cases, a driving element for changing a transmittance of a pixel by controlling a voltage applied to a liquid crystal of one pixel is used. However, amorphous silicon is not suitable for forming a transistor element of a driving circuit requiring fast operating characteristics because of the low carrier mobility. On the other hand, polycrystalline silicon has a higher carrier mobility than amorphous silicon, which is advantageous as a switching device of a high resolution panel, and is easy to be applied to a display device exposed to a lot of light due to less photocurrent than amorphous silicon.

However, when the thin film transistor is manufactured using polycrystalline silicon as the semiconductor layer, the leakage current is larger than that of the amorphous silicon thin film transistor, and the current between the source electrode and the drain electrode is not kept constant. Therefore, when it is used in a display device, since luminance uniformity is lowered, a problem such as spots appearing on an image may occur. In particular, in the case of an active matrix type electroluminescent display, an image is generated by adjusting a current flowing through a light emitting element in each pixel, so that uniformity of current characteristics controlled by an active element in each pixel is very important. The uniformity of current characteristics of the thin film transistor used as a layer becomes a big problem.

In order to solve the above problems, various attempts have been made. Among them, Korean Patent Laid-Open Publication No. 2003-0057074 forms a sequential doping region in which an offset region and a doping density sequentially change in a polycrystalline silicon semiconductor layer to minimize leakage current. A polycrystalline silicon thin film transistor capable of preventing a decrease in on current and a method of manufacturing the same are disclosed. The offset region and the sequential doping region can limit the horizontal electric field at the gate and drain boundary, resulting in suppression of the leakage current. However, the present invention can suppress the leakage current, but does not improve the uniformity of the current characteristics of the thin film transistor.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a polycrystalline silicon thin film transistor having a uniform current characteristic, a method of manufacturing the same, and a flat panel display device having the same.

In order to achieve the above object and various other objects, the present invention provides a substrate, an active layer having a thickness of about 390 Å to 530 Å formed on the substrate, a gate electrode provided to correspond to the channel region of the active layer, A thin film transistor comprising a gate insulating film which insulates the active layer and the gate electrode, and a source electrode and a drain electrode connected to the active layer.

In order to achieve the above object, the present invention also provides a method of forming a polycrystalline silicon layer by depositing an amorphous silicon layer having a thickness of about 390 kPa to 530 kPa on a substrate, and crystallizing the amorphous silicon layer to form a polycrystalline silicon layer; Forming a gate insulating film on the polycrystalline silicon layer, forming a gate electrode on the gate insulating film, activating the polycrystalline silicon layer, and stacking an intermediate layer having contact holes formed over the entire surface of the substrate. It provides a method for manufacturing a thin film transistor comprising the step of forming a source electrode and a drain electrode thereon.

According to another feature of the invention, the step of crystallization may use a laser.

In order to achieve the above object, the present invention also includes a light emitting area having a plurality of pixels and a selection driving circuit provided for each pixel, wherein each selection driving circuit includes a substrate and a substrate formed on the substrate. An active layer having a thickness of about 390 kV to 530 kV, a gate electrode provided to correspond to a channel region of the active layer, a gate insulating film insulating the active layer and the gate electrode, and a source electrode and a drain electrode connected to the active layer; A flat panel display device comprising at least one thin film transistor is provided.

According to another feature of the invention, the flat panel display further comprises a driving circuit for controlling a signal applied to the light emitting region, the driving circuit is a substrate and a thickness of approximately 390 ~ 530 Å formed on the substrate At least one thin film transistor including an active layer having a gate electrode, a gate electrode provided to correspond to a channel region of the active layer, a gate insulating film insulating the active layer and the gate electrode, and a source electrode and a drain electrode connected to the active layer It can be provided.

According to still another feature of the present invention, the image implementing device including the light emitting area of the flat panel display may be an electroluminescent device.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view showing a polycrystalline silicon thin film transistor according to a preferred embodiment of the present invention.

Referring to FIG. 1, a buffer layer 110 is provided on a substrate 100 using silicon oxide as an insulating material, and a semiconductor layer made of polycrystalline silicon, that is, a channel region 124c, is formed on the buffer layer 110. Source and drain regions 124a and 124b are formed on both sides of the channel region 124c, respectively. The source and drain regions 124a and 124b are doped with n-type or p-type impurities and may include a silicide layer.

A gate insulating layer 130 formed of silicon oxide (SiO ₂ ) or silicon nitride (SIN _x ) covering the semiconductor layers 124a, 124b, and 124c is formed on the substrate 100, and the upper portion of the channel region 126 is formed. The gate electrode 140 is formed on the gate insulating layer 130. An interlayer insulating layer 150 is formed on the gate insulating layer 130 to cover the gate electrode 140. The gate insulating layer 130 and the interlayer insulating layer 150 are the sources of the semiconductor layers 124a, 124b, and 124c. And contact holes 150a and 150b exposing drain regions 124a and 124b.

A source electrode 160a connected to the source region 124a through a contact hole 150a and an upper surface of the interlayer insulating layer 150 facing the source electrode 160a around the gate electrode 140. A drain electrode 160b connected to the drain region 124b through the contact hole 150b is formed. Silicon nitride, silicon oxide, an a-Si: O: C, an a-Si: O: F film, or an organic insulating material (not shown) may be formed on the interlayer insulating layer 150.

In the polycrystalline silicon thin film transistor having the above structure, the current characteristic flowing between the source electrode 160a and the drain electrode 160b through the polycrystalline silicon layer 124 should be uniform.

FIG. 2 is a graph illustrating a relationship between a thickness T of a semiconductor layer 124 formed of polycrystalline silicon and an amount of on current flowing through a channel region of the semiconductor layer in the polycrystalline silicon thin film transistor of FIG. 1. It is a graph to show. The horizontal axis represents the thickness of the semiconductor layer 124 formed of polycrystalline silicon, and the vertical axis represents the size of on current. As described below, the semiconductor layer formed of polycrystalline silicon is formed by depositing amorphous silicon on the substrate 100 and crystallizing it. The horizontal axis of FIG. 2 accurately represents the thickness of the amorphous silicon layer before crystallization. will be. The unit of thickness of a silicon layer is kPa, and the unit of oncurrent is kPa / micrometer.

Referring to FIG. 2, the uniformity of the on current (current) varies depending on the thickness of the silicon layer, and the thickness of the silicon layer is most uniform when the thickness of the silicon layer is 400 kW to 520 kW, and uniformity decreases as the thickness of the silicon layer becomes thinner or thicker. Appeared to be. As described above, since the uniformity of the luminance decreases as the uniformity of the current decreases, problems such as spots appearing on the image occur. In order to prevent such a problem, the magnitude of the current is better. Referring to the graph of FIG. 2, the thickness of the silicon layer corresponding to the case where the magnitude of the variation width of the current is the smallest is 400 kPa or more and 520 kPa or less. On the other hand, in general, when forming a silicon layer of a certain thickness it is not possible to form the same thickness of all parts of the silicon layer in the current process, there will be a deviation, on average when forming a silicon layer of the specific thickness The spread is approximately ± 10 dB. Therefore, the amorphous silicon layer is deposited on the substrate with a thickness of 390 Å or more and 530 Å or less, and then crystallized to produce a thin film transistor to realize a clear image when used in a display device. Therefore, the thickness of the amorphous silicon layer is preferably 390 kPa or more and 530 kPa or less.

FIG. 3 shows the relationship between the thickness of the amorphous silicon layer of a thin film transistor and the variation of the magnitude of the on current flowing through the channel region of the semiconductor layer, exactly three times the value (3σ) of the dispersion. It is a graph.

Currently, the lower limit of the size of the on-current flowing through the channel region of the semiconductor layer is 9 μs / µm, and the variation in the size of the on-current is approximately 10% of the average of the average on-current size. Therefore, if the average of the size of the on current is 9 μs / μm, the variation of the size of the on current is about 0.9 μm / μm, and as a result, the size of the on current is smaller than the lower limit of 9 μs / μm. As such, the average of the size of the on-current is preferably 10 mW / µm. At this time, in order to prevent the size of the on-current from being smaller than the lower limit of 9 μs / μm, the fluctuation range of the size of the on-current may be within 1 μm / μm. Therefore, in order to have a statistically 99.97% probability that the variation in the magnitude of the oncurrent is within 1 dB / µm, the value is three times the spread of the variation in the magnitude of the oncurrent, that is, the three sigma (3σ) value. The thickness of the silicon layer may be 400 mW or more and 520 mW or less. Therefore, in consideration of the dispersion of the amorphous silicon layer thickness deposited in the current process, the thickness of the amorphous silicon layer deposited on the substrate is preferably 390 kPa or more and 530 kPa or less.

4 is a flowchart illustrating a process of manufacturing a polycrystalline silicon thin film transistor according to another preferred embodiment of the present invention, and FIGS. 5 to 13 are cross-sectional views illustrating a process of manufacturing the polycrystalline silicon thin film transistor according to the flowchart of FIG. 4. . Hereinafter, a manufacturing process of a polycrystalline silicon thin film transistor will be described with reference to the drawings.

First, as shown in FIG. 5, the substrate 100 is cleaned and then the buffer layer 110 is formed using silicon oxide or the like. The buffer layer 110 serves to prevent impurities from penetrating into the silicon layer formed thereon. After the buffer layer 110 is formed, an amorphous silicon layer 120 is formed thereon by chemical vapor deposition (CVD) or sputtering, and then the amorphous silicon layer 120 is converted into the polycrystalline silicon layer 122. . Of course, in forming the amorphous silicon layer 120, the thickness T is preferably 390 kPa or more and 530 kPa or less as described above.

The polycrystallization process of the amorphous silicon layer 129 is divided into a low temperature process and a high temperature process according to the process temperature. However, the high temperature process is required to use the expensive quartz substrate having a high thermal resistance because the temperature conditions above the deformation temperature of the substrate is used, and thus the low temperature process is mainly used. The low temperature process may be classified into laser annealing, metal induced crystallization (MIC), and the like, and the laser is irradiated to the amorphous silicon layer 120 as shown in FIG. 6. Eximer laser annealing, which melts into a liquid phase and grows the grain while cooling, or the grains of polycrystalline silicon are perpendicular to the interface at the boundary between the liquid region where the laser is irradiated and the solid region where the laser is not irradiated The polycrystalline silicon layer 122 is formed using a sequential lateral solidification process using the fact that it grows.

After the polycrystalline silicon layer 122 is formed as described above, the polycrystalline silicon layer 122 is patterned as shown in FIG. 7 through a photolithography process.

After patterning the polycrystalline silicon layer 122, as illustrated in FIG. 8, silicon oxide (SiO ₂ ) or silicon nitride (SiN _x ) is deposited on the entire surface of the substrate to form a gate insulating layer 130. As illustrated in FIG. 9, the gate electrode 140 is formed on the channel region 124c of the semiconductor layer 122 by patterning and depositing a conductive material for gate wiring.

After the gate electrode 140 is formed, n-type or p-type impurities are ion-implanted and activated in the semiconductor layer 122 using the gate electrode 140 as a mask to activate the channel region ( Source regions 124a and drain regions 124b are formed on both sides of 124c.

After the source region 124a and the drain region 124b are formed, an interlayer insulating layer 150 is formed to form a gate wiring including the gate electrode 140 as shown in FIG. 11, and a data line and a source electrode to be formed later. And data wirings including drain electrodes. The interlayer insulating layer 150 may be formed by growing an a-Si: C: O film or an a-Si: O: F film by chemical vapor deposition (CVD), or may be formed by applying an organic insulating material.

Then, contact holes exposing the source region 124a and the drain region 124b of the silicon layer by patterning the interlayer insulating layer 150 and the gate insulating layer 130 using a photolithography process as shown in FIG. 12. 150a and 150b are formed. Finally, as shown in FIG. 13, a metal for data wiring such as chromium (Cr) or molybdenum (Mo) is deposited and patterned to form a data wiring including a source electrode 160a and a drain electrode 160b. In this case, the source electrode 160a and the drain electrode 160b are connected to the source region 124a and the drain region 124b through the contact holes 150a and 150b, respectively. Of course, an a-Si: C: O film or an a-Si: O: F film may be formed on the upper portion by chemical vapor deposition (CVD) to form a protective film for protecting the thin film transistor.

As described above, by manufacturing a thin film transistor having a thickness of 390 kPa or more and 530 kPa or less, a thin film transistor having improved uniformity in current characteristics can be obtained.

FIG. 14 is a circuit diagram schematically illustrating a circuit of a plurality of sub-pixels disposed on a substrate of an active matrix type EL display device according to another preferred embodiment of the present invention. FIG. 15 is a circuit diagram of FIG. Fig. 16 is a plan view of an active matrix type electroluminescence table value schematically showing part A of Figs. 14 and 15, and Fig. 17 shows a subpixel portion of an active matrix type electroluminescent display. Sectional drawing taken along P1-P7 of 16 is shown.

A flat panel display using an electroluminescent element has an advantage of being superior to other conventional display devices in terms of brightness, contrast, and viewing angle, and thus has been actively researched and developed. In particular, transistors are provided for each pixel to determine whether each pixel emits light or not. Attention has been paid to an active matrix type electroluminescent display for controlling a signal applied to each pixel.

14 and 15, each subpixel unit includes a first thin film transistor 210 driven by a driving circuit, a second thin film transistor 250 driven by the first thin film transistor, and the second thin film transistor. The display unit 260 is driven by.

The first source electrode 212 of the first thin film transistor 210 is connected to the driving circuit by the first conductive line 220, and the first gate electrode 211 of the first thin film transistor is the second conductive line 230. The first drain electrode 213 of the first thin film transistor is connected to the first capacitor electrode 241 of the storage capacitor and the second gate electrode 251 of the second thin film transistor 250. .

In the above configuration, it may be assumed that the first data line 220 transmits data and the second data line 230 corresponds to a scan line. The first transistor 210 serves as a switching transistor and the second transistor 250 serves as a driving TR. Of course, two or more transistors may be used in the selection driving circuit. Hereinafter, a case in which two transistors, a switching transistor and a driving transistor, are used will be described.

The second capacitor electrode 242 of the storage capacitor and the second source electrode 252 of the second thin film transistor are connected to the third conductive line 270, and the second drain electrode 253 of the second thin film transistor is a display unit ( It is connected to the first electrode 261 of 260. As can be seen from FIG. 17, the second electrode 262 of the display unit is disposed to face the first electrode 261 with a predetermined gap from the first electrode, and a light emitting layer (B) between the first electrode and the second electrode. 287b and intermediate layers 287a and 287c are disposed.

16 and 17 schematically show the physical structure of part A of FIGS. 14 and 15. For reference, FIG. 16 illustrates a first conductive wire 220, a first source electrode 212, a first gate electrode 211, a first drain electrode 213, and a second conductive wire 230 which are not illustrated in FIG. 17. 17, components not shown in FIG. 16, that is, a substrate 281, a buffer layer 282, a gate insulating film 283, an interlayer insulating film 284, a first protective film 285, and a first An intermediate layer 287a, a light emitting layer 287b, a second intermediate layer 287c, a second electrode 262, and a second passivation film 289 are shown.

When a voltage is applied to the first gate electrode 211 by the driving circuit, a conductive channel is formed in the semiconductor layer 280 connecting the first source electrode 212 and the first drain electrode 213. When charge is supplied to the first source electrode 212 by the conductive wire 220, the charge is transferred to the first drain electrode 213. When the amount of charge that determines the amount of light in the light emitting layer 287b is supplied to the third conductive line 270 by the driving circuit, and the charge is supplied to the second gate electrode 251 by the first drain electrode 213, the second amount is charged. The charge of the source electrode 252 moves to the first electrode 261 via the second drain electrode 253.

A detailed configuration of the subpixel unit will be described with reference to FIG. 17. P1 through P2 show the display unit 260 of the subpixel unit, P2 through P3 show the second thin film transistor 250, and P3 through P7 show the storage capacitor 240.

A buffer layer 282 is formed on the entire surface of the substrate 281 shown in FIG. 17, and the second thin film transistor 250 having a thickness of the semiconductor layer as described above is 390 kPa to 530 kPa. A first passivation layer 285 is formed to cover the second thin film transistor 250 entirely, and a contact hole is formed in a portion corresponding to the second drain electrode 253 of the first passivation layer 285. The first electrode 261 is formed in a predetermined region including the region where the contact hole is formed. The first electrode 261 is connected to the second drain electrode 253 of the second thin film transistor through a contact hole formed in the first insulating layer.

A first intermediate layer 287a is entirely formed on the first electrode 261, and a light emitting layer 287b is formed on the first intermediate layer positioned on the display unit 260, and is not covered by the light emitting layer 287b and the light emitting layer. On the first intermediate layer, the second intermediate layer 287c is entirely formed. The second electrode 262 is entirely formed on the second intermediate layer 287c. A second passivation layer 289 may be formed on the second electrode 262 as necessary.

When the EL device is a bottom emission type, the substrate 281, the buffer layer 282, the gate insulating film 283, the interlayer insulating film 284, the first protective film 285, the first electrode 261 and the first intermediate layer ( 287a and the second intermediate layer 287c are formed of a transparent material, and the second electrode 262 includes lithium (Li), magnesium (Mg), aluminum (Al), aluminum-lidium (Al-Li), and calcium (Ca). ), Magnesium-indium (Mg-In), magnesium-silver (Mg-Ag) and the like. When the electroluminescent device is a top emission type, the first electrode 261 is formed of a metal material having good light reflectance, and includes a first intermediate layer 287a, a second intermediate layer 287c, a second electrode 262, and a first electrode. The protective film 289 may be formed of a transparent material. The electroluminescent device according to the present invention may be a bottom emitting type or a top emitting type, and the light generated in the electroluminescent element may be emitted through at least one of the first electrode and the second electrode. When the first electrode or the second electrode is transparent, the electrode may be formed of ITO or the like.

The display unit 260 is provided between the first electrode 261, the second electrode 262, and the first electrode and the second electrode which are supplied with charges from the second drain electrode 253 of the second thin film transistor 250. A light emitting layer 287b interposed therebetween, and intermediate layers 287a and 287c interposed between at least one of the first and second electrodes and the light emitting layer.

Examples of the material for forming the light emitting layer include phthalocyanine (CuPc: copper phthalocyanine), N, N-di (naphthalen-1-yl) -N, N'-diphenyl-benzidine (N, N'-Di (naphthalene-1- Low molecular organic materials such as yl) -N, N'-diphenyl-benzidine (NPB), tris-8-hydroxyquinoline aluminum (Alq3), or poly-phenylenevinylene (PPV) -based and polyfluorene A polymer organic material such as a (polyfluorene) -based or the like is used, and when an electric charge is supplied to the first electrode and the second electrode, an exciton is generated by combining holes and electrons, and this exciton is in a ground state in an excited state. The light emitting layer emits light as it changes to. The light emitting layer includes a poly (1,4-phenylenevinylene) derivative, nile red, and 4- (dicyanomethylene) -2-methyl-6- (Juloli), which causes the light emitting layer to emit red light. Din-4-yl-vinyl) -4H-pyran (DCM2), 2,3,7,8,12,13,17,18-octaethyl, 21H, 23H-phosphine platinum (II) (PEOEP), 4 10, which allows the light emitting layer to emit green light, such as (dicymethylene) -2-tertbutyl-6- (1,1,7,7-tetramethylzololidyl-9-enyl) -4H-pyran -(2-benzothiazolyl) -2,3,6,7-tetrahydro-1,1,7,7-tetramethyl-1H, 5H, 11H- [1] benzopyrano [6,7,8- ij] quinolizine (C545T), tri (8-hydroxyquinolato) aluminum (Alq3), tris (2- (2-pyridylphenyl-C, N)) iridium (II) (Ir) ppy, and the like, Or fluorene-based polymers, spirofluorene-based polymers, or dicarbazole stilbenes (DCS) (also called "bis [carbazole- (9)]-stilbenes), which cause the light emitting layer to emit blue light. Carbazole low molecular weight, 4,4'-bis (2,2'-diphenylethen-1-yl ) Biphenyl {4,4'-Bis (2,2'-diphenylethen-1-yl) biphenyl} (DPBVi) N, N'-bis (naphthalen-1-yl) -N, N-bis (phenyl) benzidine {N, N'-Bis (naphthalene-1-yl) -N, N'-bis (phenyl) benzidine} (α-NPD) and the like.

Each of the first and second intermediate layers may include an electric charge injection layer formed of a component for smoothly injecting charges and / or an electric charge transfer layer for smoothly transferring charges. . The charge injection layer may be divided into an electron injection layer (EIL) and a hole injection layer (HIL), and the charge transport layer may be an electron transport layer (ETL) and a hole transport layer (HTL). hole transfer layer). The electron injection layer may be formed of lithium fluoride, calcium, barium, and the like.

The storage capacitor 240 includes a lower electrode 241 and an upper electrode 242. The lower electrode 241 may be integrally formed with the second gate electrode 251, and the upper electrode 242 may be a second electrode. It may be integrally formed with the source electrode 252. The storage capacitor 240 functions to maintain current to the first electrode 261 or to improve driving speed.

When the first electrode is an anode and the second electrode is a cathode, the first intermediate layer 287a becomes a hole injection layer or a transport layer, and the second intermediate layer 287c becomes an electron injection layer or an electron transport layer. The hole injection layer may be formed of CuPc or Starburst type amines such as TCTA, m-MTDATA, m-MTDAPB, and the hole transport layer is N, N'-bis (3-methylphenyl) -N, N ' -Diphenyl- [1,1-biphenyl] -4,4'-diamine (TPD), N, N'-di (naphthalen-1-yl) -N, N'-diphenylbenzidine, N, N ' -Di (naphthalene-1-yl) -N, N'-diphenyl-benxidine (α-NPD) and the like, the electron injection layer is LiF, NaCl, CsF, Li2O, BaO, etc., the electron transport layer A oxazole compound, isoxazole compound, triazole compound, isothiazole compound, oxadiazole compound, thiadiazole compound, perylene compound, aluminum complex (e.g. Alq3 (tris (8-quinolinolato) -aluminum (tris (8-quinolinolato) -aluminium) BAlq, SAlq, Almq3, gallium complexes (e.g. Gaq'2OPiv, Gaq'2OAc, 2 (Gaq'2)) It can be formed as.

On the other hand, when the electroluminescent device according to the present invention is a bottom emission type, the first electrode 261 is formed of a transparent and conductive material such as ITO, the second electrode 262 is lithium (Li) with good reflectivity and conductivity ), Magnesium (Mg), aluminum (Al), aluminum-lidium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag) and the like. On the contrary, when the electroluminescent device according to the present invention is a top emission type, the first electrode is lithium (Li), magnesium (Mg), aluminum (Al), aluminum-lidium (Al-Li), calcium (Ca) having good reflectivity. ), Magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), and the like, and the second electrode is formed of a transparent and conductive material such as ITO.

In constructing the active matrix electroluminescent display device as described above, by using a thin film transistor having a semiconductor layer having a thickness of 390 kHz to 530 Å as described above, the uniformity of luminance is improved and the electroluminescence display in which an unevenness does not appear in an image. The device can be implemented.

In addition, as shown in FIG. 14, the data driver 202 and the scan driver 203 provided with the driving circuit for controlling the signal applied to the light emitting region have a thickness of 390 Å to 530 Å as described above. By using the thin film transistor, the performance of the flat panel display can be improved.

As an example for describing the present invention, the above embodiments have been described with respect to a top gate type thin film transistor and an electroluminescent display having the same, but the present invention is not limited thereto. For example, the present invention may be applied to a bottom gate type thin film transistor, and may be configured in various modifications, such as to be applied to a liquid crystal display of an electroluminescent display.

According to the thin film transistor of the present invention, a method of manufacturing the same, and an electroluminescent display using the same, the following effects can be obtained.

First, it is possible to manufacture a polycrystalline silicon thin film transistor with uniform current characteristics.

Second, by fabricating an active matrix type electroluminescent display device using polycrystalline silicon thin film transistors with uniform current characteristics, it is possible to manufacture an active matrix type electroluminescent display device having high quality and improved image quality with no spots. do.

Although the present invention has been described with reference to the embodiments shown in the drawings, these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (6)

Board; An active layer having a thickness of about 390 kPa to about 530 kPa formed on the substrate; A gate electrode provided to correspond to the channel region of the active layer; A gate insulating film insulating the active layer from the gate electrode; And And a source electrode and a drain electrode connected to the active layer. Depositing an amorphous silicon layer having a thickness of approximately 390 kPa to 530 kPa on the substrate; Crystallizing the amorphous silicon layer to form a polycrystalline silicon layer; Forming a gate insulating film on the polycrystalline silicon layer; Forming a gate electrode on the gate insulating film; Activating the polycrystalline silicon layer; And Stacking an intermediate layer on which a contact hole is formed over the entire surface of the substrate, and then forming a source electrode and a drain electrode thereon. The method of claim 2, The crystallization is a thin film transistor manufacturing method characterized in that using a laser. A light emitting area having a plurality of pixels; And And a selection driving circuit provided for each pixel. Each said selection drive circuit, Board; An active layer having a thickness of about 390 kPa to about 530 kPa formed on the substrate; A gate electrode provided to correspond to the channel region of the active layer; A gate insulating film insulating the active layer from the gate electrode; And And at least one thin film transistor including a source electrode and a drain electrode connected to the active layer. The method of claim 4, wherein A driving circuit for controlling a signal applied to the light emitting area; The control drive circuit, Board; An active layer having a thickness of about 390 kPa to about 530 kPa formed on the substrate; A gate electrode provided to correspond to the channel region of the active layer; A gate insulating film insulating the active layer from the gate electrode; And And at least one thin film transistor including a source electrode and a drain electrode connected to the active layer. The method according to claim 4 or 5, The image display device including the light emitting area of the flat panel display device is an electroluminescent device.

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