KR20060000287A - Thin film transistor array substrate and fabricating method thereof - Google Patents

Abstract

The present invention relates to a thin film transistor array substrate capable of preventing a voltage drop at a reference voltage level due to line resistance and a method of manufacturing the same.

The thin film transistor array substrate according to the present invention includes a liquid crystal cell driven by a horizontal electric field; Supply lines formed at both ends of the substrate and supplying a reference voltage to the liquid crystal cell; And at least one dummy supply line formed between the first and second supply lines and supplying a reference voltage to the liquid crystal cell.

Description

Thin Film Transistor Array Substrate and its Manufacturing Method {THIN FILM TRANSISTOR ARRAY SUBSTRATE AND FABRICATING METHOD THEREOF}             

1 is a plan view illustrating a conventional horizontal field applied thin film transistor array substrate.

FIG. 2 is a circuit diagram illustrating a supply line for supplying a reference voltage to the common line illustrated in FIG. 1.

3 is a circuit diagram illustrating a horizontal field application liquid crystal display panel according to the present invention.

4A and 4B are plan and cross-sectional views illustrating a case in which the dummy supply line illustrated in FIG. 3 is formed of a transparent conductive material.

5A and 5B are plan and cross-sectional views illustrating a case in which the dummy supply line shown in FIG. 3 is formed of data metal.

6A and 6B are plan and cross-sectional views illustrating a case in which the dummy supply line illustrated in FIG. 3 is formed of a gate metal.

7A to 7C are plan views and cross-sectional views illustrating one embodiment of a supply pad connected to the dummy supply line illustrated in FIG. 3.                 

8A and 8B are a plan view and a cross-sectional view showing another embodiment of a supply pad connected to the dummy supply line shown in FIG. 3.

9A to 9D are plan and cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to the present invention.

<Description of Symbols for Main Parts of Drawings>

6,106: gate electrode 8,108: source electrode

10,110 drain electrode 18,118 protective film

22,122: pixel electrode 24,124: common electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array substrate using a horizontal electric field, and more particularly, to a thin film transistor array substrate capable of preventing a voltage drop at a reference voltage level due to line resistance and a method of manufacturing the same.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. Such liquid crystal display devices are classified into vertical electric field types and horizontal electric field types according to the direction of the electric field for driving the liquid crystal.

In the vertical field type liquid crystal display, the common electrode formed on the upper substrate and the pixel electrode formed on the lower substrate are disposed to face each other to drive the liquid crystal of TN (Twisted Nemastic) mode by a vertical electric field formed therebetween. Such a vertical field type liquid crystal display device has a large aperture ratio, but has a narrow viewing angle of about 90 degrees.

In the horizontal field type liquid crystal display, an in-plane switching (IPS) mode liquid crystal is driven by a horizontal electric field between a pixel electrode and a common electrode arranged side by side on a lower substrate. The horizontal field type liquid crystal display device has an advantage that a viewing angle is about 160 degrees. Hereinafter, the horizontal field type liquid crystal display device will be described in detail.

1 is a plan view illustrating a thin film transistor array substrate of a conventional horizontal field type liquid crystal display panel.

Referring to FIG. 1, a thin film transistor array substrate of a conventional horizontal field type liquid crystal display panel includes a gate line GL and a data line DL intersected on a lower substrate, a thin film transistor TFT formed at each intersection thereof, The pixel electrode 22 and the common electrode 24 formed to form a horizontal electric field in the pixel region provided with the cross structure are provided, and the common line CL connected with the common electrode 24 is provided.

The gate line GL supplies a gate signal to the gate electrode 6 of the thin film transistor TFT. The data line DL supplies a pixel signal to the pixel electrode 22 through the drain electrode 10 of the thin film transistor TFT. The gate line GL and the data line DL are formed in an intersecting structure to define the pixel region 5. The common line CL is formed parallel to the gate GL with the pixel region 5 interposed therebetween, and supplies a reference voltage for driving the liquid crystal to the common electrode 24.

The thin film transistor TFT keeps the pixel signal of the data line DL charged and maintained in the pixel electrode 22 in response to the gate signal of the gate line GL. For this purpose, the thin film transistor TFT includes a gate electrode 6 connected to the gate line GL, a source electrode 8 connected to the data line DL, and a drain electrode connected to the pixel electrode 22. 10). In addition, the thin film transistor TFT further includes an active layer forming a channel between the source electrode 8 and the drain electrode 10, and an ohmic contact layer for ohmic contact with the source electrode 8 and the drain electrode 10. do.

The pixel electrode 22 is formed in the pixel region by being connected to the drain electrode 10 of the thin film transistor TFT through the pixel contact hole 20 penetrating the passivation layer. In particular, the pixel electrode 22 is formed to be connected to the drain electrode 10 and formed in parallel with the adjacent gate line GL, and to protrude in parallel with the common electrode 24 from the horizontal portion 22a. The finger part 22b is provided.

The common electrode 24 is connected to the common line CL and is formed in the pixel area. In particular, the common electrode 24 is formed in the pixel region 5 to be parallel to the finger portion 22b of the pixel electrode 22.

Accordingly, a horizontal electric field is formed between the pixel electrode 22 supplied with the pixel signal through the thin film transistor TFT and the common electrode 24 supplied with the reference voltage through the common line CL. In particular, a horizontal electric field is formed between the finger portion 22b of the pixel electrode 22 and the common electrode 24. The horizontal electric field causes liquid crystal molecules arranged in a horizontal direction between the thin film transistor array substrate and the color filter array substrate to rotate by dielectric anisotropy. According to the degree of rotation of the liquid crystal molecules, the light transmittance passing through the pixel region is changed, thereby realizing an image.

In order to supply a reference voltage to the conventional common line CL, as illustrated in FIG. 2, a supply line SL is formed on the left side and / or the right side of the substrate in parallel with the data line DL. The reference voltage is supplied to the liquid crystal cell Clc through the common line CL connected to the supply line SL. However, the reference voltage supplied to the liquid crystal cell Clc positioned at the center of the substrate relatively far from the supply line SL and the outer portion of the substrate 1 relatively close to the supply line SL are provided. The reference voltage supplied to the positioned liquid crystal cell Clc is different. In other words, as the distance from the supply line SL increases, the line resistance increases, so that the reference voltage level is relatively low. Accordingly, there is a problem in that image quality deterioration such as afterimage or flicker occurs due to the difference in the reference voltage level according to the position of the liquid crystal cell. In the case of high resolution panels, the number of liquid crystal cells Clc is also increased, so that the reference voltage is more unstable due to the line resistance, and the image quality is more noticeable.

Accordingly, an object of the present invention is to provide a thin film transistor array substrate and a method of manufacturing the same, which can prevent a voltage drop of a reference voltage level due to line resistance.

In order to achieve the above object, a thin film transistor array substrate according to an embodiment of the present invention comprises a liquid crystal cell driven by a horizontal electric field; Supply lines formed at both ends of the substrate and supplying a reference voltage to the liquid crystal cell; And at least one dummy supply line formed between the first and second supply lines and supplying a reference voltage to the liquid crystal cell.

A thin film transistor connected to the pixel electrode of the liquid crystal cell; A gate line connected to the gate electrode of the thin film transistor; A data line crossing the gate line to provide a pixel area; And a common line connected to the supply line and the dummy supply line to supply a reference voltage to the common electrode of the liquid crystal cell.

The at least one dummy supply line may be formed in parallel with the data line.

The at least one dummy supply line may be formed of the same material as any one of the gate line, the data line, and the pixel electrode.

And a contact hole penetrating at least one layer of the insulating layer covering at least one of the common electrode and the common line to connect the dummy supply line with at least one of the common electrode and the common line. do.

And a connection pattern for interconnecting the dummy supply lines of adjacent liquid crystal cells through the contact hole.

In order to achieve the above object, a method of manufacturing a thin film transistor array substrate having a liquid crystal cell driven by a horizontal electric field according to the present invention is to form a supply line on each of both ends of the substrate to supply a reference voltage to the liquid crystal cell Steps; And forming at least one dummy supply line between the first and second supply lines to supply a reference voltage to the liquid crystal cell.

The thin film transistor array substrate manufacturing method includes a first conductive pattern group including a gate line, a gate electrode connected to the gate line, a common line parallel to the gate line, and a common electrode connected to the common line on the substrate. Forming; Forming a gate insulating film on the substrate on which the first conductive pattern group is formed; Forming a semiconductor pattern on the gate insulating film; A second conductive pattern group including a data line defining a pixel region crossing the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode on the gate insulating layer on which the semiconductor pattern is formed; Making a step; Forming a protective film on the substrate on which the second conductive pattern group is formed; And forming a pixel electrode forming a horizontal electric field with the common electrode on the passivation layer.

The at least one dummy supply line may be formed of the same material as any one of the gate line, the data line, and the pixel electrode.

The method of manufacturing the thin film transistor array substrate may further include forming a contact hole through the gate insulating layer and the passivation layer to connect at least one of the common electrode and the common line and the dummy supply line. .

The method of manufacturing the thin film transistor array substrate may further include forming a connection pattern for interconnecting dummy supply lines of adjacent liquid crystal cells through the contact hole.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 9D.

3 is a circuit diagram illustrating a horizontal field application liquid crystal display panel according to the present invention.

Referring to FIG. 3, the horizontal field application type liquid crystal display panel according to the present invention includes n gate lines GL1 to GLn, m data lines DL1 to DLm crossing the n gate lines, and a gate. A thin film transistor TFT formed at the intersection of the line GL and the data line DL, the liquid crystal cells Clc connected to the thin film transistor TFT and arranged in a matrix form, the gate line GL, N common lines CL1 to CLn, and a supply line SL and a dummy supply line DSL for supplying a reference voltage to the common line CL.

The gate line GL supplies a gate signal to the gate electrode 106 of the thin film transistor TFT as shown in FIG. 4A. The data line DL supplies the pixel signal to the pixel electrode 122 through the thin film transistor TFT. The common line CL supplies a reference voltage for driving the liquid crystal to the common electrode 124.

The thin film transistor TFT keeps the pixel signal of the data line DL charged and maintained in the pixel electrode 122 in response to the gate signal of the gate line GL. To this end, the thin film transistor TFT includes a gate electrode 106 connected to the gate line GL, a source electrode 108 connected to the data line DL, and a drain electrode connected to the pixel electrode 122. 110). In addition, the thin film transistor TFT further includes an active layer forming a channel between the source electrode 108 and the drain electrode 110, and an ohmic contact layer for ohmic contact with the source electrode 108 and the drain electrode 110. do.

The pixel electrode 122 is connected to the drain electrode 110 of the thin film transistor TFT through the pixel contact hole 120 penetrating the passivation layer 118 and is formed in the pixel region 105. In particular, the pixel electrode 122 is connected to the drain electrode 110 and is formed to be parallel to the adjacent gate line GL, and is formed to protrude in parallel with the common electrode 124 from the horizontal part 122a. The finger part 122b is provided.

The common electrode 124 is connected to the common line CL and is formed in the pixel area. In particular, the common electrode 124 is formed to be parallel to the finger portion 122b of the pixel electrode 122 in the pixel region 105.

Accordingly, a horizontal electric field is formed between the pixel electrode 122 supplied with the pixel signal through the thin film transistor TFT and the common electrode 124 supplied with the reference voltage through the common line CL. In particular, a horizontal electric field is formed between the finger portion 122b of the pixel electrode 122 and the common electrode 124. The horizontal electric field causes liquid crystal molecules arranged in a horizontal direction between the thin film transistor array substrate and the color filter array substrate to rotate by dielectric anisotropy. According to the degree of rotation of the liquid crystal molecules, the light transmittance passing through the pixel region is changed, thereby realizing an image.

On the other hand, the supply line SL for supplying the reference voltage generated by the power supply unit (not shown) to the common line CL is connected to the first to nth common lines CL1 to CLn. The supply line SL is formed on the right side of the substrate 101 parallel to the data line DL and on the right side of the substrate 101 parallel to the data line DL. The second supply line SL2 is included. At least one dummy supply line DSL parallel to the data line DL is formed between the first and second supply lines SL1 and SL2. Here, at least one dummy supply line DSL is formed between the first and second supply lines SL1 and SL2 with a predetermined interval therebetween, and the dummy supply line DSL required as the size of the panel increases. The number is also increased. The dummy supply line DSL prevents a voltage difference between the liquid crystal cell positioned in the center of the panel generated by the line resistance and the reference voltage supplied to the liquid crystal cell positioned in the outer portion of the panel.

4 through 6 are plan and cross-sectional views illustrating various forms of the dummy supply line DSL illustrated in FIG. 3. The pixel electrode 122 is formed of a transparent conductive material on the passivation layer 118, and the common electrode 124 and the common line CL are formed of the same metal as the gate line GL. do.

As shown in FIGS. 4A and 4B, at least one dummy supply line DSL may be formed of the same material as the pixel electrode 122, for example, indium tin oxide, indium zinc oxide, and the like. It is formed of a transparent conductive material containing indium tin zinc oxide (Indium Tin Zinc Oxide). In this case, the dummy supply line DSL is connected to the common electrode 124 and / or the common line CL through the supply contact hole 150 penetrating through the protection film 118 and the gate insulating film 112. In addition, in order to prevent disconnection of the dummy supply line DSL and the pixel electrode 122, the width of the horizontal portion 122a of the pixel electrode adjacent to the dummy supply line DSL is smaller than the width of the horizontal portion of the other pixel electrode.

As shown in FIGS. 5A and 5B, at least one dummy supply line DSL includes data identical to the data line DL, for example, copper (Cu), chromium (Cr), molybdenum (Mo), and the like. It is formed of metal. In this case, the dummy supply line DSL is connected to the common electrode 124 and / or the common line CL through the supply contact hole 152 penetrating through the gate insulating film 112.

As shown in FIGS. 6A and 6B, at least one dummy supply line DSL is made of the same metal as the gate line GL, for example, copper (Cu), aluminum (Al), aluminum neodymium (AlNd), an aluminum alloy, or the like. It is formed of a gate metal comprising a. In this case, the dummy supply line DSL is directly connected to the common electrode 124 and the common line CL. The dummy supply lines DSL are connected to each other through the connection pattern 158 with the gate line GL interposed therebetween. In other words, the dummy dummy supply line DSL exposed through the first supply contact hole 154 penetrating the gate insulating film 112 and the second supply contact hole 156 penetrating the gate insulating film 112 are exposed. The current stage dummy supply line DSL is connected to each other through a connection pattern 158 formed of data metal.

The supply pad 170 connected to the dummy supply line DSL may include a supply pad lower electrode 172 connected to the dummy supply line DSL made of a gate metal or a data metal, as shown in FIGS. 7A to 7C. ; A gate insulating film 112 and / or a protective film 118 having a pad contact hole 174 exposing the supply pad lower electrode 172; The supply pad upper electrode 176 is connected to the supply pad lower electrode 172 through the pad contact hole 174. Alternatively, as illustrated in FIGS. 8A and 8B, a supply pad electrode 178 is directly connected to a dummy supply line DSL made of a transparent conductive material formed on the passivation layer 118.

The supply pad 170 is positioned between the data pads 160 and is supplied with a reference voltage through a dummy pad of a tape carrier package (TCP) connected to the data pad 170.

9A to 9D illustrate a manufacturing method using the thin film transistor array substrate illustrated in FIGS. 4A and 4B as an example.

Referring to FIG. 9A, a first conductive pattern group including a gate line 102, a gate electrode 106, a common line CL, and a common electrode 124 is formed on the lower substrate 101.

In detail, the gate metal layer is formed on the lower substrate 101 through a deposition method such as a sputtering method. Here, the gate metal layer is formed in at least one layer structure including aluminum (Al) -based metal, copper (Cu), chromium (Cr), molybdenum (Mo) and the like. For example, the gate metal layer is formed in a two-layer structure in which aluminum / neodium (AlNd) and molybdenum (Mo) are sequentially stacked. The gate metal layer is patterned by a photolithography process and an etching process to form a first conductive pattern group including the gate line 102, the gate electrode 106, the common line CL, and the common electrode 124.

Referring to FIG. 9B, a gate insulating film 112 is formed on the lower substrate 101 on which the first conductive pattern group is formed. A semiconductor pattern including an active layer and an ohmic contact layer is formed on the gate insulating layer 112. A second conductive pattern group including a source electrode 108, a drain electrode 110, and a data line DL is formed on the gate insulating layer 112 on which the semiconductor pattern is formed.

In detail, the gate insulating layer 112, the first and the second semiconductor layers are sequentially formed on the lower substrate 101 on which the first conductive pattern group is formed through a deposition method such as PECVD or sputtering. Herein, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the material of the gate insulating film 112; Organic insulating materials such as benzocyclobutene (BCB), acryl (acryl) resin, and perfluorocyclobutene (PFCB) are used. As the first semiconductor layer, amorphous silicon that is not doped with impurities is used, and for the second semiconductor layer, amorphous silicon that is doped with N-type or P-type impurities is used. Then, the first and second semiconductor layers are patterned by a photolithography process and an etching process to form a semiconductor pattern including an active layer and an ohmic contact layer.

The data metal layer is sequentially formed on the gate insulating film 112 on which the semiconductor pattern is formed through a deposition method such as sputtering. Here, copper (Cu), molybdenum (Mo), titanium (Ti), tantalum (Ta), molybdenum alloy (Mo alloy) and the like are used as the data metal layer. The data metal layer is patterned by a photolithography process and an etching process to form a second conductive pattern group including the data line 104, the source electrode 108, and the drain electrode 110.

Then, the ohmic contact layer of the channel portion exposed by the source and drain electrodes 108 and 110 using the source electrode 108 and the drain electrode 110 as a mask is dry etched to expose the active layer of the channel portion.

Meanwhile, the semiconductor pattern and the second conductive pattern group may be simultaneously formed using a partial exposure mask including a diffraction mask and a transflective mask.

Referring to FIG. 9C, a passivation layer 118 including a pixel contact hole 120 and a supply contact hole 150 is formed on the gate insulating layer 112 on which the second conductive pattern group is formed.

To this end, the protective film 118 is entirely formed on the gate insulating film 112 on which the second conductive pattern group is formed by a deposition method such as PECVD. The passivation layer 118 may be formed of an inorganic insulating material such as the gate insulating film 112 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, (Benzocyclobutene), or perfluorocyclobutene (PFCB).

The passivation layer 118 is patterned by a photolithography process and an etching process to form the pixel contact hole 120 and the supply contact hole 150. The pixel contact hole 120 penetrates the passivation layer 118 to expose the drain electrode 110. The supply contact hole 150 passes through the passivation layer 118 and the gate insulating layer 112 to expose the common electrode 124.

Referring to FIG. 9D, a third conductive pattern group including the pixel electrode 122 and the dummy supply line DSL is formed on the passivation layer 118.

To this end, a transparent conductive film is coated on the protective film 118 by a deposition method such as sputtering. Here, the material of the transparent conductive film is indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO) or indium tin zinc oxide (ITZO). ) And the like are used. The transparent conductive film is patterned through a photolithography process and an etching process to form a third conductive pattern group including the pixel electrode 122 and the dummy supply line DSL. The pixel electrode 122 is connected to the drain electrode 110 of the thin film transistor through the pixel contact hole 120. The dummy supply line DSL is connected to the common electrode 124 through the common contact hole 150.

As described above, the thin film transistor array substrate and the method of manufacturing the same according to the present invention include at least one dummy supply line formed between the first and second supply lines formed on the substrate. Since the dummy supply line is connected through the common electrode and the contact hole, the difference in the common voltage level generated by the line resistance can be reduced, thereby preventing the deterioration of image quality such as afterimage and flicker. Furthermore, the thin film transistor array substrate and the method of manufacturing the same according to the present invention can reduce the voltage drop of the liquid crystal cell positioned in the center of the panel in a high resolution panel.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (11)

A liquid crystal cell driven by a horizontal electric field; Supply lines formed at both ends of the substrate and supplying a reference voltage to the liquid crystal cell; And at least one dummy supply line formed between the first and second supply lines and supplying a reference voltage to the liquid crystal cell. The method of claim 1, A thin film transistor connected to the pixel electrode of the liquid crystal cell; A gate line connected to the gate electrode of the thin film transistor; A data line crossing the gate line to provide a pixel area; And a common line connected to the supply line and the dummy supply line to supply a reference voltage to the common electrode of the liquid crystal cell. The method of claim 2, The at least one dummy supply line is formed in parallel with the data line. The method of claim 2, And the at least one dummy supply line is formed of the same material as any one of the gate line, the data line, and the pixel electrode. The method of claim 4, wherein And a contact hole penetrating at least one layer of the insulating layer covering at least one of the common electrode and the common line to connect the dummy supply line with at least one of the common electrode and the common line. A thin film transistor array substrate. The method of claim 5, And a connection pattern for interconnecting the dummy supply lines of adjacent liquid crystal cells through the contact hole. In the manufacturing method of a thin film transistor array substrate having a liquid crystal cell driven by a horizontal electric field, Forming supply lines at both ends of the substrate to supply a reference voltage to the liquid crystal cell; Forming at least one dummy supply line for supplying a reference voltage to the liquid crystal cell between the first and second supply lines. According to claim 7, Forming a first conductive pattern group including a gate line, a gate electrode connected to the gate line, a common line parallel to the gate line, and a common electrode connected to the common line on a substrate; Forming a gate insulating film on the substrate on which the first conductive pattern group is formed; Forming a semiconductor pattern on the gate insulating film; A second conductive pattern group including a data line defining a pixel region crossing the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode on the gate insulating layer on which the semiconductor pattern is formed; Making a step; Forming a protective film on the substrate on which the second conductive pattern group is formed; And forming a pixel electrode forming a horizontal electric field with the common electrode on the passivation layer. The method of claim 8, And the at least one dummy supply line is formed of the same material as any one of the gate line, the data line, and the pixel electrode. The method of claim 9, And forming a contact hole through the gate insulating layer and the passivation layer to connect at least one of the common electrode and the common line and the dummy supply line. The method of claim 10, And forming a connection pattern for interconnecting the dummy supply lines of adjacent liquid crystal cells through the contact hole.

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